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Add that and move them to the adreno func table. Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support") Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 42 +++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++++- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 4 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 5 files changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 690d3e53e273..b41dbca1ebc6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -91,10 +91,10 @@ bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) } =20 /* Check to see if the GX rail is still powered */ -bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) +bool a6xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) { - struct a6xx_gpu *a6xx_gpu =3D container_of(gmu, struct a6xx_gpu, gmu); - struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; u32 val; =20 /* This can be called from gpu state code so make sure GMU is valid */ @@ -117,6 +117,40 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); } =20 +bool a7xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) +{ + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + u32 val; + + /* This can be called from gpu state code so make sure GMU is valid */ + if (!gmu->initialized) + return false; + + val =3D gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); + + return !(val & + (A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | + A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); +} + +bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) +{ + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + u32 val; + + /* This can be called from gpu state code so make sure GMU is valid */ + if (!gmu->initialized) + return false; + + val =3D gmu_read(gmu, REG_A8XX_GMU_PWR_CLK_STATUS); + + return !(val & + (A8XX_GMU_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | + A8XX_GMU_PWR_CLK_STATUS_GX_HM_CLK_OFF)); +} + void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, bool suspended) { @@ -240,7 +274,7 @@ static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *= gmu) =20 if (val =3D=3D local) { if (gmu->idle_level !=3D GMU_IDLE_STATE_IFPC || - !a6xx_gmu_gx_is_on(gmu)) + !adreno_gpu->funcs->gx_is_on(adreno_gpu)) return true; } =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 2af074c8e8cf..9f09daf45ab2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -10,6 +10,7 @@ #include #include #include "msm_drv.h" +#include "adreno_gpu.h" #include "a6xx_hfi.h" =20 struct a6xx_gmu_bo { @@ -231,7 +232,9 @@ void a6xx_hfi_stop(struct a6xx_gmu *gmu); int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu); int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index); =20 -bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); +bool a6xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu); +bool a7xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu); +bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); void a6xx_sptprac_disable(struct a6xx_gmu *gmu); int a6xx_sptprac_enable(struct a6xx_gmu *gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index f4b7fc28b677..8718919c7e19 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1643,7 +1643,7 @@ static void a6xx_recover(struct msm_gpu *gpu) =20 adreno_dump_info(gpu); =20 - if (a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) { + if (adreno_gpu->funcs->gx_is_on(adreno_gpu)) { /* Sometimes crashstate capture is skipped, so SQE should be halted here= again */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); =20 @@ -2762,6 +2762,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs =3D { .get_timestamp =3D a6xx_gmu_get_timestamp, .bus_halt =3D a6xx_bus_clear_pending_transactions, .mmu_fault_handler =3D a6xx_fault_handler, + .gx_is_on =3D a6xx_gmu_gx_is_on, }; =20 const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs =3D { @@ -2794,6 +2795,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = =3D { .get_timestamp =3D a6xx_get_timestamp, .bus_halt =3D a6xx_bus_clear_pending_transactions, .mmu_fault_handler =3D a6xx_fault_handler, + .gx_is_on =3D a6xx_gmu_gx_is_on, }; =20 const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { @@ -2828,6 +2830,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs =3D { .get_timestamp =3D a6xx_gmu_get_timestamp, .bus_halt =3D a6xx_bus_clear_pending_transactions, .mmu_fault_handler =3D a6xx_fault_handler, + .gx_is_on =3D a7xx_gmu_gx_is_on, }; =20 const struct adreno_gpu_funcs a8xx_gpu_funcs =3D { @@ -2855,4 +2858,5 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs =3D { .get_timestamp =3D a8xx_gmu_get_timestamp, .bus_halt =3D a8xx_bus_clear_pending_transactions, .mmu_fault_handler =3D a8xx_fault_handler, + .gx_is_on =3D a8xx_gmu_gx_is_on, }; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/= msm/adreno/a6xx_gpu_state.c index d2d6b2fd3cba..7bec4e509d2c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -1251,7 +1251,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gp= u, _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg, &a6xx_state->gmu_registers[2], false); =20 - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) + if (!adreno_gpu->funcs->gx_is_on(adreno_gpu)) return; =20 /* Set the fence to ALLOW mode so we can access the registers */ @@ -1608,7 +1608,7 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_g= pu *gpu) } =20 /* If GX isn't on the rest of the data isn't going to be accessible */ - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) + if (!adreno_gpu->funcs->gx_is_on(adreno_gpu)) return &a6xx_state->base; =20 /* Halt SQE first */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index c08725ed54c4..29097e6b4253 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -82,6 +82,7 @@ struct adreno_gpu_funcs { u64 (*get_timestamp)(struct msm_gpu *gpu); void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off); int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *= data); + bool (*gx_is_on)(struct adreno_gpu *adreno_gpu); }; =20 struct adreno_reglist { --=20 2.51.0