From nobody Thu Apr 2 20:08:14 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40B951A23A0 for ; Fri, 27 Mar 2026 00:14:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774570488; cv=none; b=APS5FPTneOB7gEcGALz5cXeqEYIXrQES2EQnxejAlof/GB1w+QEZhDPiIQGaCtyoHgXIeSb4axzF8Jg72EdV4Q2oUVyc/QreUNxZTT3cSS02Dx/Zck6RqPSj3iDnourE7tfLRIfZp/DSfU9NfGXTDf5gEAwsU3MQjzs1IExQm2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774570488; c=relaxed/simple; bh=4sNlSSX01xvTjnuR3bo4sHiMTLNkYzfz+0imYgUO+AY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CmqMZ85hO8SXp1CpE1NmOKl6NSpFEqD3mHOyl6EcnP1BSlW9Y6xPow5xnrO6Ci7+QWYHtoeommsQyqnKU87E2Pdym2CDXl4pTKRqhJnLVQHtuCAUpbPQxNcOJAXSaIUrgKDuxKyXO2pKWb4dQcN+kkteLS/cvvsYoLY0q9SSCss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YOjxcWib; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=WbVXkgS6; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YOjxcWib"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="WbVXkgS6" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62QI58WX1476152 for ; Fri, 27 Mar 2026 00:14:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ypVmLmZoKp0ZQrPOn04KrEzrtKR2UKnrkXkHej2c9lo=; b=YOjxcWib7A38DVxc RCQcQ7z/4YxztOfn10nn0ZsnYUllMs47RszsCGdPDpGmYQ9kXW/bmx64vabchvNa oirZ1J0kVlkXL4IQDEIPuGZp+mMN8Z8TgXqTM99Xjn1bpFJ7I8MTo5/c1UQwvHZm TFyXws0z3cypikMSuANfnaI6c/+6xSqL8OqB/fPuaxetLK9O6i/8HrQDnRHR7YEc Ul8jLRMmRL4xYYWLfBxuDW90tmMJbalvIpGtoQl9y6CJORgFrSYf5oycQhJDXeTc 5lLlSWFw2BkEsmXysjMBk+UbjECkiFk0E6GdUttS6PUHl7pFyNoYoq/tkm9KlmJW 3qjLuw== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d59s410qm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 27 Mar 2026 00:14:46 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-358f058973fso2169336a91.1 for ; Thu, 26 Mar 2026 17:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774570485; x=1775175285; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ypVmLmZoKp0ZQrPOn04KrEzrtKR2UKnrkXkHej2c9lo=; b=WbVXkgS6ImHMKe8dOJ5W3iSUuUl0mSRiaDJb8nO8mnNyM/dj436lwoPrPtkLbdcr+n a70R2devTGHNJQF+lZ7lWEhZolixn2W9BYeBuOX37b4xrjEj6dG0Xa0Q+b1y7Gew9umb 5HEF7wK6Q2T3E4Fx5M03uN+Gr1K/jWZPDK7lzV524WUtni3ZXc5F/krRwjaoeI5jJNrx /JcU1H0KN3OQCIbUjjzAxoCvWDXiju9Hx2cThs0i2tZP9RAe8sNVcZh5g7o4xEA/rUoE p1x4Hbhcv65yYluSEgwkHroqpR4hxuF173ogSdKF5V821Qds+U3twYKrQbkwJFAgBXD/ 0aCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774570485; x=1775175285; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ypVmLmZoKp0ZQrPOn04KrEzrtKR2UKnrkXkHej2c9lo=; b=p/ggDjuY8297pXYKNTKTPRTS2raKpoajWL1Y51Bu9hFiKD/S6hSN/+fJclfNcxQJ7e vdLspkxLraF1AYV4ChSv3JFj5GzZ4qco6NiQXtRrnJZfCoHqb+YPPt9EvjFp2tjrKX+k QiP8TI1sISMm+W8nODeRCnNestqCRr2HWTvU08Mjjc0VUAmMoNbzjBEct/p9EZU/PO0P Lay/mMcTRa+SJERukOuAwYl344AP+0EcDkKaTSTPg3aDF1zdROoiKsd3mScxgbrE3PcY MvMttY9i0j7QQM/4ibjYVFKE7+NqC7/MSOsMV3dgVF91QVAmAI0jyLv8xveFGQN91sDH 4egA== X-Forwarded-Encrypted: i=1; AJvYcCVYYCxGeqnLe4qL8v2cZoJAzEbcZsWlke5twDwwZMOPQ4ItW8dGKjSluDpTGr1VCXEvBxZu93WKQM0rbJk=@vger.kernel.org X-Gm-Message-State: AOJu0YwGWrFKGKhahgNdgD7Qgqajd34ugsSqFnq8ZStRH21sNYz3p5yX p1ze/vQEHPpbplEQGzt8pyr3q0F/0MOfSRJAkMGYzAstZoXo8BMed9+Bv/0Pjhs2ZySyt3G8DoS D9vlluAwuc+l9xSJOS00pkQ+bQyeZc+blmDA91cv3aXOwgoBAoRqB9X/JtZqx8CAo3WcjcVixYD g= X-Gm-Gg: ATEYQzxIDRXKfUwsyJ506mhM1uB/CZ3Ho1OKoCSz7BCRfi2RvsWkckpnlAv7vu65Yus UUl/NkURlY5IAy7/ec3onOxWecQz6go96IQghl/exbLN9YmxfMNjmwaqQUle1xaDGAmHTbn9EH0 /AtJIVXsmuI68cO0VzLaKUt8lvQxV4dN0d8pOhjJYvePWiHgTSIdoSFGfPTTzJnA6f+JiH7zHdy IwMlHm8qkQRjZehkFwKiR/vr5LS77xeUHis1I0x0jHBNKKt91n1VJlF4CyLcmoqnbWkiE8WvWkP BCGrNt0EBx9xrTBpA26yueDs/9lCWDKRKgb2WEH/0lvC6jHRUeQew5Qn4tb37rSFTSyg+pDgiCC DSuu+iYVN4U5b+445sQhQ9Hc8xpPDanTKNsxTPHKMI8wFrQ== X-Received: by 2002:a17:90b:4c8e:b0:340:4abf:391d with SMTP id 98e67ed59e1d1-35c300ba450mr459570a91.16.1774570484623; Thu, 26 Mar 2026 17:14:44 -0700 (PDT) X-Received: by 2002:a17:90b:4c8e:b0:340:4abf:391d with SMTP id 98e67ed59e1d1-35c300ba450mr459523a91.16.1774570484033; Thu, 26 Mar 2026 17:14:44 -0700 (PDT) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c2ec799eesm163155a91.10.2026.03.26.17.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 17:14:43 -0700 (PDT) From: Akhil P Oommen Date: Fri, 27 Mar 2026 05:43:51 +0530 Subject: [PATCH v2 02/17] drm/msm/a8xx: Fix the ticks used in submit traces Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-a8xx-gpu-batch2-v2-2-2b53c38d2101@oss.qualcomm.com> References: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com> In-Reply-To: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Connor Abbott , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774570466; l=9033; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=4sNlSSX01xvTjnuR3bo4sHiMTLNkYzfz+0imYgUO+AY=; b=46/uTwtLhlypkw7TNF9KlOd+hv8EjygBujiXy/XCtNsoC/2mP0dzG0gCljqXP/6drRoDQiOBf Wn90MhhodBCAulHMuH9eYe8SV+w2+Ds3RAkZ8yphS0rj7Fe/x37z5J/ X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Proofpoint-ORIG-GUID: vaBMDbVtD-6nA5Wl_bE7hSaSbpa4fsGQ X-Proofpoint-GUID: vaBMDbVtD-6nA5Wl_bE7hSaSbpa4fsGQ X-Authority-Analysis: v=2.4 cv=CoGys34D c=1 sm=1 tr=0 ts=69c5cbf6 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=e5mUnYsNAAAA:8 a=EUspDBNiAAAA:8 a=wZqpmLHwZRrC_MsAvYoA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI3MDAwMCBTYWx0ZWRfX81Ti9TWR8CUD LcuInalE1GY7PdEFP1RTZciYLYwrp+K204vcPYt9y/0YqrzvMA4suBlLquokjLV2Ny+r6IWKZtM 2hpWfRq560bTiPcvNbINB2o2mcHXabLYReA2+H09TqYZ66sq/PZ8eujGD4GMWmeOjrO7hFw/zo2 H7Yws0sYNzpyzKd70cdWZqjgSLttAXzWW8DW7FzTC4PTkNWhldFOiQvKz52UA3IBSD9+VfkFByq xL7zxLa8X7HLYs5vbEyaXjiU4MlibM4eQNARATvcg+HJPoolOnOBNBA6dJiKHpK7c7F6ZAhnp79 RiXlj2GIrWKvh6Ea1ZgcG9tZLyofUBrL61+ztMMESSLlJ/RK3teakw5PI4rumF0URHixoOznyfv ZvJvDQ2wEnPZORoaK54OoyVpdDVxNQNLXGVYGUyllYNzISm4PDB4E5P/iUgxLKYunZTK1fJrs5q 1gOSKQHRXkzBNopDAmg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-26_04,2026-03-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603270000 GMU_ALWAYS_ON_COUNTER_* registers got moved in A8x, but currently, A6x register offsets are used in the submit traces instead of A8x offsets. To fix this, refactor a bit and use adreno_gpu->funcs->get_timestamp() everywhere. While we are at it, update a8xx_gmu_get_timestamp() to use the GMU AO counter. Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 6 ++---- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 23 +++++++------------= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 20 ++++++++------------ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 6 ++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 6 ++++-- 8 files changed, 27 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.c index db06c06067ae..0ed8bf2b5dd5 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -604,11 +604,9 @@ static int a4xx_pm_suspend(struct msm_gpu *gpu) { return 0; } =20 -static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +static u64 a4xx_get_timestamp(struct msm_gpu *gpu) { - *value =3D gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO); - - return 0; + return gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO); } =20 static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_ra= te) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 56eaff2ee4e4..79a441e91fa1 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1435,11 +1435,9 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) return 0; } =20 -static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +static u64 a5xx_get_timestamp(struct msm_gpu *gpu) { - *value =3D gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO); - - return 0; + return gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO); } =20 struct a5xx_crashdumper { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 2129d230a92b..50bd7aa4e792 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -16,8 +16,10 @@ =20 #define GPU_PAS_ID 13 =20 -static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu) +static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); u64 count_hi, count_lo, temp; =20 do { @@ -404,7 +406,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); OUT_RING(ring, submit->seqno); =20 - trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu)); + trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu)); =20 a6xx_flush(gpu, ring); } @@ -614,7 +616,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) } =20 =20 - trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu)); + trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu)); =20 a6xx_flush(gpu, ring); =20 @@ -2414,20 +2416,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) return 0; } =20 -static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +static u64 a6xx_get_timestamp(struct msm_gpu *gpu) { - struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); - struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); - - *value =3D read_gmu_ao_counter(a6xx_gpu); - - return 0; -} - -static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) -{ - *value =3D gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); - return 0; + return gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); } =20 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 4eaa04711246..a4434a6a56dd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -320,7 +320,7 @@ int a6xx_zap_shader_init(struct msm_gpu *gpu); void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bo= ol gx_off); int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *dat= a); void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); -int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value); +u64 a8xx_gmu_get_timestamp(struct msm_gpu *gpu); u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate); int a8xx_gpu_feature_probe(struct msm_gpu *gpu); void a8xx_gpu_get_slice_info(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index b1887e0cf698..840af9c4d718 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -1174,23 +1174,19 @@ void a8xx_bus_clear_pending_transactions(struct adr= eno_gpu *adreno_gpu, bool gx_ gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); } =20 -int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) +u64 a8xx_gmu_get_timestamp(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + u64 count_hi, count_lo, temp; =20 - mutex_lock(&a6xx_gpu->gmu.lock); - - /* Force the GPU power on so we can read this register */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); - - *value =3D gpu_read64(gpu, REG_A8XX_CP_ALWAYS_ON_COUNTER); - - a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); - - mutex_unlock(&a6xx_gpu->gmu.lock); + do { + count_hi =3D gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H); + count_lo =3D gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_L); + temp =3D gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H); + } while (unlikely(count_hi !=3D temp)); =20 - return 0; + return (count_hi << 32) | count_lo; } =20 u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index d5fe6f6f0dec..785e99fb5bd5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -391,13 +391,11 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_= context *ctx, return 0; case MSM_PARAM_TIMESTAMP: if (adreno_gpu->funcs->get_timestamp) { - int ret; - pm_runtime_get_sync(&gpu->pdev->dev); - ret =3D adreno_gpu->funcs->get_timestamp(gpu, value); + *value =3D adreno_gpu->funcs->get_timestamp(gpu); pm_runtime_put_autosuspend(&gpu->pdev->dev); =20 - return ret; + return 0; } return -EINVAL; case MSM_PARAM_PRIORITIES: diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 1d0145f8b3ec..c08725ed54c4 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -79,7 +79,7 @@ struct adreno_gpu; struct adreno_gpu_funcs { struct msm_gpu_funcs base; struct msm_gpu *(*init)(struct drm_device *dev); - int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); + u64 (*get_timestamp)(struct msm_gpu *gpu); void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off); int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *= data); }; diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gp= u/drm/msm/registers/adreno/a6xx_gmu.xml index c4e00b1263cd..33404eb18fd0 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -141,8 +141,10 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/f= reedreno/ rules-fd.xsd"> - - + + + + --=20 2.51.0