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Thu, 26 Mar 2026 17:15:42 -0700 (PDT) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c2ec799eesm163155a91.10.2026.03.26.17.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 17:15:41 -0700 (PDT) From: Akhil P Oommen Date: Fri, 27 Mar 2026 05:44:01 +0530 Subject: [PATCH v2 12/17] drm/msm/a6xx: Add soft fuse detection support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-a8xx-gpu-batch2-v2-12-2b53c38d2101@oss.qualcomm.com> References: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com> In-Reply-To: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Connor Abbott , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774570466; l=7554; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=+byEdmpRPut/PppCg/aeg2HI1gNcH4PGDt6qcxhJrzs=; b=aaBMAs7lXVQf+5hQZSxyLVIMSWwSqvKuFZtydEx1bngukkKFVgksJW8GZye4hB9JUAF0lopT0 y+hHj3VQVvlASB5rK/3Eepnf4CTTaLYn2tZoewRMFbTC0gAxrbk1mDS X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Authority-Analysis: v=2.4 cv=A99h/qWG c=1 sm=1 tr=0 ts=69c5cc2f cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=V3uGv-Aa6LsVx7MfQ8cA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: 5E4QThF5WbigVow9BVA68zWyo7lYRYgQ X-Proofpoint-GUID: 5E4QThF5WbigVow9BVA68zWyo7lYRYgQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI3MDAwMCBTYWx0ZWRfX+/NvRTVUocmm RhzmpawXjtIkEcfFpghQMAhJzkeRwrQhYgEzwQB/RnZB0gmb9iNZAlXKYR2t6UZqLOewQcVMzIs 3EZ+Ms9Ud12MmZk2JbisZFn5I6CRJI0muynuvHkBI9wclYu/TQuLL64zAqk+iDd6UmQu27whfW3 LTV4V3uHr3u3MvSvp9i+0YkXkapr8I47HLItrBChfquYlb5JTvaaiJSR8wN1EAUoUDkXgIwVetS BiJ7yrIVl+uz/WXw6+LesY11lhKAC6QgVUD4MyhEnw34Ks4YLXmuOSZDld98FRiMt7i+0o+O7cb WaWykLQ8FCm+3E/0pu4ThEdPeD1irAhfO5J4GbGYVtoVFBZBf3AN5Xw6wQFxEcdRBu9GaaDhWkX w1pqoRVXpSdmoWOivHAqRNvdQ0dDjnuXlarb/ooE7Us7/Iuup2gGx2Hbw2IvQN9FN3ZbsJzlT7T 7fSBrg09yY8fZnd3k8g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-26_04,2026-03-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603270000 Recent chipsets like Glymur supports a new mechanism for SKU detection. A new CX_MISC register exposes the combined (or final) speedbin value from both HW fuse register and the Soft Fuse register. Implement this new SKU detection along with a new quirk to identify the GPUs that has soft fuse support. There is a side effect of this patch on A4x and older series. The speedbin field in the MSM_PARAM_CHIPID will be 0 instead of 0xffff. This should be okay as Mesa correctly handles it. Speedbin was not even a thing when those GPUs' support were added. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 ++++++++++++++++++++++-= ---- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 4 +++ 5 files changed, 45 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 79a441e91fa1..d7ed3225f635 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1731,6 +1731,7 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_devic= e *dev) struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; unsigned int nr_rings; + u32 speedbin; int ret; =20 a5xx_gpu =3D kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL); @@ -1757,6 +1758,11 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_devi= ce *dev) return ERR_PTR(ret); } =20 + /* Set the speedbin value that is passed to userspace */ + if (adreno_read_speedbin(&pdev->dev, &speedbin) || !speedbin) + speedbin =3D 0xffff; + adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); + msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, a5xx_fault_handler); =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 5cddfc03828f..fb9662b946d0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2546,13 +2546,33 @@ static u32 fuse_to_supp_hw(const struct adreno_info= *info, u32 fuse) return UINT_MAX; } =20 -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_i= nfo *info) +static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gp= u, + const struct adreno_info *info, u32 *speedbin) +{ + int ret; + + /* Use speedbin fuse if present. Otherwise, fallback to softfuse */ + ret =3D adreno_read_speedbin(dev, speedbin); + if (ret !=3D -ENOENT) + return ret; + + if (info->quirks & ADRENO_QUIRK_SOFTFUSE) { + *speedbin =3D a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMI= T_STATUS); + *speedbin =3D A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*spe= edbin); + return 0; + } + + return -ENOENT; +} + +static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx= _gpu, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; =20 - ret =3D adreno_read_speedbin(dev, &speedbin); + ret =3D a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine @@ -2586,11 +2606,13 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_dev= ice *dev) struct msm_drm_private *priv =3D dev->dev_private; struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; + const struct adreno_info *info =3D config->info; struct device_node *node; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; extern int enable_preemption; + u32 speedbin; bool is_a7xx; int ret, nr_rings =3D 1; =20 @@ -2613,14 +2635,14 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_dev= ice *dev) adreno_gpu->gmu_is_wrapper =3D of_device_is_compatible(node, "qcom,adreno= -gmu-wrapper"); =20 adreno_gpu->base.hw_apriv =3D - !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); + !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); =20 /* gpu->info only gets assigned in adreno_gpu_init(). A8x is included int= entionally */ - is_a7xx =3D config->info->family >=3D ADRENO_7XX_GEN1; + is_a7xx =3D info->family >=3D ADRENO_7XX_GEN1; =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 - ret =3D a6xx_set_supported_hw(&pdev->dev, config->info); + ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); @@ -2628,15 +2650,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_dev= ice *dev) } =20 if ((enable_preemption =3D=3D 1) || (enable_preemption =3D=3D -1 && - (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) + (info->quirks & ADRENO_QUIRK_PREEMPTION))) nr_rings =3D 4; =20 - ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_ri= ngs); + ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, info->funcs, nr_rings); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); } =20 + /* Set the speedbin value that is passed to userspace */ + if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || !speedbi= n) + speedbin =3D 0xffff; + adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); + /* * For now only clamp to idle freq for devices where this is known not * to cause power supply issues: diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 8475802fdde2..f6c39aed50f2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1185,7 +1185,6 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, struct msm_gpu_config adreno_gpu_config =3D { 0 }; struct msm_gpu *gpu =3D &adreno_gpu->base; const char *gpu_name; - u32 speedbin; int ret; =20 adreno_gpu->funcs =3D funcs; @@ -1214,10 +1213,6 @@ int adreno_gpu_init(struct drm_device *drm, struct p= latform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } =20 - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) - speedbin =3D 0xffff; - adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); - gpu_name =3D devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); if (!gpu_name) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 29097e6b4253..044ed4d49aa7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -63,6 +63,7 @@ enum adreno_family { #define ADRENO_QUIRK_PREEMPTION BIT(5) #define ADRENO_QUIRK_4GB_VA BIT(6) #define ADRENO_QUIRK_IFPC BIT(7) +#define ADRENO_QUIRK_SOFTFUSE BIT(8) =20 /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 3941e7510754..2309870f5031 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -5016,6 +5016,10 @@ by a particular renderpass/blit. + + + + =20 --=20 2.51.0