From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42B0D30596D for ; Thu, 26 Mar 2026 23:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568859; cv=none; b=mSsyjlL/mhwRrjUTjFEa/B3eJNdUNlwiJ6PeNVAekSk3/v+AInrtXtJzrWWrdmVBn+yTinz6bRGLec0bZr4ujZ5Q+3YH/QeScNsrTRLOaLLQZCDY6QC7aX0memB9N714mito7h5pE3s3QWhKLXJ5Mr8Y6Eh+C8uUJ/ybH+ifrn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568859; c=relaxed/simple; bh=whw5ih33RKzhzjxmn7G9KhAZAEVLCxqBpYjISYPPjr4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q2DTTHRysRzo93phy8yFy7Bs9Zethxhs4Fyl9q7MX2jngQSzoZW9LouHgqhbs6pRMsjbwbeayX7A6r02MIpW67tx+otjs9uVgbIvupGW8HzIjFcwXwWI/uqRonjP90P3Ej8foCJkiRJ7S2NV9pwNTD9oHCYuTBQ3/M3gmlWVyvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iGpMWln7; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iGpMWln7" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-c76864f4e58so40358a12.1 for ; Thu, 26 Mar 2026 16:47:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568857; x=1775173657; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jlXNZ6YErxvr6V0/1Nzao8eMwm0DA+edMLaU07KmQkY=; b=iGpMWln7/gOOyCIdyrY9IIUUPax5Ihg/SM+WiQH4tbDBnzgKkOgyijltbnfQzKuxoI Nf6iKem0iDX178mCpgy2Q/1zh21o03DWP7tDI5i/Q4UweSvJAF/G27pPtywGRN6E3i9m xNZn6OafPbZf0Oh7f4gS7Q9X2XaXFau+YKvd6SbP8XjbAZXMeIOFagOrlUNcY5X898No rvixebWR/ttU56QDQXdJ8Kd9Y6rwvSIl8aQHBXRyf/2hKYBCYj8eExoi8AM0N//JJ8Cl Q9INmzygXWkURZxVJ9UGE4hrTpOKlra4Q0LJ5tlJ0nO6xm2xybHLflqnLOYOYVyV/G+v HTOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568857; x=1775173657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=jlXNZ6YErxvr6V0/1Nzao8eMwm0DA+edMLaU07KmQkY=; b=Y/aW5rdlABm/3O3mGF/6i6UybcTpylasambmQqGVPBj8HhKnXtna5u1Vr1NifRjj3q Q4W0r2R4MGPIeMgSWaf8lRF3/2SRVP7qgAVb64QMzOTX14QvFYENEqfBERkBFaxFNusF BqhbV0YLn46FDh5eyDTLjx2WDLxNkQHZbGGnjpQB24pzROvicj2h842RPSp/GOw56bq3 iRQjHB2w0Z8qtwW+rKDe5nOvoNuL46lUAbEr8sv/WMfY/4ftAbPq4vQtrkyRrS+Ca+9Y AuAL8lb477dRHb+WQVbr71+2n13TdAIHIOIBVNP8/UfhUgRLgl1TETBtbXo0SFUZXLo2 rKpQ== X-Forwarded-Encrypted: i=1; AJvYcCV+MP2oQ5X8aRs7nGjO3LXx+5snrDLvE4Hy5cHSjMlEc90UOm07ruGPyogwZQc84dmJ0xu3jZOpnLUZNUI=@vger.kernel.org X-Gm-Message-State: AOJu0Yza4i7I53al5Z95AUHvzjwm5OurHrZuiv97m/GXzVBAgpKOfvLU CHmp2clfQZecX8SwuQ5NIoVQ+0BZTt8XQ+xfT/9XSqcsP8/rfldNoHdv X-Gm-Gg: ATEYQzzWn1nBFItwU4CyiV4W7E148ym3fr3WTJXEdODLtvHr2IIag/1/+pzrt3qDB51 kBAX0R6TGDpJZaoZMXk/JPiaDJqMlo34ubUzQQLJ0oeih5U5o8CTZ9sRAwT7RKKQPoSiLaGfMJa Idq5shrjaU4IHZzEPDuInyKg6aR3EVWkafcBsnVRLLgZIaozmFmMsZZRwGE2ixWtojGDHVIGS+N Aryb650jCw03t8dMlOvs0UaJCAn1EeF7Cpk6XGoBDvos+KvdiyVK1QS2kUg5JhROBiYER6dvjnZ i+b0kvqeHGcS3izMHQJBSYi1/T/T9pPsd+p8C1AEErMXzIkKx5K50bneUB7d1CAYcyMwd42QcNL Eg35KbgO/2RxghwCF57Kf+SCcdiAezfFdaB01qr7OSLby7AiavHz2JOFoFSl84/XTOYb/pgspaU EXpHZIN//fLBQA5wWXg+2mGvS2uSc6BVprixyovRE7P7Xx6ZqsSQFhY5U= X-Received: by 2002:a05:6a20:3d83:b0:398:4bf2:4285 with SMTP id adf61e73a8af0-39c877fe4bamr553257637.16.1774568857439; Thu, 26 Mar 2026 16:47:37 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:36 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 1/9] drm/amd/amdgpu: decouple ASPM with pcie dpm Date: Thu, 26 Mar 2026 16:47:08 -0700 Message-ID: <20260326234716.16723-2-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kenneth Feng [ Upstream commit df0e722fbdbedb6f2b682dc2fad9e0c221e3622d ] ASPM doesn't need to be disabled if pcie dpm is disabled. So ASPM can be independantly enabled. Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index d5e6d5ec69c8..dbee43c58741 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1782,8 +1782,6 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_devi= ce *adev) } if (adev->flags & AMD_IS_APU) return false; - if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) - return false; return pcie_aspm_enabled(adev->pdev); } =20 --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pg1-f174.google.com (mail-pg1-f174.google.com [209.85.215.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B5792609E3 for ; Thu, 26 Mar 2026 23:47:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568861; cv=none; b=W9ZQ8Hs6v5ulMcyRt8fPz4hA8dJ6hw7D0+l10bRJYtfTllmIMFRu99ASevtTOzoQYtSLL3nDdQgChVJ3Cy6nIgOVVbBq/kpPb8WxRJJKURrhMYOT6B7y+XtWw7Ir2ifa2X8Iy2B8AOnf/6k2gvUBpj6vGN1aZlPcC/fWnqdQH10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568861; c=relaxed/simple; bh=xoYVdTk23TPn6JIaf7yY0qqI000iCFBtQjQUAdfGGDk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l4q1trxTlSaWEVD11xCt6waBQbRw2QM28fBi1AZXxkJw9UGFgDmP6/fLwKRbh8TzplWaGctFUwsdZGL64vENrQMbJrH4EDJ+JNWKHfBucIYcL0MYAXFsEaK8aExe+HyFkejSPYtDyNN5V7HdJl6L9MqyaW6R/1EyQVKD3DGAb2I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KPdGROls; arc=none smtp.client-ip=209.85.215.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KPdGROls" Received: by mail-pg1-f174.google.com with SMTP id 41be03b00d2f7-c73c990a96dso798934a12.0 for ; Thu, 26 Mar 2026 16:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568859; x=1775173659; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mqMdpDaaRiGg+2ZN9NqktjEbPVOkWurGFYKafkS7Z0Q=; b=KPdGROlsexr77/+/oBXv2kXTVBjYRg7L0KUiLnQ4MkILHxgsqkIaRSuxnZdcG/rbpH gCXd+kqbqoQo19rvggGCbvcXFewdWvGc8pyd0Z/BVi8ctMc3JXDIwPHzo+s7XMX/Ykzf XrXpL8jQpLgb/lN/ZT44hT1LTSypruAI3KbRE2f49bWtwkGmA2yu3jRff8YEAVmM/b2O EAwvfSjNpho4uEtKsJfxFbZZWt8jBrSVDcdM1BjqlMRDVnocRrhbewHPHFPGJDkMj/Mt xH3BzISUxSHdIPkanK10mhjjxw7xiwn9Hfom5ci2mvpMwaTMLhJy3yS5L1wk9tKombBq RdRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568859; x=1775173659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=mqMdpDaaRiGg+2ZN9NqktjEbPVOkWurGFYKafkS7Z0Q=; b=S6fI2PgFNdvroBhM6VbXga/MaZY604PBuFoCJOjKokpelkg9518nbF7WWi01MJ69US LxWi/nOasDzERO1r8DhLCi0HngG56dVieC1tUKe0NSYOE+UC2VUFJ6vW2HQWgOmTULkz cJWMj0G/yAxh9GEzWOYfX5FDJdiYe8DBvo+flmMlbApsOiPVps/IUuNpq09zc+s9lHDk z7AIpkw/ZoXDObCIbko7M+KaxbyKt8PqoxKN/xeO6GPPJVa+PsKElf5XbR1RgguVQ8Dc 3ZFwom6UOd0GuOrWEEI/jTFuZhVrDMo3l1OGRMQfCMANTvPvFhFikuqvDx1wSeHbu+i4 M8Dg== X-Forwarded-Encrypted: i=1; AJvYcCUWnG19xH0cbgUU7CymsZXDEhJ+Zr/lxcBumnEKSHAL7bpaFTjDZQpSoPv6ecmdXVVR/LUmQQ3hKU100ks=@vger.kernel.org X-Gm-Message-State: AOJu0YzabvAZzTOI0PeDfLOmzkMZ4CeY35hRTgxYfLGVmi7bZSdg0gTP NdNgVPaBCB9JZU8C3xD7pu0DLL0CqaQkmURDf1BGUNC+Y6FTSBRUvzvK X-Gm-Gg: ATEYQzxZluxSfDzYgjAUQ4IDrwhxgsbupXWaFXtpg9Sl2P3Rvr3Cl+BEqYQW+GEXCWI 9G3r5KE9NUSty+DkwjE6RciTqz31thqYXpW2WDiTep8q+w2pMwTuTDUN0sfF24GOmaBhk1DMtVl +BoYH5biUavPg7WQPZTT4kA2Zlyb5jW2KC440D0HGqC6YrDrUrWxuaPtVWuap7pRDUP5ot53VPG aHGeh+BkSnElLopnDqwUBzNe3b1lJr5ogo+mO/B2LRlMXKxh5VaihkUmEmPEP6p1bSz0r3PQTyN 3fnMg7JnVI53oS7z9Pev5uQiEfvwhLm1zEla2dnZt6gcL7jeF96wveUjsVpzvKY//sJ5TIutSwx 1fQkdUCalPn64JGn322Z0iUqfjneVA8q3Xm9eD+C0nSkusjhrCuVBcESezeoG2LA7CrmIQpivr1 0e2gcDl0mUI31yu4F6xSzML+Jcvw9aVlM1pbwgUD8293v0J+70ILyv8ZM= X-Received: by 2002:a05:6a21:3287:b0:398:9ae9:7112 with SMTP id adf61e73a8af0-39c8781ff90mr479262637.1.1774568859447; Thu, 26 Mar 2026 16:47:39 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:38 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 2/9] drm/amd/amdgpu: disable ASPM in some situations Date: Thu, 26 Mar 2026 16:47:09 -0700 Message-ID: <20260326234716.16723-3-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kenneth Feng [ Upstream commit c770ef19673fb1defcbde2ee2b91c3c89bfcf164 ] disable ASPM with some ASICs on some specific platforms. required from PCIe controller owner. Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index dbee43c58741..eb3c6bfe2e6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -84,6 +84,7 @@ =20 #if IS_ENABLED(CONFIG_X86) #include +#include #endif =20 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); @@ -1758,6 +1759,35 @@ static bool amdgpu_device_pcie_dynamic_switching_sup= ported(struct amdgpu_device return true; } =20 +static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev) +{ +#if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c =3D &cpu_data(0); + + if (!(amdgpu_ip_version(adev, GC_HWIP, 0) =3D=3D IP_VERSION(12, 0, 0) || + amdgpu_ip_version(adev, GC_HWIP, 0) =3D=3D IP_VERSION(12, 0, 1))) + return false; + + if (c->x86 =3D=3D 6 && + adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) { + switch (c->x86_model) { + case VFM_MODEL(INTEL_ALDERLAKE): + case VFM_MODEL(INTEL_ALDERLAKE_L): + case VFM_MODEL(INTEL_RAPTORLAKE): + case VFM_MODEL(INTEL_RAPTORLAKE_P): + case VFM_MODEL(INTEL_RAPTORLAKE_S): + return true; + default: + return false; + } + } else { + return false; + } +#else + return false; +#endif +} + /** * amdgpu_device_should_use_aspm - check if the device should program ASPM * @@ -1782,6 +1812,8 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_devi= ce *adev) } if (adev->flags & AMD_IS_APU) return false; + if (amdgpu_device_aspm_support_quirk(adev)) + return false; return pcie_aspm_enabled(adev->pdev); } =20 --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DB6C35BDD5 for ; Thu, 26 Mar 2026 23:47:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568863; cv=none; b=sOn196wKJ2z3MXDLlo0OJLlOI5ZhYI3UhIxUawkkfihUg5fPEyS9NEjrABW+PfYO/Yzl1kZQNPdYO4MM9xC/rgAhp1dQomxKYuhY98FQiWLhSa4Dj5NnJBnKIx3PKQGTtKLdtZmMs+lt0ErsV6j67g86OvBT1c4W+JLqfahiTiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568863; c=relaxed/simple; bh=RwoqpXy71D2hq/9YeKiguZNaZPXik4kFxfn+hYcauuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mXNYZPB4yg5sV26oJr3OP3/s5XFYxFtZmYkXZ2ejTz+DF6Mfo1R+GsD1kVS17fn5nz7sCRPE+xY5YZ3ckTHzIaZwEBZ8aM5UBApAZyMLlKAJOO59RkdBH0ZVMCyOUSJpHwb5e6axMG4em+d8HJ09fanZtencio+5B0BkxJqwKmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RlabgnAe; arc=none smtp.client-ip=209.85.216.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RlabgnAe" Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-3567e2b4159so1027212a91.0 for ; Thu, 26 Mar 2026 16:47:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568861; x=1775173661; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=izF33sGDSHxUIsJEwsnSvCBwPxbglhEjEwQBj49A0mg=; b=RlabgnAe32e98ogTMNQgIFQqmbK1mMjBGXUj630+Kvz5qioX+707S2V+oCf+tOcImo R/QoG7hnTcPzkwLrlzfHixGfn8qoYvEDQ3XCjh9ws7+hxwQHTI3/mjVTSmotzv6fdili vJuP7Fn3AgSUbS3qc1GeUb4e1CQU3xML+Ujshvzio9GLhvFzs8cqYNXeblVG5olBVIE/ E4bP2QymXRtKvpvjxWwGRcMzHvL77gZgSYC98mVE7BkRl5hlquVzLHZHNcw/LkqZBpXD ReuNSoVJwoH78rfQVhETE4eF1HEygSu0h29+bMi92hzoxnl5HQiUCfhSPpnGjSlYFMTq c71A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568861; x=1775173661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=izF33sGDSHxUIsJEwsnSvCBwPxbglhEjEwQBj49A0mg=; b=kGkr1fAuFGP8zrx3P/ytb4b3v0oamLfJduxZNJyGMl3QnDAeSuH6HHxourSEcsGcAO ietP5TQM5UtYddpPLQpb+aeMzUq78ZPWTIboUFJYBhvxkhjO5T/MUem97yOTx0isX51A yG9duNV8Ph0+GHQazkvzIsF9zcnOyqUM7bVkz+p84h36Xe5swr3HF5wbjSVhVP3pbfcL YAUf53gYjGLrIYYOGxG1aSKjT0NimnmXGZWaw478usd7ynJ6EwRXzhn41Az4eNjfNG09 M3bFBaFt1G2rna+olx5gt+zS5HSqGAGGDnmffWFh2ASA4Kt+zCMPgEGvcp5eqEPsg0Xo tmhg== X-Forwarded-Encrypted: i=1; AJvYcCWZ+l/eAwVX0I+zwU4x7tc52SCNuHjDiA3QPv3dM5jsDtXsJlqYzvro/SzmyOjiRaeucC9ddw2tlxhQhic=@vger.kernel.org X-Gm-Message-State: AOJu0YxlI5QUxL+K59ejCePuJxbrZiNQhAr2PUjpJ8kq3X1hGw7lMnmv J2dKECOyW0+YH2pLSomVOc20tOllaD/WWCTHl4t7fBwo9gJNa5ff2YQB X-Gm-Gg: ATEYQzyrZysyF2FNydnpRrU3DQfsOdx398bOpg8CK5ZSMKWSZzaTShXy2odl6MuEgIq DjwA1GdGm5bEY6TM4C/btoLPCYf+lD2KhBgNQavUX+p+d+zGyKhmyMZm/WYK8jvkYjtaKUIZwI+ WvXyitQ6DnfscortwVX4fgExCBZf9S9TNHvKMlJ/VCdlD3k6doWNN2oYPin9aNcGlH0Kj20Afe6 Sln/6WqtoI4OtSgqXT+BTGiM6aAc5uWyTGfXE094vKVMBu1cS1AoZY7XChy2Ci01bb334u1k7vO vsbYWEI3TL/r+frMEDF3r3MISk/nOgOWnwEc4xgqUFQmsBluM9qaWHPATwnh+BvuLn13XiGVcO4 PGrUOsPTzYvIcfqQ7CiIZSTrZ8+LwNyh6BtgbOHhUy0ngP8ZJFWbQGAFkAyHQFwNbJXIl2d4JHC BDO3DsHVZq3OcIeoDHvtzE3D5KLR8Ok1YcSUs0CrreyrzYSRejrZHy7Pc= X-Received: by 2002:a17:902:e5cd:b0:2ae:c907:85e6 with SMTP id d9443c01a7336-2b0cddb3827mr4478145ad.50.1774568861439; Thu, 26 Mar 2026 16:47:41 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:40 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 3/9] drm/amd/display: Disable fastboot on DCE 6 too Date: Thu, 26 Mar 2026 16:47:10 -0700 Message-ID: <20260326234716.16723-4-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 7495962cbceb967e095233a5673ea71f3bcdee7e ] It already didn't work on DCE 8, so there is no reason to assume it would on DCE 6. Signed-off-by: Timur Krist=C3=B3f Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/dr= ivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index df69e0cebf78..7dc99c85b8ea 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1910,10 +1910,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, s= truct dc_state *context) =20 get_edp_streams(context, edp_streams, &edp_stream_num); =20 - // Check fastboot support, disable on DCE8 because of blank screens - if (edp_num && edp_stream_num && dc->ctx->dce_version !=3D DCE_VERSION_8_= 0 && - dc->ctx->dce_version !=3D DCE_VERSION_8_1 && - dc->ctx->dce_version !=3D DCE_VERSION_8_3) { + /* Check fastboot support, disable on DCE 6-8 because of blank screens */ + if (edp_num && edp_stream_num && dc->ctx->dce_version < DCE_VERSION_10_0)= { for (i =3D 0; i < edp_num; i++) { edp_link =3D edp_links[i]; if (edp_link !=3D edp_streams[0]->link) --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B951F2609E3 for ; Thu, 26 Mar 2026 23:47:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568866; cv=none; b=Kp+EWRH91NosF4+NWDjtG2kYzgVKAYVR/PgdZuueyDLsDLaUNC9JoRMwNWZObDr7FkIPodKqjo4B+pDedpdS0ZT0WaF4losnEHRj2IjnoLBFNLC4Z3hU1z2PfG621Nl4fNOtDAt8szbrkh8ivzGdqwc0oWOxjFst+KoCn+NJk/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568866; c=relaxed/simple; bh=KDqNex0SrS190A1ilN+y9+8TCpjpm9vndDHmyB+HvwU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q/PIWvfnlFITbUILFnvwzy4IE41ALiUi85fYZZhFOE2XZMEkfYmZJRLkvgwVMsFqcEsSUQhmPNHd4hMYSmsXzEctZpjUvsT5ZLitEGmjm/RlauE6uCe0xcREypE4Jf/qDVVBn8TwY85NoiUTZCZXBEBWKhFllMOoL8DwG3RyaoM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=as749G26; arc=none smtp.client-ip=209.85.215.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="as749G26" Received: by mail-pg1-f178.google.com with SMTP id 41be03b00d2f7-c7393536e53so635573a12.2 for ; Thu, 26 Mar 2026 16:47:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568864; x=1775173664; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fYskpQzDXhxM4+9VM9RgZDo2+o/dM3+zNnNFKoGgds4=; b=as749G26jr6HMyxyZYIkxxkbc6K0IglSLPdrLyqOkChZaFLZuqjaYv/kjb7/ZjvxPM scd3TuWQ4bMlOtkw/rkkidMHwVZ2sIcHimLnSme0GvsgDtrMISH9TL0HdKvewxOltoXw 4z7dHCujrkiUCxnMX1Kk6tJqPcavewsuOLPV5Otlm5dtzczmNZaswBqzj+rYC/QYfsCC 1/kB9WqX07goIOysjg9FOEoTbg0fwe30sXNicqzA7Ogirm42pLM5yYFa0l5+sd2pA2GR muQaIlsI/GW2OoHepdFX8R9LqOg8/6jZgXydJWX6zgR8ByZEOPBqB7IepXz6fFPyFLgW D1OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568864; x=1775173664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fYskpQzDXhxM4+9VM9RgZDo2+o/dM3+zNnNFKoGgds4=; b=EPVbuIWdagNZ7ZoErsIdhWWtMGWHyyjkvVxLjAGcSbG4TAkgW7j/5Cd0oYTdJ0jJLj XWytWcNbbOwkKP5Bb7femOEp8fD3cSKymd44xZPbvVUgmHkdD3Zq1ZaSVmu/wXT2QK1q S12NKOd3wM+9mb3x57U2cJ+5AzJ6fh3BhRX0YrPwMLHXPFkhYjmpk+CAEZ4DLhcJxW3N /BHJi7FS7ry9bWLAO6v6OmUATeuAphl046kYPIWcDLrZ8kRCJjHOOCjFW57PJOGexAcm CK+f/01gL2skUx1Cmo2Mt5NQK5rU1V+KmhHOzYeeAlU+F20OgwplzQ7gJCJCcJZF3xr9 8kEg== X-Forwarded-Encrypted: i=1; AJvYcCXX5r3rbo2P43qIVN1Sq5Oeya1AVBHZxXhb50CnNN4lPb0Zkh4fklA3/S1pxhapQFvHA56vbhBLoWlGSTA=@vger.kernel.org X-Gm-Message-State: AOJu0YyugAoHQ0wskaD8oe2fmUuzVajMP24g3EWr8fYDzXjCOVoKPHZ3 5Tg3sPnSKxgJ/kRFWfK8DJ5MDhPLJR6bYFyNNeKKK9cTAA11JG0N20lp X-Gm-Gg: ATEYQzwyivXyKt8DkP9n9NjlTfB0Ulja7rvu6qB9yfmx5MFzGysDPR4vglY/ISlsAm0 z3r2VhRg4CKeAgmVagI51eR4U9SpWb1Gl/dOqv6RYCtEEzE3EZtGZYSdPqSNVKVAJdnj2Xkv5j+ UxLBQBsa7jGlAylQh191l80pXuW6d/K1Rg5AgJTAnXpH31akz0gC0tetrtQXixYkrgl8muccznH WXOR+n5SpUZrzZjbOyel3hUaFkzCzOtX/30VQvpFXTlv2PK5R8rUxjqYpyuQZmp6X9hQstwQuj6 omtzVKpVCVOv9AruQ0oiEsRyeIgn+HKoN0q/Sd4kWi2dVqsHq2SQ9Nc2hiu8dNE6iGR+ZsL5TCO j/cnImldt+CK671cBR5geT3cDAO9kX2xCJJb3Q7nSiGuKtQQti5NHBWN2KiiVAnoYhGFL6h/9h4 vM4xGIOG8q7k8oWjSTAqxZPYM2Z9BCPyHsGp+GyyyVnu3ZE1Djw82dnfk= X-Received: by 2002:a05:6a20:3d1d:b0:39b:d9f1:6d05 with SMTP id adf61e73a8af0-39c87b30111mr483902637.53.1774568864031; Thu, 26 Mar 2026 16:47:44 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:42 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 4/9] drm/amd/display: Reject modes with too high pixel clock on DCE6-10 Date: Thu, 26 Mar 2026 16:47:11 -0700 Message-ID: <20260326234716.16723-5-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 118800b0797a046adaa2a8e9dee9b971b78802a7 ] Reject modes with a pixel clock higher than the maximum display clock. Use 400 MHz as a fallback value when the maximum display clock is not known. Pixel clocks that are higher than the display clock just won't work and are not supported. With the addition of the YUV422 fallback, DC can now accidentally select a mode requiring higher pixel clock than actually supported when the DP version supports the required bandwidth but the clock is otherwise too high for the display engine. DCE 6-10 don't support these modes but they don't have a bandwidth calculation to reject them properly. Fixes: db291ed1732e ("drm/amd/display: Add fallback path for YCBCR422") Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 3 +++ .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 10 +++++++++- .../amd/display/dc/resource/dce100/dce100_resource.c | 10 +++++++++- .../drm/amd/display/dc/resource/dce80/dce80_resource.c | 10 +++++++++- 5 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index b268c367c27c..a2e100aa3cba 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -460,6 +460,9 @@ void dce_clk_mgr_construct( clk_mgr->max_clks_state =3D DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr->cur_min_clks_state =3D DM_PP_CLOCKS_STATE_INVALID; =20 + base->clks.max_supported_dispclk_khz =3D + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_k= hz; + dce_clock_read_integrated_info(clk_mgr); dce_clock_read_ss_info(clk_mgr); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b= /drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index a39641a0ff09..69dd80d9f738 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -147,6 +147,8 @@ void dce60_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) { + struct clk_mgr *base =3D &clk_mgr->base; + dce_clk_mgr_construct(ctx, clk_mgr); =20 memcpy(clk_mgr->max_clks_by_state, @@ -157,5 +159,8 @@ void dce60_clk_mgr_construct( clk_mgr->clk_mgr_shift =3D &disp_clk_shift; clk_mgr->clk_mgr_mask =3D &disp_clk_mask; clk_mgr->base.funcs =3D &dce60_funcs; + + base->clks.max_supported_dispclk_khz =3D + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_k= hz; } =20 diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 8db9f7514466..7886a2a55caf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -34,6 +34,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce60/irq_service_dce60.h" #include "dce110/dce110_timing_generator.h" @@ -870,10 +871,17 @@ static bool dce60_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource= .c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 53a5f4cb648c..6717ed84a032 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -29,6 +29,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" @@ -843,10 +844,17 @@ static bool dce100_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c= b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index a73d3c6ef425..af4a45718c7c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -32,6 +32,7 @@ #include "stream_encoder.h" =20 #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce80/irq_service_dce80.h" #include "dce110/dce110_timing_generator.h" @@ -876,10 +877,17 @@ static bool dce80_validate_bandwidth( { int i; bool at_least_one_pipe =3D false; + struct dc_stream_state *stream =3D NULL; + const uint32_t max_pix_clk_khz =3D max(dc->clk_mgr->clks.max_supported_di= spclk_khz, 400000); =20 for (i =3D 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream =3D context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe =3D true; + + if (stream->timing.pix_clk_100hz >=3D max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } =20 if (at_least_one_pipe) { --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99BDE33555B for ; Thu, 26 Mar 2026 23:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568870; cv=none; b=V2pUDvPMStWHbpWy2jx99fyuOuP4ytj731Zz6P0pRqs/1Y53fj25yNnFrPmbgJ38zJYJTA7gFZKzXCKplU8jEf3JPgchWh00XIcL2vuCnlSZnYu2ZQS2luZbRUbKyTr/G1estNCuHOfYCfmCwiylc/YJErxmu0eSDXKp5FpOxAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568870; c=relaxed/simple; bh=7iOT+Z7eb7KqS/bY5XBbf4Vi9sbim1UF/Q/8f3P5oDI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lmsf8Uj38S2S29uiygwYAFlUaGFvBYWHYiOAuGFsj26YsOxMygCj8+QFXuXQ4nmoRy2HtNwFW4KeWDMrbjz42V4so+PlmfUX6SRG1Ntu8jgxeq1PEDfKQgC9c0TcZ/RV3ST2i8Cz0NKZXQjb0dbBoNfWdbku7ymza6N+EuXm5U4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=e4idUwH4; arc=none smtp.client-ip=209.85.215.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e4idUwH4" Received: by mail-pg1-f172.google.com with SMTP id 41be03b00d2f7-c757a9251faso702907a12.1 for ; Thu, 26 Mar 2026 16:47:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568866; x=1775173666; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R5FyONZ8Ftg8PcUrjhCTmSRITsVvMq+p91xq+TbWIsM=; b=e4idUwH4Ixn6EZQZ/LPajFCZ4CFzqKsGYeSSuqbaB1XAEo6A0u64AWisZCIu4IkF8Q e3fQk2AQLmmKWnLOigDQPOoZfVqlZzhqx9tyIfo2o+wkTIXXl7GgBvg8vMcgpp+J9I6Z yPF6sh5uyOi1UVjN15IuZ2Thers6G8C1xVS2zOCHm/qWBbsen/MX05yxNsoeN6lS8HYM PbQBzSzTkf0VurW9idSMHNkeZiJBtGt/EfI/qYd2XOMY/ve13HmLim9LYQoEYZjwxBKq 9JHjOsW5DCCtFTEWbgsYVRxx5UO8Pt0ghKv3j6aEiCGcVo3bLhK8vyX6vmK8MWRn/XO9 6uaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568866; x=1775173666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=R5FyONZ8Ftg8PcUrjhCTmSRITsVvMq+p91xq+TbWIsM=; b=VzF51hSb9clZNS1gZJTXAX/aY0wLGlJb4KTY3MZkqI1JONPm7j4eMu0SSSkqNoPL9r Cm6c2/sxQBWDvrjG4hUSTVjpTxi5G+8xp/+IuzHlDn82Mg46oDjfi6yZpMCcaNIUzsts P3atBgAKWb4jsILa3zMNmJgD9OuWRe7Z/6dkwz925mWzrmNblb2I74+lBdSu8DuNc4ft bjgMgegn4y3PI/WUXV+UHy6twRMQgkRoC902SuzqHONfheBDbwnr+1O+VeINY2frEaW0 o+yZ1yCLDABd/gRUaow8th/cATk8xFV53Sm/TOBPUj8oHS8sEOgVln8T5StHqNWzcRQZ nqig== X-Forwarded-Encrypted: i=1; AJvYcCWPTJAMNlKGRMY7JIezV8aOZRt7JQZy9CdeiUAB1IFwpfJi/lg9a98po6qokgrdaXbPLGtBUB7vEbT0Pv4=@vger.kernel.org X-Gm-Message-State: AOJu0YzZLsAt+VCJ5YxU7s+/Eq4hC0jxSYGfSE2wnqEIlvkHQCBofULQ JtImo11hiptJZoPbBxcSHq1ZdIjdvRp2rnvaYeDGoIoM1McTdI6w7dFr X-Gm-Gg: ATEYQzyUb6jzollukCiZ6J/T2Kzj2Z9CfUlG+NCx4zQJ21zEnJaCMM3t3XeJ9zcPrcB ayJnAOdiQs+67dIISILL6tlojJfM0CfPPOAOa7hHQPZ1NHoz569V7OPkQSg9f3OvqIP1r19e+P2 UpG264N4i2x4T6+rKRQ3juE5BS11fPtdSXzUKyAZ6SLHkmgLgFweByOKAee6joNRCPIHfrLKwdc dYBQK4ztMDrn84rO8NYAnGmoTb29WW/FgSOmnJRr3PPj2r8ohS5t3R5XMKKe1oPuaODneBXqY47 kqLkmUTeQKn9qRMFbG/EuwFJaQoSb6v6WnJE9PC7H6Tdj+P7WVTyotf7YBpyky/gHDiK9a49ug5 2CWNt279WTwrY7dezvglrKxgzgO8Uw13Wl1j8rgU5k6w/x/lRWWMWAnBnNWpa3mNeRT2mQbHmLE mj4ZS5+bo7/kcnepa2cFMB3nwKZgtL7RZVdLjURbIJGMRfZ/f+P+2JbVU= X-Received: by 2002:a05:6a21:6d97:b0:398:b16f:703e with SMTP id adf61e73a8af0-39c87abf84fmr507549637.40.1774568866039; Thu, 26 Mar 2026 16:47:46 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:45 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 5/9] drm/amd/display: Keep PLL0 running on DCE 6.0 and 6.4 Date: Thu, 26 Mar 2026 16:47:12 -0700 Message-ID: <20260326234716.16723-6-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 0449726b58ea64ec96b95f95944f0a3650204059 ] DC can turn off the display clock when no displays are connected or when all displays are off, for reference see: - dce*_validate_bandwidth DC also assumes that the DP clock is always on and never powers it down, for reference see: - dce110_clock_source_power_down In case of DCE 6.0 and 6.4, PLL0 is the clock source for both the engine clock and DP clock, for reference see: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Therefore, PLL0 should be always kept running on DCE 6.0 and 6.4. This commit achieves that by ensuring that by setting the display clock to the corresponding value in low power state instead of zero. This fixes a page flip timeout on SI with DC which happens when all connected displays are blanked. Signed-off-by: Timur Krist=C3=B3f Reviewed-by: Alex Deucher Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 7886a2a55caf..c4d7fa60d654 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -889,7 +889,16 @@ static bool dce60_validate_bandwidth( context->bw_ctx.bw.dce.dispclk_khz =3D 681000; context->bw_ctx.bw.dce.yclk_khz =3D 250000 * MEMORY_TYPE_MULTIPLIER_CZ; } else { - context->bw_ctx.bw.dce.dispclk_khz =3D 0; + /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and + * the DP clock, and shouldn't be turned off. Just select the display + * clock value from its low power mode. + */ + if (dc->ctx->dce_version =3D=3D DCE_VERSION_6_0 || + dc->ctx->dce_version =3D=3D DCE_VERSION_6_4) + context->bw_ctx.bw.dce.dispclk_khz =3D 352000; + else + context->bw_ctx.bw.dce.dispclk_khz =3D 0; + context->bw_ctx.bw.dce.yclk_khz =3D 0; } =20 --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A830B1946BC for ; Thu, 26 Mar 2026 23:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568870; cv=none; b=tn1FP1OaYRCGBO0x9mkgfFddi6OV9tHNXErf1KKf2Ohy7KrwZpY/bglpdSGwul8FBdqDxfDqfrugvOiw1pVvlrHj0HaySwq58Z9CrgwweiZ5ukENOIwr1ZNtwXLCT/LIUMV9SEKDLBtcfGXowxWyZlNrRHaQ02aHVag+bXh0YsA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568870; c=relaxed/simple; bh=nxNHchBEAgurZmPLW41iEo80XDuWVJCQL7AK7y+NaqE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L2+lgRVH21IaavUHfkVlFZl8VIuoi6CnX8WuLIKKpmfdKB2mXZWHubzw4R+LbV1HKFahK7TGzA+44g1Kz3xNGxgEZGY3FNH25LWChA99S2wWA4ytTZCjHs+OiG6BDPWR8DOCOsr9h1dl2MG31HlXloIVWiR64QrpOe3o6bO1t94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kIwnNE0K; arc=none smtp.client-ip=209.85.215.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kIwnNE0K" Received: by mail-pg1-f170.google.com with SMTP id 41be03b00d2f7-c7393536e53so635585a12.2 for ; Thu, 26 Mar 2026 16:47:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568868; x=1775173668; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8f7Ntg2BX3ujyAv43r3p8dJoIwxn/3R/KWzzyEF1YhY=; b=kIwnNE0KewhoCVNqV0qTfFIWmST5NNAjTjEn6yAQJvKKUfYopcgZsjfkHdBYrJrIog ZYo/SdeWvegeBl5A/rDOvEzNe77W63mq0rKopnJGnEr3VO4tjIP51FVHpID2Z98FZ1YO ckRZXSxYanL4pX9coCXqeTrAPRCHV0npcqZccHb7ivl18uKknV6zxRuHT9ThKN4WNrWR fH+kZFhpNS82PFcVgfXr07bpALGZDY9KkRL5Ka8GlrVSHENigXkM0CJ5SfvbSuk36nCL MAp4qhjHEHD5Z6jhaF9EXWS0n6jTpfvM/cpkzFMiAVWnNHGlluy9o6J4vE10ZEB1s/il izjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568868; x=1775173668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8f7Ntg2BX3ujyAv43r3p8dJoIwxn/3R/KWzzyEF1YhY=; b=ZWLJx5/sXEAqsU1AW7A2irilvDQdIRltmemABeacD/zatFUNtkNL8OGr6uG6RSG8oW sbPFgd6Nt595svTYgWeqA1+yOYjFImadb0VSAJOhpXCcjEEwhd2m3NFRCqhyLWTlbEjB TeH8rezB0akJQ9L4KmztSAgbr7WfpM42J4tAA3kLwTyqxOj8T4ahiXlpdscJqXtzccLr 6KCo/hdiyFIxHH2k+TUbtbzbFzS0bmG4DJPC7ZomnqETVTwpCz+7whi0xAETGbcLAWK9 LtGH6hIKVVvXLBdFgWj6rSscxD8EKojIKTPmQMXRcLX3QMM8jLIDyRaKN8O6ou9OXwH3 aa2Q== X-Forwarded-Encrypted: i=1; AJvYcCU9grMxXVFbNCVbPpONR0hGZ2ocstt1CS0je8XqRIj/qOSAZoH9zIPgO81mG+SA3lrvC9jmkhXaUrYJRhY=@vger.kernel.org X-Gm-Message-State: AOJu0YydxGATTbx05FoAxEQWgGllzhaSDKSVHzPPADsRJwAB8eDDNlRt L1x6xsEMhYi/m7KCx9e082dCdjIXUmwTgQZ+JoqHEfnkqt5hCIDX2SWV X-Gm-Gg: ATEYQzx1P+7GFhFga1ibSw9W3OMNZqEqdFpWBxFRYP+B7+JzZeALsGqLYHRuoh8SxYY L0+7ivxNncG2zsAZYdq9SQH8cu8o+q2JE37ciR1EFhjkkPHkDsUN4nN2/QqHbABpqmm6XXoSe6M koMlhNrwWIfwK/B7A8EejHxsmvkHRoL2hiGQiXP2+mjuFLp4D+rNlUGiycs9wt/1i6JWAZB8dHy b2RFTRKxLTQFRqOHXvzBMjwAsIZ9AUuv/q+DcWcwRGqDQ98LkTRW9JOWmI7D0MfPCWOPpGaApm7 NOzH1Ck4IZ/o8Unq4Kb24fg6RMcWAg8jebUIsfFR2TaLlXM9w7wc2eL41Wu6RWyG7OLrLLGfdzy Hq4IMn8AxCjmW0H5KVQZBmENrxO2Y19PZ/JN1hR7pl535rdE8+d4UUpDq4c4aI321nAhjdQDpon vK1AvcviCNTXSpOSu1Q3jRzRWBQM0Z4GJvRhvKHtSyqkdwsxt8HT96wck= X-Received: by 2002:a05:6a21:32a4:b0:398:79a8:5bf4 with SMTP id adf61e73a8af0-39c87a364bemr573477637.37.1774568868091; Thu, 26 Mar 2026 16:47:48 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:47 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 6/9] drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming. Date: Thu, 26 Mar 2026 16:47:13 -0700 Message-ID: <20260326234716.16723-7-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 35222b5934ec8d762473592ece98659baf6bc48e ] Apparently, both DCE 6.0 and 6.4 have 3 PLLs, but PLL0 can only be used for DP. Make sure to initialize the correct amount of PLLs in DC for these DCE versions and use PLL0 only for DP. Also, on DCE 6.0 and 6.4, the PLL0 needs to be powered on at initialization as opposed to DCE 6.1 and 7.x which use a different clock source for DFS. The following functions were used as reference from the old radeon driver implementation of DCE 6.x: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 5 +++ .../drm/amd/display/dc/dce60/dce60_resource.c | 34 +++++++++++-------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index a2e100aa3cba..5dbe89d9b72d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -245,6 +245,11 @@ int dce_set_clock( pxl_clk_params.target_pixel_clock_100hz =3D requested_clk_khz * 10; pxl_clk_params.pll_id =3D CLOCK_SOURCE_ID_DFS; =20 + /* DCE 6.0, DCE 6.4: engine clock is the same as PLL0 */ + if (clk_mgr_base->ctx->dce_version =3D=3D DCE_VERSION_6_0 || + clk_mgr_base->ctx->dce_version =3D=3D DCE_VERSION_6_4) + pxl_clk_params.pll_id =3D CLOCK_SOURCE_ID_PLL0; + if (clk_mgr_dce->dfs_bypass_active) pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS =3D true; =20 diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index c4d7fa60d654..978c024c97ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -374,7 +374,7 @@ static const struct resource_caps res_cap =3D { .num_timing_generator =3D 6, .num_audio =3D 6, .num_stream_encoder =3D 6, - .num_pll =3D 2, + .num_pll =3D 3, .num_ddc =3D 6, }; =20 @@ -390,7 +390,7 @@ static const struct resource_caps res_cap_64 =3D { .num_timing_generator =3D 2, .num_audio =3D 2, .num_stream_encoder =3D 2, - .num_pll =3D 2, + .num_pll =3D 3, .num_ddc =3D 2, }; =20 @@ -990,21 +990,24 @@ static bool dce60_construct( =20 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_= dp !=3D 0) { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, tru= e); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true= ); =20 + /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it h= ere. */ pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs= [0], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); pool->base.clock_sources[1] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [1], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); pool->base.clk_src_count =3D 2; =20 } else { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs= [0], true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[= 0], true); =20 pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [1], false); - pool->base.clk_src_count =3D 1; + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); + pool->base.clock_sources[1] =3D + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); + pool->base.clk_src_count =3D 2; } =20 if (pool->base.dp_clock_source =3D=3D NULL) { @@ -1382,21 +1385,24 @@ static bool dce64_construct( =20 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_= dp !=3D 0) { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, tru= e); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true= ); =20 + /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it h= ere. */ pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [0], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); pool->base.clock_sources[1] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs= [1], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); pool->base.clk_src_count =3D 2; =20 } else { pool->base.dp_clock_source =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs= [0], true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[= 0], true); =20 pool->base.clock_sources[0] =3D - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs= [1], false); - pool->base.clk_src_count =3D 1; + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[= 1], false); + pool->base.clock_sources[1] =3D + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[= 2], false); + pool->base.clk_src_count =3D 2; } =20 if (pool->base.dp_clock_source =3D=3D NULL) { --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA9642EC0AE for ; Thu, 26 Mar 2026 23:47:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568872; cv=none; b=rLHUallOaLT23BUYCvKuiy7DD/DOlh2cf19ntb+Y7lJr1cZVYvnhEgmAYpy6jDkTHxhFzhCIUQbSuZQV0CrU4tA6MiEeAJ+sCs7PL1nSgi0oWizWvMfEDDdPZh/rKIais6QxqNOZD0TTwdS+jnOR9FBMpGFFlXsATFrM9KHUKd4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568872; c=relaxed/simple; bh=HjDa2ZaVfCGyD0njzM/Hx1F3qeaUeXvsmO8wpznl5Dc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AXpWkSP6zh5HCCSqAkT/tpiPKapd+A/zosdw9uRSRifpfc/r6qCPlwObpXaqH3l6IMx0Im+1K0xSExiBR2aonYliws65Zg0AP72jg4b1V9Vgi7JGES844nVCL3yb9qliYqn0va3WfKP29V3hS3OEA83kYH8EomQGQsvAKpC70PQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aan38cOJ; arc=none smtp.client-ip=209.85.215.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aan38cOJ" Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-c742723c863so941639a12.0 for ; Thu, 26 Mar 2026 16:47:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568870; x=1775173670; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9pCNIYnvbijot8BuXxZwdBSIjs5gTuAaUWfD7Zd1qpw=; b=aan38cOJ4P6Jt48RwEGnMigjeQYWKaP4ukgUJeBVkmXLOoeylu9TKYgsjHcVai1v7f vOhMsJaxHpooQVFJLyKr7YcG+OT8U81rZuXtFJ3Gam6fUW1RwQTrc9KxFmKttgol3MjI HgJGsq8oJaVkVg9Iex8pyQktfnpdAyPRyh2vGnZ/V3dnlJrZwiAfZ6ferhfRvg83+lP1 Qu8jCjqJ0wCMXo5pYNJIxyW/MrQPwp6Wtou2kL4v/PrCyemntg5st0W3EfQrcUz60osK zOXA81bOqNLOd1YSqkh/bFPkFvOIb7Ic8Yn1tfKmGYGOZrig56BPBzIBjo6jsBdEOcWh +sGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568870; x=1775173670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=9pCNIYnvbijot8BuXxZwdBSIjs5gTuAaUWfD7Zd1qpw=; b=nCdNH0vkntlG+IE+SBf/B1BYcoSM2s95VHufR0/+3QAp+dksoz1AwCJz4622uIXL21 a57RYpD5MarxPDMC9lya1y5avfyQJulC2b9Yy4zz+0RnHFha9964RJgf1zErNvs/sehi L5aI+ySA4svkwOL1fdyvmHvO0pBCdnvnrLGKkBawoWWeQu5skAcsoUpVb+UjUy3Jq4Qb Ej0sRhxAhDb4jJgoqEAJ8FU1XVg2bUKVLLaPvifL2omk5a3NY2l4EXAem2tmN0o9RsDL M1ZIQywSj8o1SXb0BJSVHqGyLG0ZdFnsyApp61wWMJKUzbA8w7cLX1HKwyLkRPWwD+gR fY8Q== X-Forwarded-Encrypted: i=1; AJvYcCUEPhGLdcrS8G7r5Qaxu7PS5XGcF3Fvkfa8Nd+Z8D9ssW8RkDmsSQ5N2EjHis3rBMEtJ8B6KHcXBkF59M8=@vger.kernel.org X-Gm-Message-State: AOJu0YxfJzN3bborFNoKU/Oou0fp09yDinGhbQWlXb0fS2SiaSUOTC1p ZqHtwPftrp7M4X9UfXotVu4bGWN5gYW45wJgA6aypV2e1ExgKDdZdIoY X-Gm-Gg: ATEYQzxcwEwEOkChFFcLZhP4OA4jQ38v8rOPJLa/T2YjYSJO6rSz0JsWvRtiQVNFfNL p6DdTZPZVFtXI77qaFl6qMBHPqcGru+VPadZCR67P/S+P25/ZK0KGQas0Sqh7F26ilL8oU5vPlp rY44lgBdX2UBVFiE7005CMYwr2XHdVnoBxL/jjBhZNBnsg7Ql5MwhBM6mRl2fNAXyAxSBeoLDEr naGs9Nhn5KcKDgAbSnIZojK+OZ389RG/FJl/b+r4129gUSz9Y8XCx4g6nBsInXdiYDCiESFVCpH Q9CjO2uSQnLgG201UYLS8TOlYEr3KgErADV/3Rrv1CshoCRA2UWy9pkbs09v/2RV6H2GAAYj+Sh 0RMbkFEJCnrz16m44laARGDuzvM+Ip3fppqi5H1FyVSkDavqi37L93axLlIrb2GdZmdj8DqCeGz YUGjtCWbDMsV+tF6E/b0jdbSx/L4eySLErJ0lcCYRWp+ZQ11YnmaScEeWRsbduqaTx/w== X-Received: by 2002:a05:6300:210e:b0:398:919a:ddf5 with SMTP id adf61e73a8af0-39c878d5394mr525263637.24.1774568870090; Thu, 26 Mar 2026 16:47:50 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:49 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 7/9] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15% Date: Thu, 26 Mar 2026 16:47:14 -0700 Message-ID: <20260326234716.16723-8-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 1ae45b5d4f371af8ae51a3827d0ec9fe27eeb867 ] Adjust the nominal (and performance) clocks for DCE 8-10, and set them to 625 MHz, which is the value used by the legacy display code in amdgpu_atombios_get_clock_info. This was tested with Hawaii, Tonga and Fiji. These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz. The extra 15% clock was added as a workaround for a Polaris issue which uses DCE 11, and should not have been used on DCE 8-10 which are already hardcoded to the highest possible display clock. Unfortunately, the extra 15% was mistakenly copied and kept even on code paths which don't affect Polaris. This commit fixes that and also adds a check to make sure not to exceed the maximum DCE 8-10 display clock. Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") Signed-off-by: Timur Krist=C3=B3f Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/= drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 5dbe89d9b72d..6131ede2db7a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks= _by_state[] =3D { /* ClocksStateLow */ { .display_clk_khz =3D 352000, .pixel_clk_khz =3D 330000}, /* ClocksStateNominal */ -{ .display_clk_khz =3D 600000, .pixel_clk_khz =3D 400000 }, +{ .display_clk_khz =3D 625000, .pixel_clk_khz =3D 400000 }, /* ClocksStatePerformance */ -{ .display_clk_khz =3D 600000, .pixel_clk_khz =3D 400000 } }; +{ .display_clk_khz =3D 625000, .pixel_clk_khz =3D 400000 } }; =20 int dentist_get_divider_from_did(int did) { @@ -403,11 +403,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_= base, { struct clk_mgr_internal *clk_mgr_dce =3D TO_CLK_MGR_INTERNAL(clk_mgr_base= ); struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk =3D context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk =3D patched_disp_clk * 115 / 100; + const int max_disp_clk =3D + clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_c= lk_khz; + int patched_disp_clk =3D MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk= _khz); =20 level_change_req.power_level =3D dce_get_required_clocks_state(clk_mgr_ba= se, context); /* get max clock state from PPLIB */ --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C84F3303C83 for ; Thu, 26 Mar 2026 23:47:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568876; cv=none; b=G2tDTwE1OZ5k4GvwOjOe3vETm+G+wC3xOyvXnEHykgu3clmGHWrkpyKySOw/ZDvcmx3Rvd13SiEwZ6AqYq4YXQlhrK6uJXq1bCGNZavYysVJh+3IMggqG/us9Hg+8Q4HLq8J5mTGcrJcyqqzRT0XFHk/gjbsBfncP6pRQ+/uIlM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568876; c=relaxed/simple; bh=mQkiW4SfMzS137EmyrdOnE67zcpG0+2zfv8kd36ZGCU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PAlDuDYmbZHriiFHSXcyLHiTJQw0vwPJPTx0w4lrmGZkFih53rvk283+Wz9QLaZHdYKRO2pJT8TlG7mNREe2GroGQ8/+l2WkpijcrWLbvPj6LF2reZZS1iO4XfWp3K26PrcGak03VLkbkjw47tUcVnfoCNPj1wgJDDjSsJ+muBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SdQ1VVwB; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SdQ1VVwB" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-829a27414a3so1124549b3a.3 for ; Thu, 26 Mar 2026 16:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568872; x=1775173672; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0/3ZOVQYuvF8/v5An1EVVsLN1VlAxvgYs14Kv3HQDNc=; b=SdQ1VVwBAY8AZrB4tlI5vEp3JaEECyx+DQYQjWk5/omoRpNEJxl7P3iNyasnpRjgMn 0hhrOH5DEQBHH0BK7UYaJzAFF177pCZ4CK5TCokb/y+e5ptil2VnrnSid1CA88+SP4xE XnvmuzKeAXEf7siBReq0MCR+NcV1aDlBOmScgMw0Rk1a9AsQ06WplUXouZiYDP+2wptw JTi4/2I1SjluzROCRlhzYu+XXT/4ypY67TqAQEYT6a9aHZ3MI6iPaDSZ+0GdPjbEHC05 74YdiLnqvGfptsNc1SwBXgVo4hsrJb53NTgPLRO0jp/HfPO/lM4xMLz3kWtzDYq6ZQd5 4Viw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568872; x=1775173672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0/3ZOVQYuvF8/v5An1EVVsLN1VlAxvgYs14Kv3HQDNc=; b=guifi2sCkdWU1fNDMHHX40JohummCUe2TmuRi97vejykHXC9joaSF1wJDwUQ5ymJk0 pknU4Dx+ArYjk8TylSqxu6Z0G288kEs8rC9lPDBvP8TxEIQtwfox9FDCIsnpu1bo/82o Qk36xvXvuq+lgHxUb7E0gXFM04q8EXl7YVX0A+dbyi6Zy7UsEGHLY6u6OBOflJS7861e GcUYjFDGOSr/vp9E6/tI+igGy8FbUey5rNYNgacp2NaOrvTwKxf+eXc/S/OOdXgm7b7a JeIWYQMCRpsUlPm+dKSOtp58v9hHWeuHfPdyVsRnY0yilSteWGmCyGwj+YdQYwtnTVLr 4qiQ== X-Forwarded-Encrypted: i=1; AJvYcCVgdZrszI5MUZUXORKVXZn7CPrCiS4psFH/3OWldSf8iaERP0SfF4SpKe1R8jG3LP7FQRgHLaKdcRGUcZs=@vger.kernel.org X-Gm-Message-State: AOJu0YxnawaorIAH3HbvSmPkZROC9EULJfv2pOgbqzeNjYWtoZhNcFG4 s04bzlQtxXjJz6NHL1lv3S34C80NBoOkXKZozRSRfRSg7KB0644xm6ZK X-Gm-Gg: ATEYQzwB/BqBUZKN9mnN/WJgWXKbWIENeIVMJRz4dmB7Sl6yqDRTkC00hmD8uN1LnJL RkFwVzVN43hiMDgIq4TL/frgsCrPRmUPhEPJRSblbmY3GI8f/E+eo5KF4ipgXvs6vlA3H8NaZjx ECZvbfxJEB/4a/wLEXspuE2gVbgkv4ssvhYDcZyqUr7P6bItr3pTtPuxOlhZByBwehTJXQJKW87 iwV8+0VMXXi8vEsqZTwQWCRuIr9P9VwGfCuUF+fmEzII/Fc7XhDlCVeM6Gd9+m+m6cpsWPnyGQ9 6uEdoa0YSD8y6LEQwh99cdgSPUUijH+CwSsqHYnAG9TAxzkwKsIhXMubq9UYLgJgBk/qOcvYmWs SrdeRz14tC5IZf4g9kr5vP1Aa6bJv9uFZzcMcFNYqmdRwQi7gezrvCa0FMlkhoFueJhIZLlQ3Eh EHVeJQSzSfFkyJgcfUddXUn99MyDPu1hAbGOdHIOgqva9TbiKYUaolhig= X-Received: by 2002:a05:6a20:3ca3:b0:398:a060:a97b with SMTP id adf61e73a8af0-39c877b2c2fmr512115637.1.1774568872136; Thu, 26 Mar 2026 16:47:52 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:51 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 8/9] drm/amd/display: Disable scaling on DCE6 for now Date: Thu, 26 Mar 2026 16:47:15 -0700 Message-ID: <20260326234716.16723-9-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 0e190a0446ec517666dab4691b296a9b758e590f ] Scaling doesn't work on DCE6 at the moment, the current register programming produces incorrect output when using fractional scaling (between 100-200%) on resolutions higher than 1080p. Disable it until we figure out how to program it properly. Fixes: 7c15fd86aaec ("drm/amd/display: dc/dce: add initial DCE6 support (v1= 0)") Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/driver= s/gpu/drm/amd/display/dc/dce60/dce60_resource.c index 978c024c97ba..3f9ea4fdc7d8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c @@ -404,13 +404,13 @@ static const struct dc_plane_cap plane_cap =3D { }, =20 .max_upscale_factor =3D { - .argb8888 =3D 16000, + .argb8888 =3D 1, .nv12 =3D 1, .fp16 =3D 1 }, =20 .max_downscale_factor =3D { - .argb8888 =3D 250, + .argb8888 =3D 1, .nv12 =3D 1, .fp16 =3D 1 } --=20 2.53.0 From nobody Thu Apr 2 19:00:24 2026 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C81E92609E3 for ; Thu, 26 Mar 2026 23:47:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568879; cv=none; b=AWoKzLlBqdpZrDRPRPffdC5TXmRXzUvfU1L1NCJAxR/PX2Mwp8uTtYTwdqeLYmA78jcJ46I18plE/y4fFaWm+QUBqf3NRZoyGn2RAKPVv5EokT31m0PK/OLCKZSfE/9J917CGqQzwzDRxObzX43CykSLujcxugQzuxpHI7HDgYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774568879; c=relaxed/simple; bh=NZJRkaTJpI1Vf+sGzChIbc9lasjvdkae3wVAdxFTZiw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pfpk/r2YHxzFDPxSObWmH3xgYi0vXAj8WdJocmgt6lPaofuagErjW86lIoqCiamR3ZwaKZ2L4fJGpT7sgcPGPl+9nK1xiP4qm7pITlwsCjUHfosE5nR6DowfYIBht/MiJ8VRjAdXebkAdM1pRO2JOMPxhvtmNQQyk1jhRscz2ts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=itt+1pTF; arc=none smtp.client-ip=209.85.215.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="itt+1pTF" Received: by mail-pg1-f169.google.com with SMTP id 41be03b00d2f7-c74f0c3fc16so572107a12.2 for ; Thu, 26 Mar 2026 16:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774568874; x=1775173674; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xynl6l4IZX6SF8kreSc2FtsN0XosoMomLgf109DsfAw=; b=itt+1pTFQdtHRowKFkl5BNdkawW8X1XjU/x/zPN568xwPtFAUZLURtrbzyjSG8DYOU GkJYRDUdo0AaS8hASsbSjzBzPzaUx4cnovzAsDKW/NueZHDQO8WSy9OCrOQixKDdXBZv Hvi9dHYxIpQP0nztcrfeyE5F8iKaYBGQ0fxZhGD99IZcc4544qzPbi+K8jQmkUKPMElm wry2qi8x9cgZYH2sQh2u1psvl/XaDuFxldx0R5RsQhwoKDwYLzilf3gVACPDbWqLQ43n GjBc20WqOlmIKs7tjwkyGutF1v18iHsVHGJ5tyVcHrwZ+gLVJol5BmTXDLYsCrgfPFk1 DanA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774568874; x=1775173674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=xynl6l4IZX6SF8kreSc2FtsN0XosoMomLgf109DsfAw=; b=bg65IWyXw5Zx1mdkjX7j/vVjS6fzNcY1y69YQQaH3FAb1FyyVYRP9Zzf9HPDo6Haq5 Ng0WlM8gssWBgNmdJrAJKGWpceqVFPFgRsLc7xYUA/j3FYwI8+94dKF1TEvJvB+oXWyK XuciXsGZnFZlOsrFe28b5YKI6nWyFTR44Hd7ZaL4R5ZtamkhJqS4KqFLsitfbWvryLIY JOGvT/Pz5D2+0cCwrgiXfyKDcx2xB4jPK18VwA1VA9qOWLrfl6qDYDt2NZp+BFtcmni6 fFUGY6IAGK2bpDgSzhg0V/jnhIbblZacV+F4zGl0DJbaS+PC6Pa2n7tyYTmzSTrHp1Dt 7YtA== X-Forwarded-Encrypted: i=1; AJvYcCXFmN+mawsh8NswJzWVncYJrYSgbSXIW+1sAzxYVJYwEhYMPk8N2fiIwkfJniCeZG/nHIYQuFnkiM4W5dM=@vger.kernel.org X-Gm-Message-State: AOJu0YzNjHr7N1Qz3bawhYzjspy3itz1H6x5jwboYHaXk8LkU8PuCHkn vtKO8p90zromCgbAwF4FnKIA9z+Gr1O1RT+ZHnKlcth+kygFwrXlfHT7 X-Gm-Gg: ATEYQzxUcyVbTe61WSci/nUZceuTEWxseXdD/tUHbGiQx+/V6/ebDQgzrKxmDKlfONs 2js+kCPvDGOxMJnvrK/cfB1thm4A8GATjZsU0w9g2He700rOCn1qEk42amrxPAYdySDxWQTRpSR RbOU0QejyjflXjSWVtrMEVNZiajQ3zVefJNNoNv7D58gU8QXfjir0JG3vUlRrfT9u3O26UnCNaK kZublUpOIBLffqnAtOloFCFdcNW/pkpZTfS2x9qNADN007EW/0uQ+8mqo3JCb7Jrp18JR3e1gkq TNQ//MZY7QeJjWgDh2T4M00soZrZK4PzPYR8KYbx8oLE4PKjSiGIgHrklRFuDGAxw79ezd0HROL ykGl6a4lKR4Zv0iGxyJP3thDmmK11iTgdkyY2yd88ABF10ADwDY5flUdo7AQkClZofumL1KTWXI m2QM4Ifpo21TdqmiGSsjPgq0J48hYaDtjo9glRbe42E/wk5v0AAyOr8PA= X-Received: by 2002:a05:6a20:94cb:b0:398:9820:f6cc with SMTP id adf61e73a8af0-39c87bcf3e0mr492459637.55.1774568874123; Thu, 26 Mar 2026 16:47:54 -0700 (PDT) Received: from ryzen ([2601:644:8000:5b5d::8bd]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7673933816sm3201162a12.21.2026.03.26.16.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:47:53 -0700 (PDT) From: Rosen Penev To: stable@vger.kernel.org Cc: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , Harry Wentland , Leo Li , Greg Kroah-Hartman , Bin Lan , He Zhe , Vitaly Prosyak , Alex Hung , Rodrigo Siqueira , =?UTF-8?q?Timur=20Krist=C3=B3f?= , Mario Limonciello , Ray Wu , Wayne Lin , Roman Li , Eric Yang , Tony Cheng , Mauro Rossi , amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH for 6.12 9/9] drm/amd: Disable ASPM on SI Date: Thu, 26 Mar 2026 16:47:16 -0700 Message-ID: <20260326234716.16723-10-rosenp@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326234716.16723-1-rosenp@gmail.com> References: <20260326234716.16723-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Timur Krist=C3=B3f [ Upstream commit 7bdd91abf0cb3ea78160e2e78fb58b12f6a38d55 ] Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4. It's unclear if this is a platform-specific or GPU-specific issue. Disable ASPM on SI for the time being. Reviewed-by: Alex Deucher Signed-off-by: Timur Krist=C3=B3f Signed-off-by: Alex Deucher Signed-off-by: Rosen Penev --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index eb3c6bfe2e6c..12d7e45a4245 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1761,6 +1761,13 @@ static bool amdgpu_device_pcie_dynamic_switching_sup= ported(struct amdgpu_device =20 static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev) { + /* Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4. + * It's unclear if this is a platform-specific or GPU-specific issue. + * Disable ASPM on SI for the time being. + */ + if (adev->family =3D=3D AMDGPU_FAMILY_SI) + return true; + #if IS_ENABLED(CONFIG_X86) struct cpuinfo_x86 *c =3D &cpu_data(0); =20 --=20 2.53.0