From nobody Thu Apr 2 18:46:22 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A41DC2FF161 for ; Thu, 26 Mar 2026 23:23:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774567422; cv=none; b=DAEOegXhoL5cFUhERXCsNyGf1Kl6HRPGCkuA7zrwgE8K407hc1JGuW7dpWWWL1Yq5uy8THvJwDqMfGLX1Emg/Y9B0tMgy7dIFKhzgyezD9WOOi2gIILE2Sms6XPRnuuyOQ/8INZWyU74nWUesNlINFl/3wlXDLPNORqnRid/glU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774567422; c=relaxed/simple; bh=6GpbW7tFut9sY85txH59hj+2HOyOlHdNNvOt6PtCgaE=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=b3PA/9yEHFbWyo2Rb/MWnoaapnPp9yNHWiOS4wkB0ENGAvSKr9eXr6M2KFR109RAmYYIwWDKXmjJWEsjYaJEpT1qR5PpfIx9XAMlVcTb8+XYR8EDsrUbsq/YYbmbUQonCNfbyEO0SgVjF22nzH5QPlfE5LaVvaQDrVoBFqQUreo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=U59cUCie; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="U59cUCie" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-486ff3a0fc1so15141835e9.2 for ; Thu, 26 Mar 2026 16:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774567419; x=1775172219; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=4bYHQZKeiCiMBzOolGhgKFQToMa7hk6HZA/6z0UHTvk=; b=U59cUCieCq5JKTsB1zN7aMNHJ0ns3qMJjGIHmSAWjn8x31P0itSeysfnQjrO1gGXDI quEIidLwsFUvVqJdiUph993yIaR3cmp/etlraZM+//uowdbGC8Fyr6KZiLRhEyv1vU6N sCuiSjRvzNcSX0nniz4AnPWIDAbKk8zoQcnq1bPJ/gM9mOyoLOzTPxg0MoyiQpdoLOVl coo/CT1BGU0HWXd6Pp9GdsqaXa8bgnw/t2t+jwQj5X+eIl87RFwtClPNyV03AwswRp+m CO0DBsQqaHluY0u1P62qqUOaz8D0w/VImXPwKGO421cW6ldggN29qBvsQk0AmxnkjUdy HcIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774567419; x=1775172219; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4bYHQZKeiCiMBzOolGhgKFQToMa7hk6HZA/6z0UHTvk=; b=oSnMAuKnEgAwuu0Gd0wm7bcmYQDAhAs3GUwSX9294hMvKnMPfmbnn5iYEQXGZfYEb9 BcGnltp9IVoqoZiZfq9SDHpl3TUDgq1YmWHkIhd4HzV7vpfIYFNr7N7keODcXPog2pj1 AoeeDE80T9G5sr38Tb2MXE/pzIf83EwHt2pVlDaBA2Er+E6NtEjbVLrybDqFNF+We9AJ wteHf+R7lsp6KktU4a0FRUmmOpUFP13RnqNGgDb+Dw7Cw/ux+Emf6UQnTZlLYeeRLyJs eOWg2437xsYuBwnB3FPFRpg8g52paKu/mdguh3aMxPSju6lurOGVr7knXdXgtiVyLVPd vw/g== X-Forwarded-Encrypted: i=1; AJvYcCVcS52d6S+/jz0/3D2Ahix81pK3bsCp0KcA90B5PF9cJsm5iISGzXRnc8wcNF9ko3ytxvIeDK865xXCzTo=@vger.kernel.org X-Gm-Message-State: AOJu0Yw01uwUas+DCWXSRdjgwviBmlMQawF4MgvAU8MC5wNoERIuLHU6 8Lu6yNdKVIQ+wffwS7vEPaYfuby8otPKYkuFuCCbnFClEw2h+bwNRXQF X-Gm-Gg: ATEYQzwIFIYAcD91DMrdF969NFCCym0GoRxqo3MSp9o1u9Oe9VKt7JIMaxMzbOVIotG Dh8oNsdl/V2WJouU/71jDOfAAqFDpBv43IeYCr2o2Lb3tAfoIyX/BuRx39E0XFLRhhF9HdU29eL 6lqldP5w02Ip1CmDzvauWSZPRKGHKEvmnw0/pvS1HemL0AukSY4vrVaXjfRwbwp6gCwA89iupcQ IWrqaLTHGGbBVYtyM2NTXj8KAyyzue9BexADdSbTJz6H0GivP+tNrIrHFusiLl1xtpIhPSkklGt b8SqOFkOk6mZYpfvpb2mR6QScn13Nd1eYFA4n6ENYsCb/5bA0+f0eAp5xKL0PsG2t9vCwBPYUK/ 6uY8LChD0R0pNZD5SWdsQ+bu0HDceyTA3R/ZRI41i/p6sdE0HWyMmAGtx+HqcrCH4OBgyVnLOBx CnkEqJfR8bA26ixnQPn795BawEJ4dPeP46BhimV5E31KQspRXtOmOQv66loKaq X-Received: by 2002:a05:600c:4447:b0:487:219e:42d with SMTP id 5b1f17b1804b1-48727d6f90cmr7279675e9.11.1774567418763; Thu, 26 Mar 2026 16:23:38 -0700 (PDT) Received: from osama.. ([2a02:908:1b6:8980:8cd6:6329:c43d:2fcb]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48725d9acb9sm5956885e9.1.2026.03.26.16.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 16:23:38 -0700 (PDT) From: Osama Abdelkader To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Osama Abdelkader , Thomas Gleixner , Vladimir Kondratiev , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: panic from init_IRQ if IRQ handler stacks cannot be allocated Date: Fri, 27 Mar 2026 00:23:33 +0100 Message-ID: <20260326232335.60353-1-osama.abdelkader@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" init_irq_stacks() and init_irq_scs() may fail when arch_alloc_vmap_stack or scs_alloc return NULL. Return -ENOMEM from both and call panic() once from init_IRQ(), covering per-CPU IRQ stacks and shadow IRQ stacks consistently. Signed-off-by: Osama Abdelkader --- arch/riscv/kernel/irq.c | 43 ++++++++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index b6af20bc300f..43392276f7f8 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -5,6 +5,7 @@ * Copyright (C) 2018 Christoph Hellwig */ =20 +#include #include #include #include @@ -75,41 +76,53 @@ DECLARE_PER_CPU(ulong *, irq_shadow_call_stack_ptr); DEFINE_PER_CPU(ulong *, irq_shadow_call_stack_ptr); #endif =20 -static void init_irq_scs(void) +static int __init init_irq_scs(void) { int cpu; + void *s; =20 if (!scs_is_enabled()) - return; + return 0; =20 - for_each_possible_cpu(cpu) - per_cpu(irq_shadow_call_stack_ptr, cpu) =3D - scs_alloc(cpu_to_node(cpu)); + for_each_possible_cpu(cpu) { + s =3D scs_alloc(cpu_to_node(cpu)); + if (!s) + return -ENOMEM; + per_cpu(irq_shadow_call_stack_ptr, cpu) =3D s; + } + + return 0; } =20 DEFINE_PER_CPU(ulong *, irq_stack_ptr); =20 #ifdef CONFIG_VMAP_STACK -static void init_irq_stacks(void) +static int __init init_irq_stacks(void) { int cpu; ulong *p; =20 for_each_possible_cpu(cpu) { p =3D arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu)); + if (!p) + return -ENOMEM; per_cpu(irq_stack_ptr, cpu) =3D p; } + + return 0; } #else /* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned= . */ DEFINE_PER_CPU_ALIGNED(ulong [IRQ_STACK_SIZE/sizeof(ulong)], irq_stack); =20 -static void init_irq_stacks(void) +static int __init init_irq_stacks(void) { int cpu; =20 for_each_possible_cpu(cpu) per_cpu(irq_stack_ptr, cpu) =3D per_cpu(irq_stack, cpu); + + return 0; } #endif /* CONFIG_VMAP_STACK */ =20 @@ -129,8 +142,15 @@ void do_softirq_own_stack(void) #endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */ =20 #else -static void init_irq_scs(void) {} -static void init_irq_stacks(void) {} +static int __init init_irq_scs(void) +{ + return 0; +} + +static int __init init_irq_stacks(void) +{ + return 0; +} #endif /* CONFIG_IRQ_STACKS */ =20 int arch_show_interrupts(struct seq_file *p, int prec) @@ -141,8 +161,9 @@ int arch_show_interrupts(struct seq_file *p, int prec) =20 void __init init_IRQ(void) { - init_irq_scs(); - init_irq_stacks(); + if (init_irq_stacks() || init_irq_scs()) + panic("Failed to allocate IRQ stack resources\n"); + irqchip_init(); if (!handle_arch_irq) panic("No interrupt controller found."); --=20 2.43.0