From nobody Thu Apr 2 18:53:51 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A33833A3800; Thu, 26 Mar 2026 19:35:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774553704; cv=none; b=F2MgnVfUDobXPWbua9bxdR7+V+NjF56pfT9nm9tRjxDHYf1XC6zH0YtKX53waqTe4hQzHqM4dSoM0BYppHrhPUg6+ddfMGGOhuoMSIjvo4OvTu+TwEhhQa66J7+ch+rnAiWqYqi/eTjVLxQLpqV4O7Q4zDiFv7Wly5H6wk7lcF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774553704; c=relaxed/simple; bh=AsXZHe8dhzo/iV7ai1HnoAnUoNxuSgEq0RdX3yPSBFs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XHPhGkNpfFk6KyBanykOg9PJFO7V9KUpFJo0fEzgbwe+Z+rp3vm8LpmaUqy2OHgZnTilXisFxJDRLNSJT8zqw6jFEkoCuawHaY1mlHyLKMeGCg01Iyq7R/mpEvENuTNQbBZ9Z2jrMF7fuwX0zPR5XxXJToFeszl+wr7SGVyIbT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Q4PoJyzR; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Q4PoJyzR" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 6E01526FA1; Thu, 26 Mar 2026 20:34:59 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id VuYjDAo8Y4VK; Thu, 26 Mar 2026 20:34:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1774553698; bh=AsXZHe8dhzo/iV7ai1HnoAnUoNxuSgEq0RdX3yPSBFs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Q4PoJyzR3ffICE6eNHZdkYrxBPMNCbZUGKrDnhYfHl/j844SsKPfNg4uV1V7+M2Uf KRbMQ81yFSWwNu9CWyJvMzR/NrmXB5GpbN2P0fpcVtu2tcUf8Wo+HoqKbwcRUY7caw +f1qh3N1tYhpcKFQVOZFE4dAuSJUxu7DSbhOaJhuL40tC6xrk8y/WCC50od7Q9ahWx FLIcaXgbzNIv9E5locJHEmsdS42ZNxQ8q3SELbCWp02va1n1BDRS8gUixcX2cDge5Y 6/cIzpTQ+2Zx/weOGnn76jchmo8oq3W/iNUaEmQzn0ZA2b97lppj/w9ASAGCgv0D6Q 9m2VEA0Vqf1Wg== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH 1/6] phy: realtek: usb2: introduce vstatus/new_reg_req variables to driver data Date: Fri, 27 Mar 2026 00:34:14 +0500 Message-ID: <20260326193419.48419-2-adilov@disroot.org> In-Reply-To: <20260326193419.48419-1-adilov@disroot.org> References: <20260326193419.48419-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In RTL9607C SoC, the vstatus register is located at a certain offset from the base and so introduce the vstatus_offset to handle it. Busy bit of the vstatus and new_reg_req bit are also different and so introduce these variables to the driver data as well. Add these variables to the pre-existing phy cfg structs for RTD SoCs and assign them the default values. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 59 ++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 11 deletions(-) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index 248550ef98ca..f5d2f0c3376a 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -64,6 +64,9 @@ struct phy_reg { void __iomem *reg_wrap_vstatus; void __iomem *reg_gusb2phyacc0; int vstatus_index; + int vstatus_offset; + int vstatus_busy; + int new_reg_req; }; =20 struct phy_data { @@ -96,6 +99,9 @@ struct phy_cfg { bool do_toggle_driving; bool use_default_parameter; bool is_double_sensitivity_mode; + int vstatus_offset; + int vstatus_busy; + int new_reg_req; }; =20 struct phy_parameter { @@ -162,21 +168,21 @@ static char rtk_phy_read(struct phy_reg *phy_reg, cha= r addr) addr -=3D OFFEST_PHY_READ; =20 /* polling until VBusy =3D=3D 0 */ - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D low nibble of addr, and set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D high nibble of addr, and set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 @@ -194,25 +200,25 @@ static int rtk_phy_write(struct phy_reg *phy_reg, cha= r addr, char data) int ret =3D 0; =20 /* write data to VStatusOut2 (data output to phy) */ - writel((u32)data << shift_bits, reg_wrap_vstatus); + writel((u32)data << shift_bits, reg_wrap_vstatus + phy_reg->vstatus_offse= t); =20 - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D low nibble of addr, set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D high nibble of addr, set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); + val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 @@ -957,6 +963,7 @@ static int get_phy_data_by_efuse(struct rtk_phy *rtk_ph= y, =20 static int parse_phy_data(struct rtk_phy *rtk_phy) { + struct phy_cfg *phy_cfg =3D rtk_phy->phy_cfg; struct device *dev =3D rtk_phy->dev; struct device_node *np =3D dev->of_node; struct phy_parameter *phy_parameter; @@ -974,6 +981,9 @@ static int parse_phy_data(struct rtk_phy *rtk_phy) phy_parameter->phy_reg.reg_wrap_vstatus =3D of_iomap(np, 0); phy_parameter->phy_reg.reg_gusb2phyacc0 =3D of_iomap(np, 1) + index; phy_parameter->phy_reg.vstatus_index =3D index; + phy_parameter->phy_reg.vstatus_offset =3D phy_cfg->vstatus_offset; + phy_parameter->phy_reg.vstatus_busy =3D phy_cfg->vstatus_busy; + phy_parameter->phy_reg.new_reg_req =3D phy_cfg->new_reg_req; =20 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) phy_parameter->inverse_hstx_sync_clock =3D true; @@ -1085,6 +1095,9 @@ static const struct phy_cfg rtd1295_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1395_phy_cfg =3D { @@ -1109,6 +1122,9 @@ static const struct phy_cfg rtd1395_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1395_phy_cfg_2port =3D { @@ -1133,6 +1149,9 @@ static const struct phy_cfg rtd1395_phy_cfg_2port =3D= { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1619_phy_cfg =3D { @@ -1155,6 +1174,9 @@ static const struct phy_cfg rtd1619_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1319_phy_cfg =3D { @@ -1181,6 +1203,9 @@ static const struct phy_cfg rtd1319_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1312c_phy_cfg =3D { @@ -1206,6 +1231,9 @@ static const struct phy_cfg rtd1312c_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1619b_phy_cfg =3D { @@ -1231,6 +1259,9 @@ static const struct phy_cfg rtd1619b_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1319d_phy_cfg =3D { @@ -1256,6 +1287,9 @@ static const struct phy_cfg rtd1319d_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1315e_phy_cfg =3D { @@ -1282,6 +1316,9 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct of_device_id usbphy_rtk_dt_match[] =3D { --=20 2.53.0 From nobody Thu Apr 2 18:53:51 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4E463A1E96; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="UrozqLWt" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 6EBF0262F5; Thu, 26 Mar 2026 20:35:02 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id DlgneAx83vLb; Thu, 26 Mar 2026 20:35:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1774553701; bh=vOZf6eE42IzDhkHYxccK5Q1lOSa6x6I72x6AYuJTPuQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=UrozqLWtWrC4HYdJFVg8zlwd5WeuQjjoGIXlTQ0R3vqt6kFoPbtjoZkhS5gWyk6CZ DLby+fvxY2L+0vAqVL632kBixCMlRuF2L5Fuk/KnQomy5aTKczUWXcmpY6MR70B6Z3 Pak8wN0KVeRRnGqcunEu86mYTEXH6hY+imDcSXTrWfSWAu7OqaPWSHGYtivFjkhc0B gBCcU+uc3tZMxpFLTTdZ35/I5UreCvTS9WGXf4rgor7aKhmJKeXpGsScveapBEt+u2 ynyD6s8qJMC7UgIcu0o1F9F8OPHowtTo6C3aumdkLHEfIcPgsPQO/G8XiJlLrb1g+b yj35yLnir8Zrg== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH 2/6] phy: realtek: usb2: introduce read and write functions to driver data Date: Fri, 27 Mar 2026 00:34:15 +0500 Message-ID: <20260326193419.48419-3-adilov@disroot.org> In-Reply-To: <20260326193419.48419-1-adilov@disroot.org> References: <20260326193419.48419-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL9607C is a big endian SoC but has little endian USB host controller and thus, reads and writes to the reg_gusb2phyacc0 should go through le32_to_cpu and cpu_to_le32 functions respectively. This doesn't apply to vstatus register though. To handle this situation, introduce read and write functions to the driver data and create 2 variations of reads and write function with le32 function in it and without. Adjust all instances of utmi_wait_register function to now include the read function as one of its arguments. Assign the existing phy configuration for RTD SoCs to the default phy_read and phy_write functions. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 73 ++++++++++++++++++++++++------ 1 file changed, 60 insertions(+), 13 deletions(-) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index f5d2f0c3376a..e65b8525b88b 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -67,6 +67,9 @@ struct phy_reg { int vstatus_offset; int vstatus_busy; int new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; =20 struct phy_data { @@ -102,6 +105,9 @@ struct phy_cfg { int vstatus_offset; int vstatus_busy; int new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; =20 struct phy_parameter { @@ -128,6 +134,26 @@ struct rtk_phy { struct dentry *debug_dir; }; =20 +static inline u32 phy_read(void __iomem *reg) +{ + return readl(reg); +} + +static inline u32 phy_read_le(void __iomem *reg) +{ + return le32_to_cpu(readl(reg)); +} + +static inline void phy_write(u32 val, void __iomem *reg) +{ + writel(val, reg); +} + +static inline void phy_write_le(u32 val, void __iomem *reg) +{ + writel(cpu_to_le32(val), reg); +} + /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */ static inline int page_addr_to_array_index(u8 addr) { @@ -144,12 +170,13 @@ static inline u8 array_index_to_page_addr(int index) #define PHY_IO_TIMEOUT_USEC (50000) #define PHY_IO_DELAY_US (100) =20 -static inline int utmi_wait_register(void __iomem *reg, u32 mask, u32 resu= lt) +static inline int utmi_wait_register(u32 (*read)(void __iomem *reg), void = __iomem *reg, u32 mask, + u32 result) { int ret; unsigned int val; =20 - ret =3D read_poll_timeout(readl, val, ((val & mask) =3D=3D result), + ret =3D read_poll_timeout(read, val, ((val & mask) =3D=3D result), PHY_IO_DELAY_US, PHY_IO_TIMEOUT_USEC, false, reg); if (ret) { pr_err("%s can't program USB phy\n", __func__); @@ -168,25 +195,25 @@ static char rtk_phy_read(struct phy_reg *phy_reg, cha= r addr) addr -=3D OFFEST_PHY_READ; =20 /* polling until VBusy =3D=3D 0 */ - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D low nibble of addr, and set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D high nibble of addr, and set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 - val =3D readl(reg_gusb2phyacc0); + val =3D phy_reg->read(reg_gusb2phyacc0); =20 return (char)(val & PHY_REG_DATA_MASK); } @@ -202,23 +229,23 @@ static int rtk_phy_write(struct phy_reg *phy_reg, cha= r addr, char data) /* write data to VStatusOut2 (data output to phy) */ writel((u32)data << shift_bits, reg_wrap_vstatus + phy_reg->vstatus_offse= t); =20 - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D low nibble of addr, set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D high nibble of addr, set PHY_NEW_REG_REQ */ val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 @@ -984,6 +1011,8 @@ static int parse_phy_data(struct rtk_phy *rtk_phy) phy_parameter->phy_reg.vstatus_offset =3D phy_cfg->vstatus_offset; phy_parameter->phy_reg.vstatus_busy =3D phy_cfg->vstatus_busy; phy_parameter->phy_reg.new_reg_req =3D phy_cfg->new_reg_req; + phy_parameter->phy_reg.read =3D phy_cfg->read; + phy_parameter->phy_reg.write =3D phy_cfg->write; =20 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) phy_parameter->inverse_hstx_sync_clock =3D true; @@ -1098,6 +1127,8 @@ static const struct phy_cfg rtd1295_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1395_phy_cfg =3D { @@ -1125,6 +1156,8 @@ static const struct phy_cfg rtd1395_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1395_phy_cfg_2port =3D { @@ -1152,6 +1185,8 @@ static const struct phy_cfg rtd1395_phy_cfg_2port =3D= { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1619_phy_cfg =3D { @@ -1177,6 +1212,8 @@ static const struct phy_cfg rtd1619_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1319_phy_cfg =3D { @@ -1206,6 +1243,8 @@ static const struct phy_cfg rtd1319_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1312c_phy_cfg =3D { @@ -1234,6 +1273,8 @@ static const struct phy_cfg rtd1312c_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1619b_phy_cfg =3D { @@ -1262,6 +1303,8 @@ static const struct phy_cfg rtd1619b_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1319d_phy_cfg =3D { @@ -1290,6 +1333,8 @@ static const struct phy_cfg rtd1319d_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct phy_cfg rtd1315e_phy_cfg =3D { @@ -1319,6 +1364,8 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D phy_read, + .write =3D phy_write, }; =20 static const struct of_device_id usbphy_rtk_dt_match[] =3D { --=20 2.53.0 From nobody Thu Apr 2 18:53:51 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C63A3A6B61; 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charset="utf-8" Add the "realtek,rtl9607-usb2phy" compatible for USB2 PHY on the RTL9607C SoC series. Add a resets property to properties to describe the usb2phy reset line. In RTL9607C, USB2 PHY reset line is from "IP Enable controller" which is multipurpose and handle activating various SoC peripherals. It is unclear whether RTD SoCs have something similar to that but make it available to them anyway. RTL9607C requires the "resets" to be specified so add the corresponding if check for the "realtek,rtl9607-usb2phy" compatible. Signed-off-by: Rustam Adilov --- .../bindings/phy/realtek,usb2phy.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml b/D= ocumentation/devicetree/bindings/phy/realtek,usb2phy.yaml index 9911ada39ee7..cdc7b72e5f60 100644 --- a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml @@ -11,10 +11,12 @@ maintainers: - Stanley Chang =20 description: | - Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoC= s. + Realtek USB 2.0 PHY support the digital home center (DHC) RTD and + RTL9607C series SoCs. The USB 2.0 PHY driver is designed to support the XHCI controller. The S= oCs support multiple XHCI controllers. One PHY device node maps to one XHCI controller. + This driver also supports the OCHI and EHCI controllers. =20 RTD1295/RTD1619 SoCs USB The USB architecture includes three XHCI controllers. @@ -57,6 +59,12 @@ description: | XHCI controller#1 -- usb2phy -- phy#0 XHCI controller#2 -- usb2phy -- phy#0 =20 + RTL9607C SoCs USB + The USB architecture includes OHCI and EHCI controllers. + Both of them map to one USB2.0 PHY. + OHCI controller#0 -- usb2phy -- phy#0 + EHCI controller#0 -- usb2phy -- phy#0 + properties: compatible: enum: @@ -69,6 +77,7 @@ properties: - realtek,rtd1395-usb2phy-2port - realtek,rtd1619-usb2phy - realtek,rtd1619b-usb2phy + - realtek,rtl9607-usb2phy =20 reg: items: @@ -130,6 +139,9 @@ properties: minimum: -8 maximum: 8 =20 + resets: + maxItems: 1 + required: - compatible - reg @@ -157,6 +169,15 @@ allOf: then: properties: realtek,driving-level-compensate: false + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl9607-usb2phy + then: + required: + - resets =20 additionalProperties: false =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:51 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6CA53A6F0A; Thu, 26 Mar 2026 19:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774553711; cv=none; b=t5774wlv5vo/uY3wxYeF5G1OmrHFfKZIOGm8HxUC5lZIoTdGZcjix9TOQPdZRzh45f1Psg+5+3Dto66i40Ar+sADDLh4R4GGKS959LN2xizuC/j/aG8xOOWKzcD6akXsc0yHgUccfnP7BpRr6fWHYVXBhto5VtvmgJBwbRFzzwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774553711; c=relaxed/simple; bh=A2n8k6aIgmIJ4ucRQWwBcogmliaMS8yEWnuf1xcyKuE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pob6cr5e1C3WWBVtEumTlGk9ASelJvCvrlJlBChy81fm3xJcYTxFfy/Jb/dEmFXzeBg5kKP+C9wqZjzRW/zCje9kwU9YUT3b87UoJNhbj5sp8yWHADcEyZF8k1n7mvEeIS5dyylG2zThDPjOGK1goPHJI6no9iDMrV1igEwKa3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=e13b6Eok; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="e13b6Eok" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 43ABD26FFC; Thu, 26 Mar 2026 20:35:08 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 6WwhpugZu9q4; Thu, 26 Mar 2026 20:35:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1774553707; bh=A2n8k6aIgmIJ4ucRQWwBcogmliaMS8yEWnuf1xcyKuE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=e13b6EokfOfBvap7f5YTsZCTpSjPuyrx4uHeU4fSdPPHFLFi2TF4dUEG+g+mORS55 R/sHzd+YS9mmYJ6nD/RBSWVw2VIFSVZjmQUFnzcZTp4W/LmcpqhviIyFb8AFslEOio 9O4oD/IdXawgRBJwOMWrBZijWEENqOCPjVpgpEOupWoHuRGjj8cSrEYaCB/Uc0sGyP UPvUVOYldCorL0a101ZZj3qPiRWa12hvENW8+ZSmKZAoFt60uhbIYDQuKxPIjz+bpq yXOCDUQDXCQgf0NKFgY4HT2qHtQPfcDJQx/Ko/NVVyt0d/R+AMy5Fgk6aurL93yo2O X/MlQ7ap046Tw== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH 4/6] phy: realtek: usb2: introduce reset controller struct Date: Fri, 27 Mar 2026 00:34:17 +0500 Message-ID: <20260326193419.48419-5-adilov@disroot.org> In-Reply-To: <20260326193419.48419-1-adilov@disroot.org> References: <20260326193419.48419-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In RTL9607C, there is so called "IP Enable Controller" which resemble reset controller with reset lines and is used for various things like USB, PCIE, GMAC and such. Introduce the reset_control struct to this driver to handle deasserting usb2 phy reset line. Make use of the function devm_reset_control_array_get_optional_exclusive() function to get the reset controller and since existing RTD SoCs don't specify the resets we can have a cleaner code. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index e65b8525b88b..070cba1e0e0a 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 /* GUSB2PHYACCn register */ @@ -130,6 +131,7 @@ struct rtk_phy { struct phy_cfg *phy_cfg; int num_phy; struct phy_parameter *phy_parameter; + struct reset_control *phy_rst; =20 struct dentry *debug_dir; }; @@ -602,6 +604,10 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, in= t index) phy_parameter =3D &((struct phy_parameter *)rtk_phy->phy_parameter)[index= ]; phy_reg =3D &phy_parameter->phy_reg; =20 + reset_control_deassert(rtk_phy->phy_rst); + + mdelay(5); + if (phy_cfg->use_default_parameter) { dev_dbg(rtk_phy->dev, "%s phy#%d use default parameter\n", __func__, index); @@ -1069,6 +1075,12 @@ static int rtk_usb2phy_probe(struct platform_device = *pdev) =20 rtk_phy->num_phy =3D phy_cfg->num_phy; =20 + rtk_phy->phy_rst =3D devm_reset_control_array_get_optional_exclusive(dev); + if (IS_ERR(rtk_phy->phy_rst)) { + dev_err(dev, "usb2 phy resets are not working\n"); + return PTR_ERR(rtk_phy->phy_rst); + } + ret =3D parse_phy_data(rtk_phy); if (ret) goto err; --=20 2.53.0 From nobody Thu Apr 2 18:53:51 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B4093A6417; Thu, 26 Mar 2026 19:35:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774553714; cv=none; b=B1nvBMubRFLH+UmINsFLxUXLt8MZctbMa4LwOx5UrYfNZPdDc69pcdULt+dw8MwKHlctWIF2NJq7G+iLd8e+uI+CQlDNMdoWKP/WWewr27hkP8TQmuuJhKr5RNnWEJiNZsvhTukZtAcej5WENV9k/HpzW+KzMn2+R5tfZ6WSzrU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774553714; c=relaxed/simple; bh=QaMxN5JIjzz6HwV6IhF0gYp+uTretPZBpdnTbCTSpv0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iaH801mFegEAY5O4V04ejjHGPQRT/9NDLHMO8pXFWZSkrFLgvKwb1PkP5U87zO3Bzm7zFR5OCVfnMvfbVJJ0A2i7+Bq86fe1fs/7i+DkfCcz1dUkdvv1dneeFp10w93LwINazFtCj6jYbGQiCATinEYe9ouMNghfBkF1d3vH/cg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=h+IjJEeo; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="h+IjJEeo" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 358D926471; Thu, 26 Mar 2026 20:35:11 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id PYjQ0TBXeGoz; Thu, 26 Mar 2026 20:35:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1774553710; bh=QaMxN5JIjzz6HwV6IhF0gYp+uTretPZBpdnTbCTSpv0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=h+IjJEeojumeSY440gmDf8576U5m7dfOj4J5AtGSBqxovKI9Lgtq82A87W89vB2Eg q6DHyqb/JeEC1Dm3+N053gD7jUpFNSxhJ1jap9/JmKiAYZJxF8aWo+ZkYkQyHqVzEy lBbD9CNgEXCBJcDFfTKixaCxzl9Q4jMW/nTA+kAHJ/K4Bj9P3/3l3Q9pL0FqFsMOEX EmHQDfua9nlnngNQJs+umjjpTexnmELq2DMPooXnJkodsh7gkMIybrLFUhGubV2Oab NHey9SvkDdu9smqVWkwG3Py2JGqdoS0c3og+kcv/w8/OHF3P7lY8x9ZrZ7oXLKDKXR 7DkiPLRx9mC6Q== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY Date: Fri, 27 Mar 2026 00:34:18 +0500 Message-ID: <20260326193419.48419-6-adilov@disroot.org> In-Reply-To: <20260326193419.48419-1-adilov@disroot.org> References: <20260326193419.48419-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the usb2 phy of RTL9607C series based SoCs. Add the macros and phy config struct for rtl9607. RTL9607C requires to clear a "force host disconnect" bit in the specific register (which is at an offset from reg_wrap_vstatus) before proceeding with phy parameter writes. Add the bool variable to the driver data struct and hide this whole procedure under the if statement that checks this new variable. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index 070cba1e0e0a..bf22d12681dc 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -26,6 +26,12 @@ #define PHY_VCTRL_SHIFT 8 #define PHY_REG_DATA_MASK 0xff =20 +#define PHY_9607_VSTS_BUSY BIT(17) +#define PHY_9607_NEW_REG_REQ BIT(13) + +#define PHY_9607_FORCE_DISCONNECT_REG 0x10 +#define PHY_9607_FORCE_DISCONNECT_BIT BIT(5) + #define GET_LOW_NIBBLE(addr) ((addr) & 0x0f) #define GET_HIGH_NIBBLE(addr) (((addr) & 0xf0) >> 4) =20 @@ -109,6 +115,7 @@ struct phy_cfg { =20 u32 (*read)(void __iomem *reg); void (*write)(u32 val, void __iomem *reg); + bool force_host_disconnect; }; =20 struct phy_parameter { @@ -614,6 +621,16 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, in= t index) goto do_toggle; } =20 + if (phy_cfg->force_host_disconnect) { + /* disable force-host-disconnect */ + u32 temp =3D readl(phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT= _REG); + + temp &=3D ~PHY_9607_FORCE_DISCONNECT_BIT; + writel(temp, phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT_REG); + + mdelay(10); + } + /* Set page 0 */ phy_data_page =3D phy_cfg->page0; rtk_phy_set_page(phy_reg, 0); @@ -1141,6 +1158,7 @@ static const struct phy_cfg rtd1295_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1395_phy_cfg =3D { @@ -1170,6 +1188,7 @@ static const struct phy_cfg rtd1395_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1395_phy_cfg_2port =3D { @@ -1199,6 +1218,7 @@ static const struct phy_cfg rtd1395_phy_cfg_2port =3D= { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1619_phy_cfg =3D { @@ -1226,6 +1246,7 @@ static const struct phy_cfg rtd1619_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1319_phy_cfg =3D { @@ -1257,6 +1278,7 @@ static const struct phy_cfg rtd1319_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1312c_phy_cfg =3D { @@ -1287,6 +1309,7 @@ static const struct phy_cfg rtd1312c_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1619b_phy_cfg =3D { @@ -1317,6 +1340,7 @@ static const struct phy_cfg rtd1619b_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1319d_phy_cfg =3D { @@ -1347,6 +1371,7 @@ static const struct phy_cfg rtd1319d_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, }; =20 static const struct phy_cfg rtd1315e_phy_cfg =3D { @@ -1378,6 +1403,37 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .new_reg_req =3D PHY_NEW_REG_REQ, .read =3D phy_read, .write =3D phy_write, + .force_host_disconnect =3D false, +}; + +static const struct phy_cfg rtl9607_phy_cfg =3D { + .page0_size =3D MAX_USB_PHY_PAGE0_DATA_SIZE, + .page0 =3D { [0] =3D {0xe0, 0x95}, + [4] =3D {0xe4, 0x6a}, + [12] =3D {0xf3, 0x31}, }, + .page1_size =3D MAX_USB_PHY_PAGE1_DATA_SIZE, + .page1 =3D { [0] =3D {0xe0, 0x26}, }, + .page2_size =3D MAX_USB_PHY_PAGE2_DATA_SIZE, + .page2 =3D { [7] =3D {0xe7, 0x33}, }, + .num_phy =3D 1, + .check_efuse =3D false, + .check_efuse_version =3D CHECK_EFUSE_V2, + .efuse_dc_driving_rate =3D EFUS_USB_DC_CAL_RATE, + .dc_driving_mask =3D 0x1f, + .efuse_dc_disconnect_rate =3D EFUS_USB_DC_DIS_RATE, + .dc_disconnect_mask =3D 0xf, + .usb_dc_disconnect_at_page0 =3D true, + .do_toggle =3D true, + .do_toggle_driving =3D false, + .driving_updated_for_dev_dis =3D 0x8, + .use_default_parameter =3D false, + .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0xc, + .vstatus_busy =3D PHY_9607_VSTS_BUSY, + .new_reg_req =3D PHY_9607_NEW_REG_REQ, + .read =3D phy_read_le, + .write =3D phy_write_le, + .force_host_disconnect =3D true, }; =20 static const struct of_device_id usbphy_rtk_dt_match[] =3D { @@ -1390,6 +1446,7 @@ static const struct of_device_id usbphy_rtk_dt_match[= ] =3D { { .compatible =3D "realtek,rtd1395-usb2phy-2port", .data =3D &rtd1395_phy= _cfg_2port }, { .compatible =3D "realtek,rtd1619-usb2phy", .data =3D &rtd1619_phy_cfg }, { .compatible =3D "realtek,rtd1619b-usb2phy", .data =3D &rtd1619b_phy_cfg= }, + { .compatible =3D "realtek,rtl9607-usb2phy", .data =3D &rtl9607_phy_cfg }, {}, }; MODULE_DEVICE_TABLE(of, usbphy_rtk_dt_match); --=20 2.53.0 From nobody Thu Apr 2 18:53:51 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 468A23A7582; Thu, 26 Mar 2026 19:35:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="mV7euzOo" Received: from [127.0.0.1] (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 7A83A267D8; Thu, 26 Mar 2026 20:35:13 +0100 (CET) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 3UicETYF_tVn; Thu, 26 Mar 2026 20:35:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1774553712; bh=6B7686z3QUopU/zWMAAwBVlHDWV9IFVlgjbzHESJ76k=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=mV7euzOoPEwIOGE4BSw0d9ECKi2Rt49aJrN2gZ+qi6hq7mbpy6jeBLKq54Ybs+gsr l4U9GEX2BFR+Xeswy+jbyoWl4+fRXdkMlHAN1/eaYvPxHWtp9pTVeAEJFNUvvya0Pi juaXWgLvqZJMkjGZ9uy9hsGCr38z+g8lu35GP0pbGW6BII+MvBELBIsYsf5vALNm6c Ge2R7kN3Phq7aX8J0i4mRhM3ov11SgkKnbkoFfwUV72tnT2zjkevqbm/9Vqxjw1Uj4 pTRxyL58SOffIqVMKrgzHcw58MRGLSSkUy101AWD2DlVg6efcTjY9N/jFoQUA0Ec3m mdXe3QM76Kw9Q== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov Subject: [PATCH 6/6] phy: realtek: usb2: Make configs available for MACH_REALTEK_RTL Date: Fri, 27 Mar 2026 00:34:19 +0500 Message-ID: <20260326193419.48419-7-adilov@disroot.org> In-Reply-To: <20260326193419.48419-1-adilov@disroot.org> References: <20260326193419.48419-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the MACH_REALTEK_RTL to the if statement to make the config options available for Realtek RTL SoCs as well. Signed-off-by: Rustam Adilov --- drivers/phy/realtek/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/realtek/Kconfig b/drivers/phy/realtek/Kconfig index 75ac7e7c31ae..f9eadffacd18 100644 --- a/drivers/phy/realtek/Kconfig +++ b/drivers/phy/realtek/Kconfig @@ -3,7 +3,7 @@ # Phy drivers for Realtek platforms # =20 -if ARCH_REALTEK || COMPILE_TEST +if ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST =20 config PHY_RTK_RTD_USB2PHY tristate "Realtek RTD USB2 PHY Transceiver Driver" --=20 2.53.0