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charset="utf-8" For CPSW5G QSGMII ports, CPSW assumes SERDES to be configured. Since it may not be always true, add SERDES phys to guarantee it. Fixes: 496cdc82e05f ("arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5= G ports in QSGMII mode") Signed-off-by: Chintan Vankar --- This patch is based on commit "0138af2472df" of origin/master branch of Linux repo. arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/a= rch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 6432ca08ee8e..4824d53c95bb 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -32,7 +32,8 @@ &cpsw0_port1 { phy-handle =3D <&cpsw5g_phy0>; phy-mode =3D "qsgmii"; mac-address =3D [00 00 00 00 00 00]; - phys =3D <&cpsw0_phy_gmii_sel 1>; + phys =3D <&cpsw0_phy_gmii_sel 1>, <&serdes0_qsgmii_link>; + phy-names =3D "mac", "serdes"; }; =20 &cpsw0_port2 { --=20 2.34.1