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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Mario Limonciello Subject: [PATCH v4 03/12] amd-pstate: Make certain freq_attrs conditionally visible Date: Thu, 26 Mar 2026 17:17:47 +0530 Message-ID: <20260326114756.20374-4-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|SJ2PR12MB8881:EE_ X-MS-Office365-Filtering-Correlation-Id: 27b7a93b-a3f3-4e67-d3fc-08de8b2d9715 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: 7HYRgCe6lvHAZ2XBjLMELaTNJDMRRZD5dHZGhsmXanG2Sgyu4Wu/ywD0FCBSQDNyslNyM/LtYrVDvvt8ZEgZeWRXPf/bA1m9GP48wg3wJ5LyCcVa7aJwIP38mN/GOG2iKEFSoJUrOPqNpO6P820B22gnr1DfUrMI3Mb1g0yPH+2WTABovW1TTSk53DwYOjudK1F6Y6RnFg11hT6hdYh7oBKGD2Re1HWpiLbou9rfwsnLr6ksMGrLHKLNg58HTu/wsZS7ysp+TOi1rDEzBtyh8PgnnEDoBAR9YvaNYXN/Vfl2nlW3HOyFAxwlQrzrZJkgz/Ie2GNsNJBhI6GJYqvQgEr+2GtKCvNHkGoSYyZOMpPfbWBXN+DDg0+kze79fNEp32DsxNyTQ3c/DCg4WxB+sZ08KICCcT5JJUCywhOKSgzXnXW4QHNrDQUSwC3740G2QJD3csRJgeYqGizrDyWcmHeZKy8P2K5FyB1MbKgrv4IwheFZ9TxqHb56HYemGmv+J51wpkrhLwkjeO0eKEcqYotL9EVd5+2Uap/L6b9tXT8d7jPy2A/VGt3JBVg5/p3glQRig0DRB+BaMb7d+mbMDBK9Qhd6dh3rJfbg5gXZqbEHHrazNNrGaa5PKOkpRtlhamHwQ6dwBFETzKCjiFZPFRxdZSIL3WHXfh99wgIRlOieIlMbe+jLBTXBQO+OBkZC5pQoUzx0aysf1AjTpQ5bv88ZoUKSjtIU/b/RuD9mUX2DBIj81y6uA3cuDmsDc7RmKqRsFXXLAipTwnB/Dg2n/g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hSMFu9TymSQ3OwZFJ2/D7Wk8fmOLZcJmxcMBcOhdHhK2QUIlr5+ixGRFom2EVZfvhMo5eylkA3HoTAdb6NPiQJwz0llZi4HxvxZ7flLG+Py62/ilsdE9nkeSDtpZOa0e4k9hB65uJb22cFa9EjXZlW5LAUW4XCcqqTxBoOgTcPcpFZDOAJ5rvIiehVhapfaLnd71aCJKZH7s3DEeDJTX1JDl0JODNbF9QuNl7tGz745rBjUZzfqcWUyz77dGZqFaEbfcVFjXNeQhrG9q6B6zYknU+VTc3aJFzpQLZFCTpKEX3wTiiimkKBD36L0hNOg9QwdJ+0CMNNs8KfdMvwddY+eI5HMOd+frNVmdOYu564FRgKCw3oGnq2YBvDf79pZqNrrDfFs90Q/t6+yMGREwSKpTxLR7sl8tjq9hQzMDjuHRB8MGQZklEVC8AXtXDZV7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:25.7089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27b7a93b-a3f3-4e67-d3fc-08de8b2d9715 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8881 Content-Type: text/plain; charset="utf-8" Certain amd_pstate freq_attrs such as amd_pstate_hw_prefcore and amd_pstate_prefcore_ranking are enabled even when preferred core is not supported on the platform. Similarly there are common freq_attrs between the amd-pstate and the amd-pstate-epp drivers (eg: amd_pstate_max_freq, amd_pstate_lowest_nonlinear_freq, etc.) but are duplicated in two different freq_attr structs. Unify all the attributes in a single place and associate each of them with a visibility function that determines whether the attribute should be visible based on the underlying platform support and the current amd_pstate mode. Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 124 ++++++++++++++++++++++++++--------- 1 file changed, 93 insertions(+), 31 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 24cdeffbcd40..4de2037a414c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1220,12 +1220,87 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } =20 +cpufreq_freq_attr_ro(amd_pstate_max_freq); +cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); + +cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); +cpufreq_freq_attr_rw(energy_performance_preference); +cpufreq_freq_attr_ro(energy_performance_available_preferences); + +struct freq_attr_visibility { + struct freq_attr *attr; + bool (*visibility_fn)(void); +}; + +/* For attributes which are always visible */ +static bool always_visible(void) +{ + return true; +} + +/* Determines whether prefcore related attributes should be visible */ +static bool prefcore_visibility(void) +{ + return amd_pstate_prefcore; +} + +/* Determines whether energy performance preference should be visible */ +static bool epp_visibility(void) +{ + return cppc_state =3D=3D AMD_PSTATE_ACTIVE; +} + +static struct freq_attr_visibility amd_pstate_attr_visibility[] =3D { + {&amd_pstate_max_freq, always_visible}, + {&amd_pstate_lowest_nonlinear_freq, always_visible}, + {&amd_pstate_highest_perf, always_visible}, + {&amd_pstate_prefcore_ranking, prefcore_visibility}, + {&amd_pstate_hw_prefcore, prefcore_visibility}, + {&energy_performance_preference, epp_visibility}, + {&energy_performance_available_preferences, epp_visibility}, +}; + +static struct freq_attr **get_freq_attrs(void) +{ + bool attr_visible[ARRAY_SIZE(amd_pstate_attr_visibility)]; + struct freq_attr **attrs; + int i, j, count; + + for (i =3D 0, count =3D 0; i < ARRAY_SIZE(amd_pstate_attr_visibility); i+= +) { + struct freq_attr_visibility *v =3D &amd_pstate_attr_visibility[i]; + + attr_visible[i] =3D v->visibility_fn(); + if (attr_visible[i]) + count++; + } + + /* amd_pstate_{max_freq, lowest_nonlinear_freq, highest_perf} should alwa= ys be visible */ + BUG_ON(!count); + + attrs =3D kcalloc(count + 1, sizeof(struct freq_attr *), GFP_KERNEL); + if (!attrs) + return ERR_PTR(-ENOMEM); + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(amd_pstate_attr_visibility); i++) { + if (!attr_visible[i]) + continue; + + attrs[j++] =3D amd_pstate_attr_visibility[i].attr; + } + + return attrs; +} + static void amd_pstate_driver_cleanup(void) { if (amd_pstate_prefcore) sched_clear_itmt_support(); =20 cppc_state =3D AMD_PSTATE_DISABLE; + kfree(current_pstate_driver->attr); + current_pstate_driver->attr =3D NULL; current_pstate_driver =3D NULL; } =20 @@ -1250,6 +1325,7 @@ static int amd_pstate_set_driver(int mode_idx) =20 static int amd_pstate_register_driver(int mode) { + struct freq_attr **attr =3D NULL; int ret; =20 ret =3D amd_pstate_set_driver(mode); @@ -1258,6 +1334,22 @@ static int amd_pstate_register_driver(int mode) =20 cppc_state =3D mode; =20 + /* + * Note: It is important to compute the attrs _after_ + * re-initializing the cppc_state. Some attributes become + * visible only when cppc_state is AMD_PSTATE_ACTIVE. + */ + attr =3D get_freq_attrs(); + if (IS_ERR(attr)) { + ret =3D (int) PTR_ERR(attr); + pr_err("Couldn't compute freq_attrs for current mode %s [%d]\n", + amd_pstate_get_mode_string(cppc_state), ret); + amd_pstate_driver_cleanup(); + return ret; + } + + current_pstate_driver->attr =3D attr; + /* at least one CPU supports CPB */ current_pstate_driver->boost_enabled =3D cpu_feature_enabled(X86_FEATURE_= CPB); =20 @@ -1399,37 +1491,9 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } =20 -cpufreq_freq_attr_ro(amd_pstate_max_freq); -cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); - -cpufreq_freq_attr_ro(amd_pstate_highest_perf); -cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); -cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); -cpufreq_freq_attr_rw(energy_performance_preference); -cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); =20 -static struct freq_attr *amd_pstate_attr[] =3D { - &amd_pstate_max_freq, - &amd_pstate_lowest_nonlinear_freq, - &amd_pstate_highest_perf, - &amd_pstate_prefcore_ranking, - &amd_pstate_hw_prefcore, - NULL, -}; - -static struct freq_attr *amd_pstate_epp_attr[] =3D { - &amd_pstate_max_freq, - &amd_pstate_lowest_nonlinear_freq, - &amd_pstate_highest_perf, - &amd_pstate_prefcore_ranking, - &amd_pstate_hw_prefcore, - &energy_performance_preference, - &energy_performance_available_preferences, - NULL, -}; - static struct attribute *pstate_global_attributes[] =3D { &dev_attr_status.attr, &dev_attr_prefcore.attr, @@ -1696,7 +1760,6 @@ static struct cpufreq_driver amd_pstate_driver =3D { .set_boost =3D amd_pstate_set_boost, .update_limits =3D amd_pstate_update_limits, .name =3D "amd-pstate", - .attr =3D amd_pstate_attr, }; =20 static struct cpufreq_driver amd_pstate_epp_driver =3D { @@ -1712,7 +1775,6 @@ static struct cpufreq_driver amd_pstate_epp_driver = =3D { .update_limits =3D amd_pstate_update_limits, .set_boost =3D amd_pstate_set_boost, .name =3D "amd-pstate-epp", - .attr =3D amd_pstate_epp_attr, }; =20 /* @@ -1858,7 +1920,7 @@ static int __init amd_pstate_init(void) return ret; =20 global_attr_free: - cpufreq_unregister_driver(current_pstate_driver); + amd_pstate_unregister_driver(0); return ret; } device_initcall(amd_pstate_init); --=20 2.34.1