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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Jonathan Corbet , "Shuah Khan" , Mario Limonciello Subject: [PATCH v4 12/12] Documentation/amd-pstate: Add documentation for amd_pstate_floor_{freq,count} Date: Thu, 26 Mar 2026 17:17:56 +0530 Message-ID: <20260326114756.20374-13-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DE:EE_|CY1PR12MB9675:EE_ X-MS-Office365-Filtering-Correlation-Id: dd55e161-9543-43b9-af57-08de8b2da63c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|376014|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: IgzTaW2kw+CFEyg7gg9QSIT1MU4nTGx7Ez5BfUw5KdW9TSvMBNqlA9d+CY8YhD3uQCkwC8/vcyIek2IcUSvKVoRQeOfgTIVj6OTRCRUbB0Ey6tlxNld+aqL6za1/lb4ZGLPyzhnzahKoVJxVIpE0EtuJId+JHAX0KGAZnQNJtzNFEG3WtYov8K6Ser6QaQ3zNI1KtpAjAetslTNbiFkHgGfIBnniCEWSTcUkzJjmexkcVap92gJqqg86ybAjEPLDcCcesGuPZJLB7oFZVhYcIJQdNj+g/6dU4NV/VGFjMgHXCucPS4FR/7C9ah1Z/JhxWW9MtjQq2btW69OR73EJgA1KGM2IXQOHVsbOoq8LHdoZ+HMRb249Smrtcofz0KEGMXeFjQAULgbGWOXBg74pYuwCZVG1vRs6Fnyi8lKZ12h8jPv8lTekhP/q/YNq2BXKA2wh2p1eBpF9lUiGyGcNIPV/yINedMiTysXONrgO7ucOyajxUD5QVG+iGas0qumB4bFiocyzpP7HTMAwoQYDIMkYG+IsfvfWd0Zdvuhsxq4zle6goQ9EU65ZG14TY3ATJWJH9SQZIsVEmXwd0EivoyWAbcG4unds4Fo33TAKidPCyGTDABjDroZh0faMpq0FUUAjGJAoWN3E8mIN0MzBCy7JXlfF8181AxRPIITVYN4Jm7DXOUYRw5rTlA8MaY6+vY3F8Uok7iH63Mkq8dMppwaWux/hu2J2C7/uskag3ffD4PFnFS+NoqL/vn5y2gHPHNKeblWadZ5BFIOsIwmKFg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(82310400026)(376014)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5IBhJOBH6queeBYjAm6X7lMT5NXresPPvDPIY8v/VutWVV288Hz4P5wJXMWFU6bqf4Do6yW/qy2Pjx6a5c4zgivfSpyILhSkGweNRpjfl+4J+OENhiGZKMvsXle76V8H5FwMyjE/teANpcKd0VLttP0NOZHMR/J8/ngENgtg2cWrb2Ma0znw+DML3oyWMhdvMPfe0UrpnqBLTqr6rSob2a6+rDahu+f4Fyv767xr5ahnoXwZeuH0v5RXH4TWGwnpeQlliaciTlhp0TgCRCBIdYSPNJ5+z2rJcUB/I8V/Y44oTcUuvcXh8tce3RIziW3zpaHR32mBpkGii/+rDnY1TBmIMga6jBcX4Ax2MK/zHLeIXdVI8yJclvdDMmu20VKk0hvEOz/pFxoCcBFExR1RULDVk93mcSS27YeYNG1woDHme9ciyDW6zSIpOTWI3C/R X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:51.1173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd55e161-9543-43b9-af57-08de8b2da63c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9675 Content-Type: text/plain; charset="utf-8" Add documentation for the sysfs files /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq and /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_count. Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index b31a478c28ba..d6c2f233ab23 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -242,6 +242,8 @@ control its functionality at the system level. They are= located in the /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_hw_prefcore /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_count /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_prefcore_ranking =20 =20 @@ -277,6 +279,36 @@ larger numbers are preferred at the time of reading. T= his can change at runtime based on platform conditions. This attribute is read-only. This fi= le is only visible on platforms which support the preferred core feature. =20 +``amd_pstate_floor_freq`` + +The floor frequency associated with each CPU. Userspace can write any +value between ``cpuinfo_min_freq`` and ``scaling_max_freq`` into this +file. When the system is under power or thermal constraints, the +platform firmware will attempt to throttle the CPU frequency to the +value specified in ``amd_pstate_floor_freq`` before throttling it +further. This allows userspace to specify different floor frequencies +to different CPUs. For optimal results, threads of the same core +should have the same floor frequency value. This file is only visible +on platforms that support the CPPC Performance Priority feature. + + +``amd_pstate_floor_count`` + +The number of distinct Floor Performance levels supported by the +platform. For example, if this value is 2, then the number of unique +values obtained from the command ``cat +/sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq | +sort -n | uniq`` should be at most this number for the behavior +described in ``amd_pstate_floor_freq`` to take effect. A zero value +implies that the platform supports unlimited floor performance levels. +This file is only visible on platforms that support the CPPC +Performance Priority feature. + +**Note**: When ``amd_pstate_floor_count`` is non-zero, the frequency to +which the CPU is throttled under power or thermal constraints is +undefined when the number of unique values of ``amd_pstate_floor_freq`` +across all CPUs in the system exceeds ``amd_pstate_floor_count``. + ``energy_performance_available_preferences`` =20 A list of all the supported EPP preferences that could be used for --=20 2.34.1