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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Mario Limonciello Subject: [PATCH v4 01/12] amd-pstate: Fix memory leak in amd_pstate_epp_cpu_init() Date: Thu, 26 Mar 2026 17:17:45 +0530 Message-ID: <20260326114756.20374-2-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|SJ0PR12MB6711:EE_ X-MS-Office365-Filtering-Correlation-Id: 64425196-1fa7-4825-fc83-08de8b2d93ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|376014|18002099003|22082099003|56012099003|13003099007; X-Microsoft-Antispam-Message-Info: EPF3IgN8dAq6EjhfS8xjns84y5QwzdANGjnDeWRorctLfMn71fPsW+y05y3gpEdKYrnP3i3BIGHjIjhC+I2XiKFEKOITBix229eoJ/S8Umh/K2bI5zluGAUWT7xh+V8qOTsgdGEds8r9PyOK17Qg5y+gcSpW2lfZ7ZcPZsJavSbRtjT3nI+udtxyXd5Q/gb9+3VOkO4QtHk4TNFftbOiosq9RVuVP60dBeCJPqBAzOXMYhycexCyn8qpoamHB2igf6dQnPoH9TbFh/HOvSFqBdvPlFvqnmpGqjLJlZPgTl1W+jZYXe13aABF3vTK5RTAtZFwkUcHCNcKNw7IMoo6arcsS0UPeSGRp0fN45kDjogzOAwqmDMuXI9YalFNQPSdn2bhllY3s13ixKq7iLG8Q9LHYnWlHBcMSZxkFtsUKyZOr2dbF3+CgTqzCtPT9V/z8qXItFFbPy9VGtV7Xd0emVUHGFpt30ZZ9nL8fnlzhmEOp4O4Ubq4t7AsgrU+xoxaLZ4Yx2ANM55sur6LHAvM9f42jwW7scuQQmVlMTP5XWAvj9gPtKg15Bu53DQEwTRlcq27hgPIKarE5cGd7wu8AWF+Rq94odxHaoZGchOSL0+8f3DCzGOn/ctiDQ8KjGmOHY0x15XEHPqKCQmyB7ZGkD+w9xPOp14QZGDVA7C8oZKxJtGp8t/KjM7tvjmnE9AXxGcJc+2Pst7Jn4389I1Ti9aPMQEdcWEwsfLi5pQrUYArnBl0nLZ9UnV5iaJA9u3yxu0ZQ9PQklsidjmgYGDY+Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(376014)(18002099003)(22082099003)(56012099003)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vkmPseAYN0KfLhP+rcVcVd1Ukv0jJaamDpr+DVCG4HxTMGF7nO3oFJ6V0mgJ0INn51YGacasnTO/ljiRqiw2X5BGtLtT/my0IT9sW9Gb+ctWH1kqRVnDCLDsiG24DQRh2LpvYibBSx5vhIhRF0aZLluqD5IgA0j7gnk0Y8QERemh/1Ws9/HsY57Iv0NGPdWvNku7IvFFlmDWvcMqRxbpacDr0i5ypV1wqGb0/oAPbW4NfSGQyzwsmahndXzpgUuZQmP4KlqwneJzD+wy14fpaaauV1hVjgYCM+rTGmR6/7HFSBkm137U8xZ6fbkNyXttX9SM0Y+7zL/qRVwoB8noo4SmJvqp+AaL/gseGDE1jmQnyt0ldnNdwjFt3b5Jg3iAPhk3X1bndZbY7fxWjJ/TvsCyz6YLAKv+ur5/sh5Tvqh+0Sq1uDOnYIvLsVKZF1pL X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:20.4057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64425196-1fa7-4825-fc83-08de8b2d93ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6711 Content-Type: text/plain; charset="utf-8" On failure to set the epp, the function amd_pstate_epp_cpu_init() returns with an error code without freeing the cpudata object that was allocated at the beginning of the function. Ensure that the cpudata object is freed before returning from the function. This memory leak was discovered by Claude Opus 4.6 with the aid of Chris Mason's AI review-prompts (https://github.com/masoncl/review-prompts/tree/main/kernel). Assisted-by: Claude:claude-opus-4.6 review-prompts/linux Fixes: f9a378ff6443 ("cpufreq/amd-pstate: Set different default EPP policy = for Epyc and Ryzen") Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5aa9fcd80cf5..d57969c72c9d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1533,7 +1533,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) =20 ret =3D amd_pstate_set_epp(policy, cpudata->epp_default); if (ret) - return ret; + goto free_cpudata1; =20 current_pstate_driver->adjust_perf =3D NULL; =20 --=20 2.34.1 From nobody Thu Apr 2 22:25:45 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012024.outbound.protection.outlook.com [52.101.43.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 918AC3F786B; Thu, 26 Mar 2026 11:48:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.24 ARC-Seal: i=2; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Mario Limonciello Subject: [PATCH v4 02/12] amd-pstate: Update cppc_req_cached in fast_switch case Date: Thu, 26 Mar 2026 17:17:46 +0530 Message-ID: <20260326114756.20374-3-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|PH7PR12MB6977:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b00948a-afad-4cbe-08f9-08de8b2d9574 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|22082099003|56012099003|18002099003|13003099007; X-Microsoft-Antispam-Message-Info: q6E1dwaAiqouqBcK67gJ7N2OK6RFMChVBWnynvx4TjuV1Nb9GMgst06e/JkJXEaN3kFDGcpXx2MBhDt0yjsoNNebc9C4s62nWOMAiH6tGRu9iqEj5x9mcWtx4Nl10k5Cij8fzqenYMx+ycRVSp7JUoEC1B4RKSlkcJSUJ6KmJsfU0biPgNZn39XTZQMKt1E790pmsCvhSmPoV1Ac2dp9nVnCMa6M9ym/faKbFduPP3/+Cj8R/Sj67GqA0nkumYihne2Vqu3g/dBquL6IGieyVgoHR1dAT8xj9xRh+iW5D+r11X17x06ygXRiiuBaCAtU47xqYu+2m6PT8KI3/X9SysFMaiBfOvipTFUl0eZTwppA5ak8BZOkBFgo9/6C/uqvx0a0py7dH/+V5FzdFSk96AQKSPRCavCUoVbr29FZC8yUedbzSq6bFJS5rL4fIJX/BNNRowkJM/Iynan95F9ZiOyYdJRdOoq3hJP+mAeXaG0FY7av1/r6oD3seHF5dhj4x9fhtDfZHDnqXUWUUGI2Zcv96LdKQ58G2+FZZ27n10Yyphx+JpFe5phsOHEUv9tquQlByQiQ8fmjt4h/Wzu+VZK3D8YGqIXMLii/mao7Z8HyjPorOxH12/tQb4hlUmuPVUqYvUKDy6LmFn8GVvctgTOTQupDOdE6xA9NrejfJNqdABDhavEeHkbPpljafMX3osuv85EVXt1Fuhs+8DQ21oiCz5Zq1ZnCAMgb0aRLRiSLQ77aEv9HuKdUfdzJ9naCleza6r0FJGsqz+eLy8CdbQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(22082099003)(56012099003)(18002099003)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nqMc7zMwIVOkmJt1vHlGnOVYLo/FlnOzNrhdAkkv33EcWyZ5R+wbAwbi+3Uk/lqgWw7gO9PGy3XJ4jmN7wbcJ0DgbNeW9TYKbNZDNgA4+ukecrLyLPXfLbOLpdkmA88Kcuzgn6Eeyp88Stc9ZJ1ZEe9kOq84/Wb3XepI66nJVkh2eV+GW2FerkiDL5zlBW8vtVIClLFUKfuwHbRiA4jakITHUM2JcA7uO6VC1O0OKfAWoEbjSAhkDBpLwHpyw4z8nPAbz+zlp1GpjmJtNuvYPOjOutyvQsbCk+rSJ/Qofl99YcNSxGEgTL+n/8Zv/T4I/2/j5K5wvCR1JH1uIVpEu7jmd+6oZLIFvy6c/tWW3flkPgLyoyF3kTFs9DMJSxYim5LY3tP2KRfCeFYAEywrOL0t2YpXaIoaZhYzjPYBBnpwQtV2p7YcvWQD9bekIiX8 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:22.9817 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0b00948a-afad-4cbe-08f9-08de8b2d9574 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6977 Content-Type: text/plain; charset="utf-8" The function msr_update_perf() does not cache the new value that is written to MSR_AMD_CPPC_REQ into the variable cpudata->cppc_req_cached when the update is happening from the fast path. Fix that by caching the value everytime the MSR_AMD_CPPC_REQ gets updated. This issue was discovered by Claude Opus 4.6 with the aid of Chris Mason's AI review-prompts (https://github.com/masoncl/review-prompts/tree/main/kernel). Assisted-by: Claude:claude-opus-4.6 review-prompts/linux Reviewed-by: Mario Limonciello (AMD) Fixes: fff395796917 ("cpufreq/amd-pstate: Always write EPP value when updat= ing perf") Signed-off-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d57969c72c9d..24cdeffbcd40 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -261,7 +261,6 @@ static int msr_update_perf(struct cpufreq_policy *polic= y, u8 min_perf, =20 if (fast_switch) { wrmsrq(MSR_AMD_CPPC_REQ, value); - return 0; } else { int ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); =20 --=20 2.34.1 From nobody Thu Apr 2 22:25:45 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012009.outbound.protection.outlook.com [52.101.48.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 532A93F7A8A; Thu, 26 Mar 2026 11:48:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.9 ARC-Seal: i=2; a=rsa-sha256; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Mario Limonciello Subject: [PATCH v4 03/12] amd-pstate: Make certain freq_attrs conditionally visible Date: Thu, 26 Mar 2026 17:17:47 +0530 Message-ID: <20260326114756.20374-4-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|SJ2PR12MB8881:EE_ X-MS-Office365-Filtering-Correlation-Id: 27b7a93b-a3f3-4e67-d3fc-08de8b2d9715 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: 7HYRgCe6lvHAZ2XBjLMELaTNJDMRRZD5dHZGhsmXanG2Sgyu4Wu/ywD0FCBSQDNyslNyM/LtYrVDvvt8ZEgZeWRXPf/bA1m9GP48wg3wJ5LyCcVa7aJwIP38mN/GOG2iKEFSoJUrOPqNpO6P820B22gnr1DfUrMI3Mb1g0yPH+2WTABovW1TTSk53DwYOjudK1F6Y6RnFg11hT6hdYh7oBKGD2Re1HWpiLbou9rfwsnLr6ksMGrLHKLNg58HTu/wsZS7ysp+TOi1rDEzBtyh8PgnnEDoBAR9YvaNYXN/Vfl2nlW3HOyFAxwlQrzrZJkgz/Ie2GNsNJBhI6GJYqvQgEr+2GtKCvNHkGoSYyZOMpPfbWBXN+DDg0+kze79fNEp32DsxNyTQ3c/DCg4WxB+sZ08KICCcT5JJUCywhOKSgzXnXW4QHNrDQUSwC3740G2QJD3csRJgeYqGizrDyWcmHeZKy8P2K5FyB1MbKgrv4IwheFZ9TxqHb56HYemGmv+J51wpkrhLwkjeO0eKEcqYotL9EVd5+2Uap/L6b9tXT8d7jPy2A/VGt3JBVg5/p3glQRig0DRB+BaMb7d+mbMDBK9Qhd6dh3rJfbg5gXZqbEHHrazNNrGaa5PKOkpRtlhamHwQ6dwBFETzKCjiFZPFRxdZSIL3WHXfh99wgIRlOieIlMbe+jLBTXBQO+OBkZC5pQoUzx0aysf1AjTpQ5bv88ZoUKSjtIU/b/RuD9mUX2DBIj81y6uA3cuDmsDc7RmKqRsFXXLAipTwnB/Dg2n/g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hSMFu9TymSQ3OwZFJ2/D7Wk8fmOLZcJmxcMBcOhdHhK2QUIlr5+ixGRFom2EVZfvhMo5eylkA3HoTAdb6NPiQJwz0llZi4HxvxZ7flLG+Py62/ilsdE9nkeSDtpZOa0e4k9hB65uJb22cFa9EjXZlW5LAUW4XCcqqTxBoOgTcPcpFZDOAJ5rvIiehVhapfaLnd71aCJKZH7s3DEeDJTX1JDl0JODNbF9QuNl7tGz745rBjUZzfqcWUyz77dGZqFaEbfcVFjXNeQhrG9q6B6zYknU+VTc3aJFzpQLZFCTpKEX3wTiiimkKBD36L0hNOg9QwdJ+0CMNNs8KfdMvwddY+eI5HMOd+frNVmdOYu564FRgKCw3oGnq2YBvDf79pZqNrrDfFs90Q/t6+yMGREwSKpTxLR7sl8tjq9hQzMDjuHRB8MGQZklEVC8AXtXDZV7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:25.7089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27b7a93b-a3f3-4e67-d3fc-08de8b2d9715 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8881 Content-Type: text/plain; charset="utf-8" Certain amd_pstate freq_attrs such as amd_pstate_hw_prefcore and amd_pstate_prefcore_ranking are enabled even when preferred core is not supported on the platform. Similarly there are common freq_attrs between the amd-pstate and the amd-pstate-epp drivers (eg: amd_pstate_max_freq, amd_pstate_lowest_nonlinear_freq, etc.) but are duplicated in two different freq_attr structs. Unify all the attributes in a single place and associate each of them with a visibility function that determines whether the attribute should be visible based on the underlying platform support and the current amd_pstate mode. Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 124 ++++++++++++++++++++++++++--------- 1 file changed, 93 insertions(+), 31 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 24cdeffbcd40..4de2037a414c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1220,12 +1220,87 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } =20 +cpufreq_freq_attr_ro(amd_pstate_max_freq); +cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); + +cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); +cpufreq_freq_attr_rw(energy_performance_preference); +cpufreq_freq_attr_ro(energy_performance_available_preferences); + +struct freq_attr_visibility { + struct freq_attr *attr; + bool (*visibility_fn)(void); +}; + +/* For attributes which are always visible */ +static bool always_visible(void) +{ + return true; +} + +/* Determines whether prefcore related attributes should be visible */ +static bool prefcore_visibility(void) +{ + return amd_pstate_prefcore; +} + +/* Determines whether energy performance preference should be visible */ +static bool epp_visibility(void) +{ + return cppc_state =3D=3D AMD_PSTATE_ACTIVE; +} + +static struct freq_attr_visibility amd_pstate_attr_visibility[] =3D { + {&amd_pstate_max_freq, always_visible}, + {&amd_pstate_lowest_nonlinear_freq, always_visible}, + {&amd_pstate_highest_perf, always_visible}, + {&amd_pstate_prefcore_ranking, prefcore_visibility}, + {&amd_pstate_hw_prefcore, prefcore_visibility}, + {&energy_performance_preference, epp_visibility}, + {&energy_performance_available_preferences, epp_visibility}, +}; + +static struct freq_attr **get_freq_attrs(void) +{ + bool attr_visible[ARRAY_SIZE(amd_pstate_attr_visibility)]; + struct freq_attr **attrs; + int i, j, count; + + for (i =3D 0, count =3D 0; i < ARRAY_SIZE(amd_pstate_attr_visibility); i+= +) { + struct freq_attr_visibility *v =3D &amd_pstate_attr_visibility[i]; + + attr_visible[i] =3D v->visibility_fn(); + if (attr_visible[i]) + count++; + } + + /* amd_pstate_{max_freq, lowest_nonlinear_freq, highest_perf} should alwa= ys be visible */ + BUG_ON(!count); + + attrs =3D kcalloc(count + 1, sizeof(struct freq_attr *), GFP_KERNEL); + if (!attrs) + return ERR_PTR(-ENOMEM); + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(amd_pstate_attr_visibility); i++) { + if (!attr_visible[i]) + continue; + + attrs[j++] =3D amd_pstate_attr_visibility[i].attr; + } + + return attrs; +} + static void amd_pstate_driver_cleanup(void) { if (amd_pstate_prefcore) sched_clear_itmt_support(); =20 cppc_state =3D AMD_PSTATE_DISABLE; + kfree(current_pstate_driver->attr); + current_pstate_driver->attr =3D NULL; current_pstate_driver =3D NULL; } =20 @@ -1250,6 +1325,7 @@ static int amd_pstate_set_driver(int mode_idx) =20 static int amd_pstate_register_driver(int mode) { + struct freq_attr **attr =3D NULL; int ret; =20 ret =3D amd_pstate_set_driver(mode); @@ -1258,6 +1334,22 @@ static int amd_pstate_register_driver(int mode) =20 cppc_state =3D mode; =20 + /* + * Note: It is important to compute the attrs _after_ + * re-initializing the cppc_state. Some attributes become + * visible only when cppc_state is AMD_PSTATE_ACTIVE. + */ + attr =3D get_freq_attrs(); + if (IS_ERR(attr)) { + ret =3D (int) PTR_ERR(attr); + pr_err("Couldn't compute freq_attrs for current mode %s [%d]\n", + amd_pstate_get_mode_string(cppc_state), ret); + amd_pstate_driver_cleanup(); + return ret; + } + + current_pstate_driver->attr =3D attr; + /* at least one CPU supports CPB */ current_pstate_driver->boost_enabled =3D cpu_feature_enabled(X86_FEATURE_= CPB); =20 @@ -1399,37 +1491,9 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } =20 -cpufreq_freq_attr_ro(amd_pstate_max_freq); -cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); - -cpufreq_freq_attr_ro(amd_pstate_highest_perf); -cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); -cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); -cpufreq_freq_attr_rw(energy_performance_preference); -cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); =20 -static struct freq_attr *amd_pstate_attr[] =3D { - &amd_pstate_max_freq, - &amd_pstate_lowest_nonlinear_freq, - &amd_pstate_highest_perf, - &amd_pstate_prefcore_ranking, - &amd_pstate_hw_prefcore, - NULL, -}; - -static struct freq_attr *amd_pstate_epp_attr[] =3D { - &amd_pstate_max_freq, - &amd_pstate_lowest_nonlinear_freq, - &amd_pstate_highest_perf, - &amd_pstate_prefcore_ranking, - &amd_pstate_hw_prefcore, - &energy_performance_preference, - &energy_performance_available_preferences, - NULL, -}; - static struct attribute *pstate_global_attributes[] =3D { &dev_attr_status.attr, &dev_attr_prefcore.attr, @@ -1696,7 +1760,6 @@ static struct cpufreq_driver amd_pstate_driver =3D { .set_boost =3D amd_pstate_set_boost, .update_limits =3D amd_pstate_update_limits, .name =3D "amd-pstate", - .attr =3D amd_pstate_attr, }; =20 static struct cpufreq_driver amd_pstate_epp_driver =3D { @@ -1712,7 +1775,6 @@ static struct cpufreq_driver amd_pstate_epp_driver = =3D { .update_limits =3D amd_pstate_update_limits, .set_boost =3D amd_pstate_set_boost, .name =3D "amd-pstate-epp", - .attr =3D amd_pstate_epp_attr, }; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , "H. Peter Anvin" , "Borislav Petkov" , Dave Hansen , "Thomas Gleixner" , Ingo Molnar , Subject: [PATCH v4 04/12] x86/cpufeatures: Add AMD CPPC Performance Priority feature. Date: Thu, 26 Mar 2026 17:17:48 +0530 Message-ID: <20260326114756.20374-5-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E0:EE_|DM3PR12MB9436:EE_ X-MS-Office365-Filtering-Correlation-Id: ab437a3f-e219-4ab4-0fb5-08de8b2d994a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700016|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: UbFUYXdQB3Q5TOFFq7fhZlbmaxaLDTap5wfo39+DPlFf5Q98rAo9heIFKbwZIJ35/OTeMrdQy0T6wYKcK1tN/OC4tFGcwW5G0bQnis8GK3kng5OIc6sjGuKXGyy04XUeQVyRbLPinZFqpovT3oirigW4i5pgAGTmztbO3E7InFw2wfahq0BJN97ulb08NiNzbwNQo9n3WGlcChqhJHXRTZ7hkcSFcJnsTWIPNKHa2hOvUIpruUU5fI0cVsX4/so4agsChNnuR5iaK2FQt16EfMjyN/pwLVMKtJlZwvJ8Xve61m8nOwLzyFWBBEanhqOYGVLe4Klgy5NQuuXYTfFl8HXDWUxYIWNODyycksGbIM4+6QkA65DC/2AvWFvE3ZfNIpcdEB6cUQW7rLLa3gx0nmNPcXRqjkbZT3CTFxtk4217/vfiCoTSxCJxhG3i8Cnpn1/yNAidTvcetdVnwljSeiAk8QWTIbH9OuB1v9SMWA6wwL8XKN9HFuzsEFIYOSU7x9jApKYYOcUZWH5sG5k9SmC73OeuYYDEgED6CKJEtI8TpHTbSIA0wDWt8RpbYqV3Ccnaw2JEU8QGka5EwQOJYlej7hDRM6pxPgvs+J93VAWjr7LifD8id9lateYD6YGH+xZYtC3MPvs6zIPT6zTrNbvCxoBKXyKEIcaM3iXSz1LV5b9W0ALZ15t6FwIe+IFEsOSsvk+h35Sr4McWrO/jfKSzZuGKfuQAwpNmBXhmI0vm6x5Mmh0LAhaZshcZo2fv8YNmS9BIpurA8d5ps7xAHA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700016)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5YorAMkpfBQG/sY6lJzjAjoXiHcrAdd8x58tmPUxyjO+YH1SKVehHJceR6STviEEnfpbkhYWZGuHy++USjzVI0CDRmN3McRlm+qEAgCx4nFA4oPFpehAW+OmOyqE1pQhMC8HY/yd4FDkLyMPyvgdAtP6JpnfWttUONtOxrW/yWlWfash6wETN/W13AW0Cd0ATkdNU2BR1wyiYAxLnkDp9W6KZPmuuFLQZKOWCpcJfZhGYl0jUuSODu+TGoCY2mwCaPmDR1jduYvnkJr77iWe0J/XQpgQ6kRWOQHpuMuqGz85akm/fYbDwf8ZqFVjUi/kU1tHfzfgDtSwfOhZrMAAc96kwsFwLNg5AF5+O2k6FIdjfJLX30E6cqRoPWgvO8xvt6BwCYA+TIR5Jub4XRcPKIqOmfCiPj2nO6dt46SsGMnKZDLfhlzgdaF3Ly054ZrE X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:29.3997 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab437a3f-e219-4ab4-0fb5-08de8b2d994a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9436 Content-Type: text/plain; charset="utf-8" Some future AMD processors have feature named "CPPC Performance Priority" which lets userspace specify different floor performance levels for different CPUs. The platform firmware takes these different floor performance levels into consideration while throttling the CPUs under power/thermal constraints. The presence of this feature is indicated by bit 16 of the EDX register for CPUID leaf 0x80000007. More details can be found in AMD Publication titled "AMD64 Collaborative Processor Performance Control (CPPC) Performance Priority" Revision 1.10. Define a new feature bit named X86_FEATURE_CPPC_PERF_PRIO to map to CPUID 0x80000007.EDX[16]. Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Gautham R. Shenoy --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dbe104df339b..86d17b195e79 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -415,7 +415,7 @@ */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA over= flow recovery support */ #define X86_FEATURE_SUCCOR (17*32+ 1) /* "succor" Uncorrectable error con= tainment and recovery */ - +#define X86_FEATURE_CPPC_PERF_PRIO (17*32+ 2) /* CPPC Floor Perf support */ #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 42c7eac0c387..837d6a4b0c28 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -52,6 +52,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, + { X86_FEATURE_CPPC_PERF_PRIO, CPUID_EDX, 16, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_X2AVIC_EXT, CPUID_ECX, 6, 0x8000000a, 0 }, { X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 }, diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index dbe104df339b..86d17b195e79 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -415,7 +415,7 @@ */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA over= flow recovery support */ #define X86_FEATURE_SUCCOR (17*32+ 1) /* "succor" Uncorrectable error con= tainment and recovery */ - +#define X86_FEATURE_CPPC_PERF_PRIO (17*32+ 2) /* CPPC Floor Perf support */ #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ --=20 2.34.1 From nobody Thu Apr 2 22:25:45 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011035.outbound.protection.outlook.com [52.101.62.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 651E53F210F; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Mario Limonciello Subject: [PATCH v4 05/12] amd-pstate: Add support for CPPC_REQ2 and FLOOR_PERF Date: Thu, 26 Mar 2026 17:17:49 +0530 Message-ID: <20260326114756.20374-6-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|LV8PR12MB9408:EE_ X-MS-Office365-Filtering-Correlation-Id: 208b4ac1-873c-4f72-e20b-08de8b2d9ada X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|13003099007|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 9uSX6yYCzyPlLiI2r2Kfs5+l3TP2bS97SYHtstM2rCBReTJD9L3ZhZIU0durEgBZ8MuDcWjmOwsCvdXwrFkmZLKKO2L3PVClSY0mjViMgiNRD/H6yimHBXfcMUD2PDzAgtTcbvuI0ieh5IY5PyJ8vDC0SdCVZdq1t8z391MxM40QY0bDIfuDArPpj6Mcmc2ywH4GPbq6Cq+24X1N0bIKxSTibSkS8TpQzUl94XIRYOobR2PkyU9ooyZCrtd+okTgCNoFsl7hIkCmvnr2uIqeQjLuVIejpVDmcvmcJa/jt8o/dHEE6Nq735o93MK0/iNB0+YVTA3EwSZ5n0y13RcvgmFjwRZgYMkkh2mg5pOL8Eu/4nLDci7X5rcr/omCvSAlIDky35FNwTfdICwfOvGaFxiZLGnEywp1hhZMSTQonIQuzrzICKoBJIHGzHSznjIcT1POf7YhmiwLjNGt2DpeGguDnHWY6hT+1PYQVlPvsZfTnQzyl6Hqz59puastFA9INib+Qsi46+BmWypDnuGbcGcTPr+QMIg3r2naXWcmc6YV0gx/Wzrts0/hFpruBhRsBLwAV5DnFmjTwY4wz++/9JYKqN8DpCfFzzplsYW97hQhVrXLcL0ZnHnPgbBNMUIsGKNq7sGBo0eUZY5UiklNPsZQVNDUrnxb3CU5tSKgI7SXo3l0C0QWPKLuhy4KzXM/ApFm2JcxRe4dAIOWkPHCyizWy8itMf/3Rbz2nK9e0G3p6ZUMIKAVBuwcf3DeB1gq2IZEIk7jWw6/tT6CNtTVKg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(13003099007)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7i9TTs/Px8aKSv/htY6qPS0uiraVmifdYvVnL3+11KcIYPGwNcy0D3xnSvdUrl2y+p0toRFvVROqraopVEc/jpRTI+fTjOpajHzPGw+aX/8VtpZv2UgD5ziyzQBHxR5SZZsyW3b+u5wEIzT6zZrJ8jLzw1EG8YcU7wgY0yYYG8gpFfIR8sHCYKtDRNR1aOo2+UOYbpcANdHplM7O1lKzC56rNnsdEhpM5v+62/auNXJLQk1mu5UpelRCgZdxg8yLN+wjk0cSGqg+2tsj2OK0ZAg+DtuVIRLWkAsK23yWU0C8MioEKjNpwSu2EdG5S7dcchR6R40es28uilinvaetCLtkNfCG0F0cJa95k+PnFPatT3KCeVkUiUQ7i0J3QluPO0ZXPtHehW1uhD/CULK7QrSTTs5GmocFth1lgk0A8JbHGSVvBWxLtKStbiDyZN+W X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:32.0262 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 208b4ac1-873c-4f72-e20b-08de8b2d9ada X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9408 Content-Type: text/plain; charset="utf-8" Some future AMD processors have feature named "CPPC Performance Priority" which lets userspace specify different floor performance levels for different CPUs. The platform firmware takes these different floor performance levels into consideration while throttling the CPUs under power/thermal constraints. The presence of this feature is indicated by bit 16 of the EDX register for CPUID leaf 0x80000007. More details can be found in AMD Publication titled "AMD64 Collaborative Processor Performance Control (CPPC) Performance Priority" Revision 1.10. The number of distinct floor performance levels supported on the platform will be advertised through the bits 32:39 of the MSR_AMD_CPPC_CAP1. Bits 0:7 of a new MSR MSR_AMD_CPPC_REQ2 (0xc00102b5) will be used to specify the desired floor performance level for that CPU. Add support for the aforementioned MSR_AMD_CPPC_REQ2, and macros for parsing and updating the relevant bits from MSR_AMD_CPPC_CAP1 and MSR_AMD_CPPC_REQ2. On boot if the default value of the MSR_AMD_CPPC_REQ2[7:0] (Floor Perf) is lower than CPPC.lowest_perf, and thus invalid, initialize it to MSR_AMD_CPPC_CAP1.nominal_perf which is a sane default value. Save the boot-time floor_perf during amd_pstate_init_floor_perf(). In a subsequent patch it will be restored in the suspend, offline, and exit paths, mirroring how bios_min_perf is handled for MSR_AMD_CPPC_REQ. Link: https://docs.amd.com/v/u/en-US/69206_1.10_AMD64_CPPC_PUB Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- arch/x86/include/asm/msr-index.h | 5 ++ drivers/cpufreq/amd-pstate.c | 78 +++++++++++++++++++++++++++++++- drivers/cpufreq/amd-pstate.h | 8 ++++ 3 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 6673601246b3..e126c7fb69cf 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -765,12 +765,14 @@ #define MSR_AMD_CPPC_CAP2 0xc00102b2 #define MSR_AMD_CPPC_REQ 0xc00102b3 #define MSR_AMD_CPPC_STATUS 0xc00102b4 +#define MSR_AMD_CPPC_REQ2 0xc00102b5 =20 /* Masks for use with MSR_AMD_CPPC_CAP1 */ #define AMD_CPPC_LOWEST_PERF_MASK GENMASK(7, 0) #define AMD_CPPC_LOWNONLIN_PERF_MASK GENMASK(15, 8) #define AMD_CPPC_NOMINAL_PERF_MASK GENMASK(23, 16) #define AMD_CPPC_HIGHEST_PERF_MASK GENMASK(31, 24) +#define AMD_CPPC_FLOOR_PERF_CNT_MASK GENMASK_ULL(39, 32) =20 /* Masks for use with MSR_AMD_CPPC_REQ */ #define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) @@ -778,6 +780,9 @@ #define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) #define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) =20 +/* Masks for use with MSR_AMD_CPPC_REQ2 */ +#define AMD_CPPC_FLOOR_PERF_MASK GENMASK(7, 0) + /* AMD Performance Counter Global Status and Control MSRs */ #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 4de2037a414c..53b8173ff183 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -329,6 +329,65 @@ static inline int amd_pstate_set_epp(struct cpufreq_po= licy *policy, u8 epp) return static_call(amd_pstate_set_epp)(policy, epp); } =20 +static int amd_pstate_set_floor_perf(struct cpufreq_policy *policy, u8 per= f) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u64 value, prev; + int ret; + + if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) + return 0; + + value =3D prev =3D READ_ONCE(cpudata->cppc_req2_cached); + FIELD_MODIFY(AMD_CPPC_FLOOR_PERF_MASK, &value, perf); + + if (value =3D=3D prev) + return 0; + + ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value); + if (ret) { + pr_err("failed to set CPPC REQ2 value. Error (%d)\n", ret); + return ret; + } + + WRITE_ONCE(cpudata->cppc_req2_cached, value); + + return ret; +} + +static int amd_pstate_init_floor_perf(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u8 floor_perf; + u64 value; + int ret; + + if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) + return 0; + + ret =3D rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, &value); + if (ret) { + pr_err("failed to read CPPC REQ2 value. Error (%d)\n", ret); + return ret; + } + + WRITE_ONCE(cpudata->cppc_req2_cached, value); + floor_perf =3D FIELD_GET(AMD_CPPC_FLOOR_PERF_MASK, + cpudata->cppc_req2_cached); + + /* Set a sane value for floor_perf if the default value is invalid */ + if (floor_perf < cpudata->perf.lowest_perf) { + floor_perf =3D cpudata->perf.nominal_perf; + ret =3D amd_pstate_set_floor_perf(policy, floor_perf); + if (ret) + return ret; + } + + cpudata->bios_floor_perf =3D floor_perf; + + return 0; +} + static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) { struct amd_cpudata *cpudata =3D policy->driver_data; @@ -426,6 +485,7 @@ static int msr_init_perf(struct amd_cpudata *cpudata) perf.lowest_perf =3D FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); WRITE_ONCE(cpudata->perf, perf); WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MAS= K, cap1)); + WRITE_ONCE(cpudata->floor_perf_cnt, FIELD_GET(AMD_CPPC_FLOOR_PERF_CNT_MAS= K, cap1)); =20 return 0; } @@ -1024,6 +1084,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy = *policy) cpudata->nominal_freq, perf.highest_perf); =20 + policy->driver_data =3D cpudata; ret =3D amd_pstate_cppc_enable(policy); if (ret) goto free_cpudata1; @@ -1036,6 +1097,12 @@ static int amd_pstate_cpu_init(struct cpufreq_policy= *policy) if (cpu_feature_enabled(X86_FEATURE_CPPC)) policy->fast_switch_possible =3D true; =20 + ret =3D amd_pstate_init_floor_perf(policy); + if (ret) { + dev_err(dev, "Failed to initialize Floor Perf (%d)\n", ret); + goto free_cpudata1; + } + ret =3D freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, FREQ_QOS_MIN_DEFAULT_VALUE); if (ret < 0) { @@ -1050,7 +1117,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy = *policy) goto free_cpudata2; } =20 - policy->driver_data =3D cpudata; =20 if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf =3D amd_pstate_adjust_perf; @@ -1062,6 +1128,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy = *policy) free_cpudata1: pr_warn("Failed to initialize CPU %d: %d\n", policy->cpu, ret); kfree(cpudata); + policy->driver_data =3D NULL; return ret; } =20 @@ -1072,6 +1139,7 @@ static void amd_pstate_cpu_exit(struct cpufreq_policy= *policy) =20 /* Reset CPPC_REQ MSR to the BIOS value */ amd_pstate_update_perf(policy, perf.bios_min_perf, 0U, 0U, 0U, false); + amd_pstate_set_floor_perf(policy, cpudata->bios_floor_perf); =20 freq_qos_remove_request(&cpudata->req[1]); freq_qos_remove_request(&cpudata->req[0]); @@ -1598,6 +1666,12 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_po= licy *policy) if (ret) goto free_cpudata1; =20 + ret =3D amd_pstate_init_floor_perf(policy); + if (ret) { + dev_err(dev, "Failed to initialize Floor Perf (%d)\n", ret); + goto free_cpudata1; + } + current_pstate_driver->adjust_perf =3D NULL; =20 return 0; @@ -1605,6 +1679,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) free_cpudata1: pr_warn("Failed to initialize CPU %d: %d\n", policy->cpu, ret); kfree(cpudata); + policy->driver_data =3D NULL; return ret; } =20 @@ -1617,6 +1692,7 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_po= licy *policy) =20 /* Reset CPPC_REQ MSR to the BIOS value */ amd_pstate_update_perf(policy, perf.bios_min_perf, 0U, 0U, 0U, false); + amd_pstate_set_floor_perf(policy, cpudata->bios_floor_perf); =20 kfree(cpudata); policy->driver_data =3D NULL; diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index cb45fdca27a6..303da70b0afa 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -62,9 +62,14 @@ struct amd_aperf_mperf { * @cpu: CPU number * @req: constraint request to apply * @cppc_req_cached: cached performance request hints + * @cppc_req2_cached: cached value of MSR_AMD_CPPC_REQ2 * @perf: cached performance-related data * @prefcore_ranking: the preferred core ranking, the higher value indicat= es a higher * priority. + * @floor_perf_cnt: Cached value of the number of distinct floor + * performance levels supported + * @bios_floor_perf: Cached value of the boot-time floor performance level= from + * MSR_AMD_CPPC_REQ2 * @min_limit_freq: Cached value of policy->min (in khz) * @max_limit_freq: Cached value of policy->max (in khz) * @nominal_freq: the frequency (in khz) that mapped to nominal_perf @@ -87,10 +92,13 @@ struct amd_cpudata { =20 struct freq_qos_request req[2]; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Mario Limonciello Subject: [PATCH v4 06/12] amd-pstate: Add sysfs support for floor_freq and floor_count Date: Thu, 26 Mar 2026 17:17:50 +0530 Message-ID: <20260326114756.20374-7-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DE:EE_|BY5PR12MB4180:EE_ X-MS-Office365-Filtering-Correlation-Id: 85c97cb4-7494-4ff1-82db-08de8b2d9c71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: w/VkZsPDY8i9h7cmyoR/7vRE4GtlsEM0rhmJ6HR0E34h6rRj21GjW1oJfN92n9QTnvcsH+W1Hd236QKyq6kE8k6qdBnUPfekfxrweWobCGa7i70465caU+PrlKVMPyC/j5JNyTbYfkif5zylEPLWifxuEyTl5U0fvOSuYJ4ZZ5MYboWFQkDj2sFZXsSoRbEKo/WYKSd+SGC40vi1XKFdGQ9/RTAdn95gSuOu1IKdRlb2U+7RJUl2qZTDTECRji4P+NZXCQWsnnJ7G5Q9Mx/x6vVxJsM3Lx97Rzjp8UV8944ILOUgiUJ1p/MxKLhpSNIqdtUSUzUytnJWBt/6FKVWw3XWuG3qF9i8SF1E1kR8z5Bu+szbtHE+LklUQTp1gvYMQD12cxwgFVWNsv37jFw6Dmx755ifuhyeIvhvIeEM6plStqEfDU8qhV6rpvQ2bOwOdgidYUbclrjbSV0tDcfFVnImlO6rr0GXnxshZxEXTMyfSv7BC3Tx2q1iIxZ35qJyQizO9uYDjX08ukHOX2NCdQIg8mpYmsQqvYc1+SQ83Q1MB+RqLj4SHwIOFkH+5Y1PcVFrI+NES5mZAek1bRm3O8uuiF1DrpyiKJrbsoTQ5cE6FfLUvIlcnYHNZ1l+VCY8gcPxOXp/an5kpSY10IXyHlTweXxWuD56N3fr0H/IEg+CpeOFxWGJA5YcC+kD9Z6hA8zOo0Z0218J+vyvmD43xysYPApeu8LEIGUXueDLyK0kaUFmCljg/oTyVhm5YJvNg7+loky1ICko71D+D9u/lw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sqEMZrVlg8UY7htRTi1INSNM8xmC6qlz9k1s8ZR6CHLzRVLo37KDMTxfAUQHJzqrD6edrla/1vOhDJiRbxW8gdl+lB06K1OtzV/rl6ECVx24HTlzmC0YRv6PbV2TBEyvnZP0NdI14IPWNGpCYoH5OeOjGX7YAcd6HA+uzHaJrrz7GRFtWgWOUMrfo8ksIC7SOQG3Ud77ITvpyDjYVhtmIIR8IqCUV8QDGHI3GfvZOf9nK+eJf+O1ydOYvZRT4vsMctZoVg0vUSBHyJmOKfMhLHrCzlndnmrj+UDJ9JmGXnOAnOpEIYzt2moLVnMHIR3QQZnfsGfkyG9ka45tDF+HssHMz//OFaQV+mc0LESVEQG1nolMHmsg+kOXYQMamYIVUJcGuS0s5UmTomiQLkaYm3AYW4fxuyMaDQIKDpiyEuMM1UEyAze6Spv5pCDsfeju X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:34.6865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85c97cb4-7494-4ff1-82db-08de8b2d9c71 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4180 Content-Type: text/plain; charset="utf-8" When Floor Performance feature is supported by the platform, expose two sysfs files: * amd_pstate_floor_freq to allow userspace to request the floor frequency for each CPU. * amd_pstate_floor_count which advertises the number of distinct levels of floor frequencies supported on this platform. Reset the floor_perf to bios_floor_perf in the suspend, offline, and exit paths, and restore the value to the cached user-request floor_freq on the resume and online paths mirroring how bios_min_perf is handled for MSR_AMD_CPPC_REQ. Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 93 +++++++++++++++++++++++++++++++++--- drivers/cpufreq/amd-pstate.h | 2 + 2 files changed, 89 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 53b8173ff183..a068c4457a8f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -383,8 +383,10 @@ static int amd_pstate_init_floor_perf(struct cpufreq_p= olicy *policy) return ret; } =20 - cpudata->bios_floor_perf =3D floor_perf; =20 + cpudata->bios_floor_perf =3D floor_perf; + cpudata->floor_freq =3D perf_to_freq(cpudata->perf, cpudata->nominal_freq, + floor_perf); return 0; } =20 @@ -1288,6 +1290,46 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } =20 +static ssize_t store_amd_pstate_floor_freq(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + unsigned int freq; + u8 floor_perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq); + if (ret) + return ret; + + if (freq < policy->cpuinfo.min_freq || freq > policy->max) + return -EINVAL; + + floor_perf =3D freq_to_perf(perf, cpudata->nominal_freq, freq); + ret =3D amd_pstate_set_floor_perf(policy, floor_perf); + + if (!ret) + cpudata->floor_freq =3D freq; + + return ret ?: count; +} + +static ssize_t show_amd_pstate_floor_freq(struct cpufreq_policy *policy, c= har *buf) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + + return sysfs_emit(buf, "%u\n", cpudata->floor_freq); +} + +static ssize_t show_amd_pstate_floor_count(struct cpufreq_policy *policy, = char *buf) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u8 count =3D cpudata->floor_perf_cnt; + + return sysfs_emit(buf, "%u\n", count); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); =20 @@ -1296,6 +1338,8 @@ cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +cpufreq_freq_attr_rw(amd_pstate_floor_freq); +cpufreq_freq_attr_ro(amd_pstate_floor_count); =20 struct freq_attr_visibility { struct freq_attr *attr; @@ -1320,6 +1364,12 @@ static bool epp_visibility(void) return cppc_state =3D=3D AMD_PSTATE_ACTIVE; } =20 +/* Determines whether amd_pstate_floor_freq related attributes should be v= isible */ +static bool floor_freq_visibility(void) +{ + return cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO); +} + static struct freq_attr_visibility amd_pstate_attr_visibility[] =3D { {&amd_pstate_max_freq, always_visible}, {&amd_pstate_lowest_nonlinear_freq, always_visible}, @@ -1328,6 +1378,8 @@ static struct freq_attr_visibility amd_pstate_attr_vi= sibility[] =3D { {&amd_pstate_hw_prefcore, prefcore_visibility}, {&energy_performance_preference, epp_visibility}, {&energy_performance_available_preferences, epp_visibility}, + {&amd_pstate_floor_freq, floor_freq_visibility}, + {&amd_pstate_floor_count, floor_freq_visibility}, }; =20 static struct freq_attr **get_freq_attrs(void) @@ -1748,24 +1800,39 @@ static int amd_pstate_epp_set_policy(struct cpufreq= _policy *policy) =20 static int amd_pstate_cpu_online(struct cpufreq_policy *policy) { - return amd_pstate_cppc_enable(policy); + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + u8 cached_floor_perf; + int ret; + + ret =3D amd_pstate_cppc_enable(policy); + if (ret) + return ret; + + cached_floor_perf =3D freq_to_perf(perf, cpudata->nominal_freq, cpudata->= floor_freq); + return amd_pstate_set_floor_perf(policy, cached_floor_perf); } =20 static int amd_pstate_cpu_offline(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; union perf_cached perf =3D READ_ONCE(cpudata->perf); + int ret; =20 /* * Reset CPPC_REQ MSR to the BIOS value, this will allow us to retain the= BIOS specified * min_perf value across kexec reboots. If this CPU is just onlined norma= lly after this, the * limits, epp and desired perf will get reset to the cached values in cp= udata struct */ - return amd_pstate_update_perf(policy, perf.bios_min_perf, + ret =3D amd_pstate_update_perf(policy, perf.bios_min_perf, FIELD_GET(AMD_CPPC_DES_PERF_MASK, cpudata->cppc_req_cached), FIELD_GET(AMD_CPPC_MAX_PERF_MASK, cpudata->cppc_req_cached), FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached), false); + if (ret) + return ret; + + return amd_pstate_set_floor_perf(policy, cpudata->bios_floor_perf); } =20 static int amd_pstate_suspend(struct cpufreq_policy *policy) @@ -1787,6 +1854,10 @@ static int amd_pstate_suspend(struct cpufreq_policy = *policy) if (ret) return ret; =20 + ret =3D amd_pstate_set_floor_perf(policy, cpudata->bios_floor_perf); + if (ret) + return ret; + /* set this flag to avoid setting core offline*/ cpudata->suspended =3D true; =20 @@ -1798,15 +1869,24 @@ static int amd_pstate_resume(struct cpufreq_policy = *policy) struct amd_cpudata *cpudata =3D policy->driver_data; union perf_cached perf =3D READ_ONCE(cpudata->perf); int cur_perf =3D freq_to_perf(perf, cpudata->nominal_freq, policy->cur); + u8 cached_floor_perf; + int ret; =20 /* Set CPPC_REQ to last sane value until the governor updates it */ - return amd_pstate_update_perf(policy, perf.min_limit_perf, cur_perf, perf= .max_limit_perf, - 0U, false); + ret =3D amd_pstate_update_perf(policy, perf.min_limit_perf, cur_perf, per= f.max_limit_perf, + 0U, false); + if (ret) + return ret; + + cached_floor_perf =3D freq_to_perf(perf, cpudata->nominal_freq, cpudata->= floor_freq); + return amd_pstate_set_floor_perf(policy, cached_floor_perf); } =20 static int amd_pstate_epp_resume(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + u8 cached_floor_perf; =20 if (cpudata->suspended) { int ret; @@ -1819,7 +1899,8 @@ static int amd_pstate_epp_resume(struct cpufreq_polic= y *policy) cpudata->suspended =3D false; } =20 - return 0; + cached_floor_perf =3D freq_to_perf(perf, cpudata->nominal_freq, cpudata->= floor_freq); + return amd_pstate_set_floor_perf(policy, cached_floor_perf); } =20 static struct cpufreq_driver amd_pstate_driver =3D { diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index 303da70b0afa..453adfb445f8 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -74,6 +74,7 @@ struct amd_aperf_mperf { * @max_limit_freq: Cached value of policy->max (in khz) * @nominal_freq: the frequency (in khz) that mapped to nominal_perf * @lowest_nonlinear_freq: the frequency (in khz) that mapped to lowest_no= nlinear_perf + * @floor_freq: Cached value of the user requested floor_freq * @cur: Difference of Aperf/Mperf/tsc count between last and current samp= le * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value (in khz) @@ -103,6 +104,7 @@ struct amd_cpudata { u32 max_limit_freq; u32 nominal_freq; u32 lowest_nonlinear_freq; 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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by DS3PEPF000099DF.mail.protection.outlook.com (10.167.17.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.21 via Frontend Transport; Thu, 26 Mar 2026 11:48:37 +0000 Received: from BLRRASHENOY1.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 26 Mar 2026 06:48:34 -0500 From: "Gautham R. Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH v4 07/12] amd-pstate: Introduce a tracepoint trace_amd_pstate_cppc_req2() Date: Thu, 26 Mar 2026 17:17:51 +0530 Message-ID: <20260326114756.20374-8-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|SN7PR12MB6863:EE_ X-MS-Office365-Filtering-Correlation-Id: da75086e-d67d-4814-6379-08de8b2d9ddb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: qVf5imGnqyxZ/2KeTr2LaX/xevW8oiEdG5nOngbikMuRH2AKAjGJsAcQc8Lo8T4eaVXaSGK0CM0neTxHS7pVqw8NFwM5JrPqex2fL8gNPGZ8yeIcBHGVyvRDiVio+fYUYlbaCM5N6QubyM1Mxql+7HO49fEF80rlcHhHCcRVpTnuLSRhryvL1akG5LxNdZQZxMGaHLxBr81GeFRRq8zrREh2HB6+gHP23hUoI9aDfpnYuOrJ4Oz91p4sr+Yg54uxx2exl1pV82MdZaFLKPNma05gt5vgOZffwbNGVxUUDkbr7Cp1mLeiAU1TkxGQ4k0qJejr97zH2keDxKn8GvYZ5vjBHmW91G6cE9halV/Cqbg+o67yFO4qx0Ie9Cp3v34j3wMXfJg+OOUckaZyPkD0a5Ujejv7IBN9V+8GR/UvX+G4nOJEdQCuL5hb6gsU/be0lrQV+bo4G1irxVqmwF4WSWA74msM5jp/hF/zuVkE5eRMVQRi/sxzEWc8zq/cBNe8NwCA2W2rL6tWFIUxsTMVgkF4i7sHoDjEGRQIBy1itp/ymha7sDwWIrThqX4ADHyKiK90PYB9uo459WVc1oA0zZOXdfrrWUS2tJ+y7qKNUJVGHeefWUt2Fl9vyb05onAo/ywEAPQ0+ydOcadUdmdepfPDN3YPd6X3TbNCdP6bH2aVfakK2SIwhkYCezPdskK7+rUTmNH9ugfX5U+Ztla5JGgHAP/u8IdIGIU4mRDwHMlYCRhSzXXxDVGPG0cQQwbxJczCVOzqZs9aMKMpEp2Emg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JxVGkARcySNxeuAtMBYWc4EtdEyIkpzcgoD6wG7JdkY+h8SI6XNIiJ6yZVT9rCubUtVThzbTVxF5yVIyPC9qVV5V7NcdArGN+Di9kAofU56VhNRfiYAQeKSgdqYyad6hXcECk/Y+d0Ca2N9uL78gDah2xBCcr7eMoxjd/rBYU3sh+SFcC0i8yNSM8tI2a6a0Un/PElI+ymZdL1LanRce64wEJfKC97Ae4EKh8AXf1xk7OCR9MHJKg86wLyDWcoraS97X6L6AbwB/wuA/DicJYifq13e6IsQTXmLCY+SLbQSrWdcUk7lf4BPly4I3tyguclfvunHDvBlcvH2ncl3Vv2sI8tFOHqtLrHR9NNdX49KMaWtjR6Vj/RBByOYqBUwjO0yssxO2nNpGIR/BI8EzGB61zCQjTfGIdMwWxs4kyUqJFsbEAnjACgWZJRFyuz0T X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:37.0582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da75086e-d67d-4814-6379-08de8b2d9ddb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6863 Content-Type: text/plain; charset="utf-8" Introduce a new tracepoint trace_amd_pstate_cppc_req2() to track updates to MSR_AMD_CPPC_REQ2. Invoke this while changing the Floor Perf. Reviewed-by: Mario Limonciello Signed-off-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate-trace.h | 35 ++++++++++++++++++++++++++++++ drivers/cpufreq/amd-pstate.c | 14 +++++++++--- 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstat= e-trace.h index 32e1bdc588c5..91fa073b2be4 100644 --- a/drivers/cpufreq/amd-pstate-trace.h +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -133,6 +133,41 @@ TRACE_EVENT(amd_pstate_epp_perf, ) ); =20 +TRACE_EVENT(amd_pstate_cppc_req2, + + TP_PROTO(unsigned int cpu_id, + u8 floor_perf, + bool changed, + int err_code + ), + + TP_ARGS(cpu_id, + floor_perf, + changed, + err_code), + + TP_STRUCT__entry( + __field(unsigned int, cpu_id) + __field(u8, floor_perf) + __field(bool, changed) + __field(int, err_code) + ), + + TP_fast_assign( + __entry->cpu_id =3D cpu_id; + __entry->floor_perf =3D floor_perf; + __entry->changed =3D changed; + __entry->err_code =3D err_code; + ), + + TP_printk("cpu%u: floor_perf=3D%u, changed=3D%u (error =3D %d)", + __entry->cpu_id, + __entry->floor_perf, + __entry->changed, + __entry->err_code + ) +); + #endif /* _AMD_PSTATE_TRACE_H */ =20 /* This part must be outside protection */ diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index a068c4457a8f..5eae74a67aeb 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -333,6 +333,7 @@ static int amd_pstate_set_floor_perf(struct cpufreq_pol= icy *policy, u8 perf) { struct amd_cpudata *cpudata =3D policy->driver_data; u64 value, prev; + bool changed; int ret; =20 if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) @@ -341,17 +342,24 @@ static int amd_pstate_set_floor_perf(struct cpufreq_p= olicy *policy, u8 perf) value =3D prev =3D READ_ONCE(cpudata->cppc_req2_cached); FIELD_MODIFY(AMD_CPPC_FLOOR_PERF_MASK, &value, perf); =20 - if (value =3D=3D prev) - return 0; + changed =3D value !=3D prev; + if (!changed) { + ret =3D 0; + goto out_trace; + } =20 ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value); if (ret) { + changed =3D false; pr_err("failed to set CPPC REQ2 value. Error (%d)\n", ret); - return ret; + goto out_trace; } =20 WRITE_ONCE(cpudata->cppc_req2_cached, value); =20 +out_trace: + if (trace_amd_pstate_cppc_req2_enabled()) + trace_amd_pstate_cppc_req2(cpudata->cpu, perf, changed, ret); return ret; } =20 --=20 2.34.1 From nobody Thu Apr 2 22:25:45 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013071.outbound.protection.outlook.com [40.107.201.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 970563F7A9D; Thu, 26 Mar 2026 11:48:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.71 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774525730; cv=fail; b=Bo+EHSUr/rEHzSJOBXsx56yoWj18LCdzC9UtiCfyHZFxemceOofw9x7wiKMbgvuZ1Zt9mzmkcAoMtCXaAq0ik8i7WOfiNVEOsSRTyXt/nYPoEWUKR1SCLsKp0ibfqqVzLm2eXF6ruEAjDqixsKPb0WRVhBudiHh6Kr/QpmadDJo= ARC-Message-Signature: i=2; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH v4 08/12] amd-pstate-ut: Add module parameter to select testcases Date: Thu, 26 Mar 2026 17:17:52 +0530 Message-ID: <20260326114756.20374-9-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|CH1PPF6D0742E7B:EE_ X-MS-Office365-Filtering-Correlation-Id: bf2657e7-bb84-4c10-c83f-08de8b2d9f4f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|82310400026|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: uopywrABx47LpRP8tSLEL3SpC29ncU4rJcdCtpdSTopCW1w5YGonaMH/SfOcGXp2NChPIZDrj0/xKWLwA7Dt9X9w5/SadwuMmQB6wY1QYzHjsQhTl9NKHJKbl3rRdlDKsKhVypvkZyQLvQFpW/SLjuNAO35ougwIwD4XmJXwcOZwH+m+PxgKC2DeoTQZOf+ZLIM5MI9qKg2EZwhZk7YFGszbFqb1Ll2r7HTiMNmQcP/NUL4VdtBb9t39YP0lwBDCWjRBYYSc2Is19PAPTWSqhO6oD2mHtcnqGf3nRWcTEphZSXI4oRrQvrpH+8KipB7qikgfiOiyZxFc+GmYG+64i/GGhKnHglgf+WTxldVsrOUM5IldEG37gT/pUMQtGLpuyjvNmUmAmoe1tDqFreA2Q7sRiUSxPIf3abNV2CRcAW/IC+a8AMyKzVgfEIBVL1IbDlcQc9ADzDlntUAwe9I1kwFeoibGQcSTSfzOEmsP3CZhxNTMyJhnSAmrDWkb6YjLBWFybhDgdI+sbwTjhEX4TEzlUeQMKpsSh0L+uLQ+MFbQhJr/ZXwpbdOKmBQGP4MCDc5+0VmcU2dLNgt3O0E+UALW82UiJ49rsy3CJyA+XRwVxUELtImtQZgv8war0HimDqde11kZnwxmwwzH6zqH0mtL4AGkSEX8NuanVDswpTTfyJPlftpDH/bIyhYlbKDyBIr/WUY7MQNqnVxqyXDNufIm8dpKTcQJC3QRSRqLK9oey3hWuXU0b9KOHCdWqw1BuudEtQ8o32yVSucEXWcIgw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(82310400026)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hyVh03tmZfPD+96UrfUNUgZ23fM1+qVfRFlAGHiobO3G9b0lGcjOrjBAdZFScVNUCj6taLzWpK6dQmcPADb65OrVvFKC+lyGDLQXSZomEzk8Nn4CcIWWD9w3mUMaz6r3N0MaGMMBHUbnk31uKUhDqQB55qvsN2ddHkuhHsflq8eHDpabCJ3InjEWd/dm/z2ZMjx+EXGsN55H4lHPufzWNJ3OiiHSLTs0HVI62yh8imBEnimVYqq1kY1hd7bLeJTkTki5Q4EYP2yGuveaCI0ozg+20pSQbn/VdlSFJXORfrCaSNcO1fC1nzCuoZhvlb2korRq4DKdhOJZJDt3YpsqoeVqkthtBvWNX1+FG92t8zv+dXR4qxX+C523hXZ7sjBlbhz6EohvxfOn5sKqpiOcQJtQtKQK2P6S+zX88y8lQNIq0WGn6QNL81DqVwNoMkCH X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:39.4980 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf2657e7-bb84-4c10-c83f-08de8b2d9f4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF6D0742E7B Content-Type: text/plain; charset="utf-8" Currently when amd-pstate-ut test module is loaded, it runs all the tests from amd_pstate_ut_cases[] array. Add a module parameter named "test_list" that accepts a comma-delimited list of test names, allowing users to run a selected subset of tests. When the parameter is omitted or empty, all tests are run as before. Signed-off-by: Gautham R. Shenoy Reviewed-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate-ut.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-u= t.c index 447b9aa5ce40..3dcdf56883a6 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -35,6 +35,10 @@ =20 #include "amd-pstate.h" =20 +static char *test_list; +module_param(test_list, charp, 0444); +MODULE_PARM_DESC(test_list, + "Comma-delimited list of tests to run (empty means run all tests)"); =20 struct amd_pstate_ut_struct { const char *name; @@ -58,6 +62,25 @@ static struct amd_pstate_ut_struct amd_pstate_ut_cases[]= =3D { {"amd_pstate_ut_check_driver", amd_pstate_ut_check_driver } }; =20 +static bool test_in_list(const char *list, const char *name) +{ + size_t name_len =3D strlen(name); + const char *p =3D list; + + while (*p) { + const char *sep =3D strchr(p, ','); + size_t token_len =3D sep ? sep - p : strlen(p); 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Thu, 26 Mar 2026 06:48:39 -0500 From: "Gautham R. Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH v4 09/12] amd-pstate-ut: Add a testcase to validate the visibility of driver attributes Date: Thu, 26 Mar 2026 17:17:53 +0530 Message-ID: <20260326114756.20374-10-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|BL4PR12MB9481:EE_ X-MS-Office365-Filtering-Correlation-Id: 2be0d0b2-c303-4a31-442c-08de8b2da0bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 3suCZbPXKL6mKZMcN5OVztRVLGvtrQLBRXYDuzxb70i9Qh5MVCUyAUzBYNBjLl6gQlbCD3kLxlFcQnZ77O83U6DRCyNGq1oKFGXnF2L9icWO+a/cjtvKxzvKYYnnmEA94BQQvOxBhbG81MVhO8BpTyKoNYig3J7Jb2LjWoVsS591gNV26nOdIesq+2vnvzM2iykjr2s1PYsBUtv62nVCF6l8nWydrCaKN32vH17oeL08wLQpQCV6gvErn8Qbuuf1uee8sHZIrdjG+ftozqvMGJSm1oJSm+Ac5jW9HCfUoHV81TNLdOne2owlE+GOJXVQTfDGLbgvvxVfUUzQFOtcmeX2vNym0PMEFb83/4/KBrO+8vaPCftcF9pL3K5QSpqocAM0lXlmPWRupFxeXzzTG1Ddk70ssaAGWJ+J6PuCswOMQ8/YfopM4JPFbuiPMIdCoMIMwv9h/cBBg8C04QN+35JP07yYTGE8udj3crKpkSwFVml+XgZwDvlOYHoXEOk554WCtz1LcOe8sOUiXce0tHwGmu3BnTxZ3W8YV1EqLdbMWGpJYoFcWt8me3j7kAqwtJnhcokhNyrhtGvc4gOclx1PhsEpSRLf4jadTrVzfxsAdWJQhOn6FUZgfXnkNanE0UVp19ucGqyZBVk8fEtDPRO1tenfYZ1QXBLNdXB1ivcEwU4HvopNWSjHIfVPloToYBUwWqEx0Q0/XZm7Ghwq7t0H1bynzP6jM7sqUvypYYRWE8nWxkPFg/t4kd4IDPJ/y8cYgN508VAviH4BSsyIyw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(1800799024)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ielOsLcWIrNaPQ2ThBt455f8zYFAWNgwF4vV9YR9RbWGXl18wGKSo6BNIaSUCqMnZwTiAW8aA2EWRbW2fpqrPcA6/4dRKY+ZQLKbeQJ6cBJlDZazebFnuFiZATlj+nZCVRrzyN9i8xGQWafenxd/r5UTIIBOVz8aXKdliabaFtnm/6qaAGljiiB62On7YRoNouGlyIsldUE3bnzj/ywfBELqcxey0qx1Dm/MqNDrg9YTV2Opyv+vu+K/iTLA8nx+Mtqqd6u7y8jVYpLfLVZIMrm6QRYAAkMqyHLc2OY1ZOcxvqlF+9eDXWi7wxQO0O8xUJnSMKyt/4z3CpNrgOGA3y8lH2IdvTGNa9c06ffWZqNXCIcuLXOqqA0XPIoPXfUqw6xDSQjyGtzi7RhpUMOn16k+2mrgpGqlSN28iympjjE4I6ITQVfejuL+7I8iCoUH X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:41.8905 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2be0d0b2-c303-4a31-442c-08de8b2da0bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9481 amd-pstate driver has per-attribute visibility functions to dynamically control which sysfs freq_attrs are exposed based on the platform capabilities and the current amd_pstate mode. However, there is no test coverage to validate that the driver's live attribute list matches the expected visibility for each mode. Add amd_pstate_ut_check_freq_attrs() to the amd-pstate unit test module. For each enabled mode (passive, active, guided), the test independently derives the expected visibility of each attribute: - Core attributes (max_freq, lowest_nonlinear_freq, highest_perf) are always expected. - Prefcore attributes (prefcore_ranking, hw_prefcore) are expected only when cpudata->hw_prefcore indicates platform support. - EPP attributes (energy_performance_preference, energy_performance_available_preferences) are expected only in active mode. - Floor frequency attributes (floor_freq, floor_count) are expected only when X86_FEATURE_CPPC_PERF_PRIO is present. Compare these independent expectations against the live driver's attr array, catching bugs such as attributes leaking into wrong modes or visibility functions checking incorrect conditions. Signed-off-by: Gautham R. Shenoy Reviewed-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate-ut.c | 139 ++++++++++++++++++++++++++++++-- drivers/cpufreq/amd-pstate.c | 8 ++ drivers/cpufreq/amd-pstate.h | 4 + 3 files changed, 146 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-u= t.c index 3dcdf56883a6..1f62ab6438b4 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -23,6 +23,8 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include +#include +#include #include #include #include @@ -53,13 +55,15 @@ static int amd_pstate_ut_check_enabled(u32 index); static int amd_pstate_ut_check_perf(u32 index); static int amd_pstate_ut_check_freq(u32 index); static int amd_pstate_ut_check_driver(u32 index); +static int amd_pstate_ut_check_freq_attrs(u32 index); =20 static struct amd_pstate_ut_struct amd_pstate_ut_cases[] =3D { - {"amd_pstate_ut_acpi_cpc_valid", amd_pstate_ut_acpi_cpc_valid }, - {"amd_pstate_ut_check_enabled", amd_pstate_ut_check_enabled }, - {"amd_pstate_ut_check_perf", amd_pstate_ut_check_perf }, - {"amd_pstate_ut_check_freq", amd_pstate_ut_check_freq }, - {"amd_pstate_ut_check_driver", amd_pstate_ut_check_driver } + {"amd_pstate_ut_acpi_cpc_valid", amd_pstate_ut_acpi_cpc_valid }, + {"amd_pstate_ut_check_enabled", amd_pstate_ut_check_enabled }, + {"amd_pstate_ut_check_perf", amd_pstate_ut_check_perf }, + {"amd_pstate_ut_check_freq", amd_pstate_ut_check_freq }, + {"amd_pstate_ut_check_driver", amd_pstate_ut_check_driver }, + {"amd_pstate_ut_check_freq_attrs", amd_pstate_ut_check_freq_attrs }, }; =20 static bool test_in_list(const char *list, const char *name) @@ -293,6 +297,131 @@ static int amd_pstate_ut_check_driver(u32 index) return ret; } =20 +enum attr_category { + ATTR_ALWAYS, + ATTR_PREFCORE, + ATTR_EPP, + ATTR_FLOOR_FREQ, +}; + +static const struct { + const char *name; + enum attr_category category; +} expected_freq_attrs[] =3D { + {"amd_pstate_max_freq", ATTR_ALWAYS}, + {"amd_pstate_lowest_nonlinear_freq", ATTR_ALWAYS}, + {"amd_pstate_highest_perf", ATTR_ALWAYS}, + {"amd_pstate_prefcore_ranking", ATTR_PREFCORE}, + {"amd_pstate_hw_prefcore", ATTR_PREFCORE}, + {"energy_performance_preference", ATTR_EPP}, + {"energy_performance_available_preferences", ATTR_EPP}, + {"amd_pstate_floor_freq", ATTR_FLOOR_FREQ}, + {"amd_pstate_floor_count", ATTR_FLOOR_FREQ}, +}; + +static bool attr_in_driver(struct freq_attr **driver_attrs, const char *na= me) +{ + int j; + + for (j =3D 0; driver_attrs[j]; j++) { + if (!strcmp(driver_attrs[j]->attr.name, name)) + return true; + } + return false; +} + +/* + * Verify that for each mode the driver's live ->attr array contains exact= ly + * the attributes that should be visible. Expected visibility is derived + * independently from hw_prefcore, cpu features, and the current mode =E2= =80=94 + * not from the driver's own visibility functions. + */ +static int amd_pstate_ut_check_freq_attrs(u32 index) +{ + enum amd_pstate_mode orig_mode =3D amd_pstate_get_status(); + static const enum amd_pstate_mode modes[] =3D { + AMD_PSTATE_PASSIVE, AMD_PSTATE_ACTIVE, AMD_PSTATE_GUIDED, + }; + bool has_prefcore, has_floor_freq; + int m, i, ret; + + has_floor_freq =3D cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO); + + /* + * Determine prefcore support from any online CPU's cpudata. + * hw_prefcore reflects the platform-wide decision made at init. + */ + has_prefcore =3D false; + for_each_online_cpu(i) { + struct cpufreq_policy *policy __free(put_cpufreq_policy) =3D NULL; + struct amd_cpudata *cpudata; + + policy =3D cpufreq_cpu_get(i); + if (!policy) + continue; + cpudata =3D policy->driver_data; + has_prefcore =3D cpudata->hw_prefcore; + break; + } + + for (m =3D 0; m < ARRAY_SIZE(modes); m++) { + struct freq_attr **driver_attrs; + + ret =3D amd_pstate_set_mode(modes[m]); + if (ret) + goto out; + + driver_attrs =3D amd_pstate_get_current_attrs(); + if (!driver_attrs) { + pr_err("%s: no driver attrs in mode %s\n", + __func__, amd_pstate_get_mode_string(modes[m])); + ret =3D -EINVAL; + goto out; + } + + for (i =3D 0; i < ARRAY_SIZE(expected_freq_attrs); i++) { + bool expected, found; + + switch (expected_freq_attrs[i].category) { + case ATTR_ALWAYS: + expected =3D true; + break; + case ATTR_PREFCORE: + expected =3D has_prefcore; + break; + case ATTR_EPP: + expected =3D (modes[m] =3D=3D AMD_PSTATE_ACTIVE); + break; + case ATTR_FLOOR_FREQ: + expected =3D has_floor_freq; + break; + default: + expected =3D false; + break; + } + + found =3D attr_in_driver(driver_attrs, + expected_freq_attrs[i].name); + + if (expected !=3D found) { + pr_err("%s: mode %s: attr %s expected %s but is %s\n", + __func__, + amd_pstate_get_mode_string(modes[m]), + expected_freq_attrs[i].name, + expected ? "visible" : "hidden", + found ? "visible" : "hidden"); + ret =3D -EINVAL; + goto out; + } + } + } + + ret =3D 0; +out: + amd_pstate_set_mode(orig_mode); + return ret; +} + static int __init amd_pstate_ut_init(void) { u32 i =3D 0, arr_size =3D ARRAY_SIZE(amd_pstate_ut_cases); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5eae74a67aeb..ed9fd4155a25 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1390,6 +1390,14 @@ static struct freq_attr_visibility amd_pstate_attr_v= isibility[] =3D { {&amd_pstate_floor_count, floor_freq_visibility}, }; =20 +struct freq_attr **amd_pstate_get_current_attrs(void) +{ + if (!current_pstate_driver) + return NULL; + return current_pstate_driver->attr; +} +EXPORT_SYMBOL_GPL(amd_pstate_get_current_attrs); + static struct freq_attr **get_freq_attrs(void) { bool attr_visible[ARRAY_SIZE(amd_pstate_attr_visibility)]; diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index 453adfb445f8..faead0b19a8a 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -134,4 +134,8 @@ const char *amd_pstate_get_mode_string(enum amd_pstate_= mode mode); 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Shenoy" , Jonathan Corbet , "Shuah Khan" , Mario Limonciello Subject: [PATCH v4 10/12] Documentation/amd-pstate: List amd_pstate_hw_prefcore sysfs file Date: Thu, 26 Mar 2026 17:17:54 +0530 Message-ID: <20260326114756.20374-11-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E0:EE_|SN7PR12MB6689:EE_ X-MS-Office365-Filtering-Correlation-Id: efbcc7db-93a3-434e-117b-08de8b2da30f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: A3iFibFw17NOEBJsTVWkzU0zf5qTW6x5JKtWgF6W4mJMaFqrBVCU69O43Tu0J4YzKNL3S8rJ/nmgalDmcphI2KemXW5f3Yoga4cH7+YyPSA7hLW65ji2Ih/SIemYnoQptSg5eoVbfkDbMxnPsFyzYU8LnBSwasCuETu4nZs5dB5yHmoQZDrCnXEf71gnnJCOFYm+2BRsB0zPrFHOhpqhEqwMWi5Jnu8fKd0JoLYWFoPuwJCUN2mmlO65I6cz3UuX2aAhAxrTPxInC3PsOZ8aIQHapleeaUpLVFQbN9nyl2Vsy6ujqqvUnYqM7AzBqZdNqkkFlnHGkKa8fHgNu3HdEJAJezLK6r7md60CzudsDgdSS6byN7df7t+Tkn0CKzX5dDcan+GH8PLOnHSM1zGRQHSLTS3oPCym8pWkurPcJTbqaz/PiFWpenF0YBgR6F63T5bCc1bswJsiK2kP0ZzlEt/ssrGW8VrXg54BZ5yWYG043Em3aWpz/4OItkN5bfQj0sVJj0w6bCWgNT8V68h2ilk6j6iMkjHuS9PaEaMcsAk+pGqbVRgwyIrU5S7235acKB64JsOe8G1x4zo/el6Mu6F6l5NxLcKA3W1q0aJ5haA58NMdwVaK8xfCMeqsn2Xyr7AWJwCyWnrb5Tka3rJO9oxJBMR4Jn2kAVhHt2gF73zeCSmYW6X6J3WLPYN1zqZNZYbUWfAScw8C/QVMgTFHYBPhBVmwGymkHNgy+wOSIPVQpeT4bErH1+pezQpbt3inypkHbzGlKnBIkqnYC5kO/w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wsAjCPqxE830ICI4QG2GvdoDIpHjDvl1v6vrC5Kq+eVKngizjmWa26lh0wEirbwXjXS6cWcJr2HwQSnvPmVWmWMJ8baisMjyBLAUi3iEkXEmqR5j8JR5uGV4vwamc00nKJhyHCZofXOk1VSBOzrWnhSmooou11foISmLTCYWEsf3ys/91ubXSpBxaCoHW29NoJ0UmsNTVw5/llqHFlxNA6UZXP1MvE901OU7Yt5FqGg1dpzhLMtK52QeE7XVSW3d6QcNNHMhXHPcLVL2Be2+A0enjB8mMXp8J8Qk2IpavGefN+8bZgfuirxBDFJFyWLjF3WUCXRl0yO3uzHFUekXTm3oypkw1X5RuLsodtmUwqQUfVDQxpe/siEdzgEdsl8BNKqTYkwyqKsLKkEBCvCtw6vW3q8Aw3DKfLpU34iacMDw8NHf4H/QXPmk4Wob7z6R X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:45.7895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efbcc7db-93a3-434e-117b-08de8b2da30f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6689 Content-Type: text/plain; charset="utf-8" Add the missing amd_pstate_hw_prefcore filenames in the sysfs listing example leading to the descriptions of these parameters. Clarify when will the file be visible. Fixes: b96b82d1af7f ("cpufreq: amd-pstate: Add documentation for `amd_pstat= e_hw_prefcore`") Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index e1771f2225d5..b8c846cbf301 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -239,6 +239,7 @@ control its functionality at the system level. They are= located in the =20 root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd* /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_highest_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_hw_prefcore /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq =20 @@ -264,8 +265,9 @@ This attribute is read-only. =20 ``amd_pstate_hw_prefcore`` =20 -Whether the platform supports the preferred core feature and it has been -enabled. This attribute is read-only. +Whether the platform supports the preferred core feature and it has +been enabled. This attribute is read-only. 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Shenoy" , Jonathan Corbet , "Shuah Khan" , Mario Limonciello Subject: [PATCH v4 11/12] Documentation/amd-pstate: List amd_pstate_prefcore_ranking sysfs file Date: Thu, 26 Mar 2026 17:17:55 +0530 Message-ID: <20260326114756.20374-12-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DE:EE_|DS2PR12MB9751:EE_ X-MS-Office365-Filtering-Correlation-Id: 39e14715-45fd-4f3a-f39e-08de8b2da45f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: fzpNcOZ4/UNudKftlwl/GKX93kGqr5MHjsXVFHXXz6KoPSD2RGiuMwxF1Z0tYP/Wk2s2/IFOJmSQh+JCQ4qGtvFV2QsILAVVMLJ6I/fHzXv2GCSJ7M3XcE7NT7zpQBHdPF47Yq4WZKj2HfdUvwZ4TdoBteBYgpoHh51F05FrN9siQbmTiRsrGdOozBQA2xHUYy1DECdHbSfM5rtntb9Z47N5rJejyMFJJFqULU/5ngAK05S9ZHglNMJRTJg5yeLxg5rcoO0nCOYqRjqW0IV9uGvs0xGHqfgODX+f4jQAwvLyUnkLq7Lund6PtDmU9HM9yweu+JcgCzaQE2ejJSFkEGIJLJbAjAL8Fet6H6UJO3C8r3CWXhjcA5AVSrMGCqrMbIK8kHrp6hCCY1AmZZqnXfvn+Gcbbb0l0KJ8JtYZgdgCgekVM8tQVje8ZYB/U3JjKAtAtcV07dJE+OTMK6caeIBYUNTZTmBB3vQjOuD7iqR3TqiWG+vKwvt5hV2DaGZ2T+hqTZnVxyTVCdXcf5Iq+xNGZKQ3LXAPXkaEp74k7Gzn8d/C/NWVU+jIYh4HbogDYGEL12uYUz3hMrHfWzcI3R8h9nEyotdpLrhFfKHzOAYx6VPcAxjVRmvVXHS6PaSowG8mNcQrdTsZAitTL5ESG47hi9FAPaMcqZyNeGlkyNYkc9L7tG/XrfH2kdkOrJr4Pri4vAMP18ZQfAl6iJ1l+WLaSOHAGT4I/ew5tEBH9AhR/nc/nHoC4/K9652cldDzycMBSdq0mw3nLq58wtZovw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UDJ3/rOyoHOLJ24NolZsvm30H41jviELnugARyZ+C7wgLxZe16cIGzV2VqcZkwEhwSRHHx1KJ3nmL9882AiYuWCdvkDymlwir6nNj7D2hD8bKIlvllmhQiKJsd3v+pMTB9VkTNAYgdjSEKsNN9JfMt+UrTZHgaTvMiozgXexH1euKukyP7jxmPZtMgcqFYfSwFsYcXnxGPZlqDvjAyh3tHMrj1Dm2WwKem6CuxBaUM6I7Y6v08Lc8WFmIpIujVVpfYAjzjZEqVhyj5RNLhMdriFdFpcmdms7OWWZG+pKyamyu0GSumX5EMjtrWBdxwhPK1QTlNrXeETVF9WCH+qxCFRy408qCinQOenvissZ1a0SsKKJqrBZ5BtUCQldPpG5/dizqN1M4FVTG1zpRQu9BfhBYiNg/PYolYHvhINh1emTnc07PKFFdSwzcEPmgnOt X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:48.0218 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39e14715-45fd-4f3a-f39e-08de8b2da45f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9751 Content-Type: text/plain; charset="utf-8" Add the missing amd_pstate_prefcore_ranking filenames in the sysfs listing example leading to the descriptions of these parameters. Clarify when will the file be visible. Fixes: 15a2b764ea7c ("amd-pstate: Add missing documentation for `amd_pstate= _prefcore_ranking`") Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index b8c846cbf301..b31a478c28ba 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -242,6 +242,7 @@ control its functionality at the system level. They are= located in the /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_hw_prefcore /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_prefcore_ranking =20 =20 ``amd_pstate_highest_perf / amd_pstate_max_freq`` @@ -273,7 +274,8 @@ on platforms which support the preferred core feature. =20 The performance ranking of the core. This number doesn't have any unit, but larger numbers are preferred at the time of reading. This can change at -runtime based on platform conditions. This attribute is read-only. +runtime based on platform conditions. This attribute is read-only. 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Shenoy" , Jonathan Corbet , "Shuah Khan" , Mario Limonciello Subject: [PATCH v4 12/12] Documentation/amd-pstate: Add documentation for amd_pstate_floor_{freq,count} Date: Thu, 26 Mar 2026 17:17:56 +0530 Message-ID: <20260326114756.20374-13-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260326114756.20374-1-gautham.shenoy@amd.com> References: <20260326114756.20374-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DE:EE_|CY1PR12MB9675:EE_ X-MS-Office365-Filtering-Correlation-Id: dd55e161-9543-43b9-af57-08de8b2da63c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|376014|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: IgzTaW2kw+CFEyg7gg9QSIT1MU4nTGx7Ez5BfUw5KdW9TSvMBNqlA9d+CY8YhD3uQCkwC8/vcyIek2IcUSvKVoRQeOfgTIVj6OTRCRUbB0Ey6tlxNld+aqL6za1/lb4ZGLPyzhnzahKoVJxVIpE0EtuJId+JHAX0KGAZnQNJtzNFEG3WtYov8K6Ser6QaQ3zNI1KtpAjAetslTNbiFkHgGfIBnniCEWSTcUkzJjmexkcVap92gJqqg86ybAjEPLDcCcesGuPZJLB7oFZVhYcIJQdNj+g/6dU4NV/VGFjMgHXCucPS4FR/7C9ah1Z/JhxWW9MtjQq2btW69OR73EJgA1KGM2IXQOHVsbOoq8LHdoZ+HMRb249Smrtcofz0KEGMXeFjQAULgbGWOXBg74pYuwCZVG1vRs6Fnyi8lKZ12h8jPv8lTekhP/q/YNq2BXKA2wh2p1eBpF9lUiGyGcNIPV/yINedMiTysXONrgO7ucOyajxUD5QVG+iGas0qumB4bFiocyzpP7HTMAwoQYDIMkYG+IsfvfWd0Zdvuhsxq4zle6goQ9EU65ZG14TY3ATJWJH9SQZIsVEmXwd0EivoyWAbcG4unds4Fo33TAKidPCyGTDABjDroZh0faMpq0FUUAjGJAoWN3E8mIN0MzBCy7JXlfF8181AxRPIITVYN4Jm7DXOUYRw5rTlA8MaY6+vY3F8Uok7iH63Mkq8dMppwaWux/hu2J2C7/uskag3ffD4PFnFS+NoqL/vn5y2gHPHNKeblWadZ5BFIOsIwmKFg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(82310400026)(376014)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5IBhJOBH6queeBYjAm6X7lMT5NXresPPvDPIY8v/VutWVV288Hz4P5wJXMWFU6bqf4Do6yW/qy2Pjx6a5c4zgivfSpyILhSkGweNRpjfl+4J+OENhiGZKMvsXle76V8H5FwMyjE/teANpcKd0VLttP0NOZHMR/J8/ngENgtg2cWrb2Ma0znw+DML3oyWMhdvMPfe0UrpnqBLTqr6rSob2a6+rDahu+f4Fyv767xr5ahnoXwZeuH0v5RXH4TWGwnpeQlliaciTlhp0TgCRCBIdYSPNJ5+z2rJcUB/I8V/Y44oTcUuvcXh8tce3RIziW3zpaHR32mBpkGii/+rDnY1TBmIMga6jBcX4Ax2MK/zHLeIXdVI8yJclvdDMmu20VKk0hvEOz/pFxoCcBFExR1RULDVk93mcSS27YeYNG1woDHme9ciyDW6zSIpOTWI3C/R X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2026 11:48:51.1173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd55e161-9543-43b9-af57-08de8b2da63c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9675 Content-Type: text/plain; charset="utf-8" Add documentation for the sysfs files /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq and /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_count. Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index b31a478c28ba..d6c2f233ab23 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -242,6 +242,8 @@ control its functionality at the system level. They are= located in the /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_hw_prefcore /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_count /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_prefcore_ranking =20 =20 @@ -277,6 +279,36 @@ larger numbers are preferred at the time of reading. T= his can change at runtime based on platform conditions. This attribute is read-only. This fi= le is only visible on platforms which support the preferred core feature. =20 +``amd_pstate_floor_freq`` + +The floor frequency associated with each CPU. Userspace can write any +value between ``cpuinfo_min_freq`` and ``scaling_max_freq`` into this +file. When the system is under power or thermal constraints, the +platform firmware will attempt to throttle the CPU frequency to the +value specified in ``amd_pstate_floor_freq`` before throttling it +further. This allows userspace to specify different floor frequencies +to different CPUs. For optimal results, threads of the same core +should have the same floor frequency value. This file is only visible +on platforms that support the CPPC Performance Priority feature. + + +``amd_pstate_floor_count`` + +The number of distinct Floor Performance levels supported by the +platform. For example, if this value is 2, then the number of unique +values obtained from the command ``cat +/sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq | +sort -n | uniq`` should be at most this number for the behavior +described in ``amd_pstate_floor_freq`` to take effect. A zero value +implies that the platform supports unlimited floor performance levels. +This file is only visible on platforms that support the CPPC +Performance Priority feature. + +**Note**: When ``amd_pstate_floor_count`` is non-zero, the frequency to +which the CPU is throttled under power or thermal constraints is +undefined when the number of unique values of ``amd_pstate_floor_freq`` +across all CPUs in the system exceeds ``amd_pstate_floor_count``. + ``energy_performance_available_preferences`` =20 A list of all the supported EPP preferences that could be used for --=20 2.34.1