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Thu, 26 Mar 2026 04:19:56 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 1/2] arm64: dts: renesas: r9a08g046: Add GBETH nodes Date: Thu, 26 Mar 2026 11:19:49 +0000 Message-ID: <20260326111953.31024-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260326111953.31024-1-biju.das.jz@bp.renesas.com> References: <20260326111953.31024-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Renesas RZ/G3L SoC is equipped with 2x Synopsys DesignWare Ethernet (10/100/1000 BASE) with TSN, IP block version 5.30. Add GBETH nodes to R9A08G046 RZ/G3L SoC DTSI. Signed-off-by: Biju Das --- v2->v3: * Rebased to boot series. v1->v2: * Added rmii_{tx,rx) clocks. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 241 +++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index e030e785ea2a..0987c531ecf4 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -171,6 +171,240 @@ sdhi1: mmc@11c10000 { /* placeholder */ }; =20 + eth0: ethernet@11c30000 { + compatible =3D "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg =3D <0 0x11c30000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks =3D <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets =3D <&cpg R9A08G046_ETH0_ARESET_N>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup0>; + snps,mtl-tx-config =3D <&mtl_tx_setup0>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,weight =3D <0x14>; + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,weight =3D <0x18>; + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + }; + }; + + eth1: ethernet@11c40000 { + compatible =3D "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg =3D <0 0x11c40000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks =3D <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii", "rmii_tx", "rmii_rx"; + resets =3D <&cpg R9A08G046_ETH1_ARESET_N>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,weight =3D <0x14>; + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,weight =3D <0x18>; + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + }; + }; + pcie: pcie@11e40000 { reg =3D <0 0x11e40000 0 0x10000>; ranges =3D <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; @@ -200,6 +434,13 @@ gic: interrupt-controller@12400000 { }; }; =20 + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <16 8 4 0 0 0 0>; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.43.0