From nobody Thu Apr 2 03:25:00 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3DB53B7747 for ; Thu, 26 Mar 2026 11:06:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774523218; cv=none; b=M1xyOyxVcFlPxQTQHnOCYj/nvgFGRLYlKrLzzYAx6hR/TgNNhFemIc/nzAIK66kGAHtne44wWbrCeuV2RdUX4qhlrr0Lt4xIxBMVjAMufo2vLSHCDBOdGiN8maUOzQmm3BjeHZxLjJEN0q/LKqyW/jtL3tNAZZgVNtO4+ctQVSI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774523218; c=relaxed/simple; bh=IBunreoW2Vz7TC5D+BTns8wsUPA87aNp96COj6e2e9U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E9yIB4zL3YKP9UAN3zm7rMkQ3SVPqU7HvK8oKq5qcFglKPXcGjmZ98LwkspRgQSSC4dyYex8LOqXpXzGdbh/X3iNfvIlnM9CjLrAe8MCz/TJKbup9QRBRGRc00H6MAc4YgE9O+c/3No817+R2VggD5zaf+DEZSgqN00A6402Ti0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gZyPF/cL; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gZyPF/cL" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-439b6d9c981so489057f8f.1 for ; Thu, 26 Mar 2026 04:06:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774523214; x=1775128014; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LKs+3rwoSUHeOFuDrt1zQk3ixT4LmadR536MQVAir4E=; b=gZyPF/cL+6OIo5HpkwRfh3DsNTJGopW6yC5o9wtV0dQtbAannNMtFB1VekDiafD8YE FH4HjmCzqti6pjLDis2+fgRaER2bTVKNTjTi0gnO3Fe82tcVyAkNyC9fZEV9WlVD7CvH G5GlhylBfYiNWu64IzP8XHPgkwLVxCnysW6o/Ye2BUapJxoJoUhoP+/jrXdn6BPkR7CO lt87uM/CNuRqOVt3/OTyo/Tyy6MAWbzn/lzE2qImf/0iiCm1nNApKnE0fhLDW5hyDwrV tbo9igEtHfxLzXdEfKwUJMEYpTvdOHBJDL6GPYQEvaDwhKPz28hDzs9cyGigGD3QuVj3 YgKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774523214; x=1775128014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LKs+3rwoSUHeOFuDrt1zQk3ixT4LmadR536MQVAir4E=; b=AHKRbhNt75vJH6u/SjK+fAIQF7fz9LgpFUrfQFfNBTY5HDRXfI9DN+rsWFZPhOr3hu o6ulYxeEehdmiQ3xZh4y2tS1rl+HkQC8GI2ejYTkQY89bCIiJzcK2H/l3iWqZ4dmgYAK q3Fj8cAVcGYohp5+2i5aDC0jJ3BLGy/am9Ho/6IVEPJGAE8L9O41XgnE1g9cjdTGUhXk aXHSDuJd4Mv4ffx7CNANEkbcv4bFrKmbgvXZtrTNintimCAxP0MSE/luECLVWWBya0Sk cQNULb1gmTUBGCX6gPxFefXrABuQpZ1lr6KHmWwKS9oAOq9Xz8KTCT6dNfHeHHtBsH2/ vGDA== X-Forwarded-Encrypted: i=1; AJvYcCW/gmuDdl2uMIampAWVgIQwCnQ0BuVyw/LgNIt9e7doVH3D0qho8L9dxTH43g0GaISgxIIc0n1H92RDPgA=@vger.kernel.org X-Gm-Message-State: AOJu0YyxwS1QNoAlrQNxIx8Lov/zYhy59uNMwSQe5OQpWl4A5Ieivbsc kDYe1LrVlZnJ8SOAM8xayJpWevTQme0vQWVZX839YNfMF9vI3CpDLhV2 X-Gm-Gg: ATEYQzxmH2bP9edBBIbX9Wz1TVZiim0VjQYGkjz5M4K7EqtwolSisivit7zRnMgQ0DM GaOz35GlBK0Jimuuocr4UZdIlhcTLPz2+oBhzwPE4oPNyl3tD0QLtvw/gABkUDyiiMRTJT5wCfW u/7oeRRPCip8rWgCHtj/pnjepICZ4xGyyccjQr4IXvbZVfn2EnFWQDhQ6sbv+z1QMQu9rVaL2Zn yiEJ96fR2xJO9j9ZWt/pF75VDWAb1WU5eIqONO4Q1s6AcVRZTIfXUncXbttWgsIVqQdrp7LBtIY BWYLxd9fcsE7U8wL5pVJTLr1NJ5j1dSJg1iGaamXHz04YOhR2C+0METojYjm2e1wouj4NqXof7q 4WWDMflAeTEZJV2bVURt1E2vm1k700npJRMSEzYOzSU570pOW717eR3toWg7jheCR0tnlUBhWKA gRRniozz/4vwutsZcdE98ICCq0FKLOV4VPZ8S1dX0sCTm9givO X-Received: by 2002:a05:6000:4213:b0:43b:48a4:a4d7 with SMTP id ffacd0b85a97d-43b97a1fcf0mr1791495f8f.10.1774523214163; Thu, 26 Mar 2026 04:06:54 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:377f:9a3e:6c94:560d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b9194311asm8626084f8f.10.2026.03.26.04.06.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 04:06:53 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v5 3/4] clk: renesas: r8a08g046: Add support for PLL6 clk Date: Thu, 26 Mar 2026 11:06:37 +0000 Message-ID: <20260326110648.29389-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260326110648.29389-1-biju.das.jz@bp.renesas.com> References: <20260326110648.29389-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for PLL6 clk by registering with rzg2l-cpg driver. Signed-off-by: Biju Das --- v4->v5: * Rebased to boot series. v3->v4: * No change v2->v3: * No change v1->v2: * No change --- drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index 6c77afdd34ea..31d800e6bcda 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -29,6 +29,9 @@ #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) =20 +/* PLL 1/4/6/7 configuration registers macro. */ +#define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12= | (setting)) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK =3D R9A08G046_USB_SCLK, @@ -45,6 +48,7 @@ enum clk_ids { CLK_PLL2_DIV2, CLK_PLL3, CLK_PLL3_DIV2, + CLK_PLL6, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -78,6 +82,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __= initconst =3D { /* Internal Core Clocks */ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, G3L_PLL1467_CONF(0x54, 0x58, 0), + 500000000UL), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), =20 --=20 2.43.0