From nobody Thu Apr 2 22:17:53 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 762F137B3F9; Thu, 26 Mar 2026 07:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774510810; cv=none; b=lzkBwwqSJoI4tsQk/je+TpR7H2yjtdD5tCiAEwR26SASpRsV87Nn0XbLO7c5FsfX+Tyg/NMFff6RLqtTsmToT746X4msv2g8JT4wEcp9CfIKtPM+s30vUq54BiX9vCTECWIrw4pHolygJ0Fg6WWwNNkePzenUzfktso/HtMXIhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774510810; c=relaxed/simple; bh=EvM7NQx5GjHWorWcY08ZjKEINGW3WusH6PLz+Tn+ASo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iELAlXn2tP3teQ0Za6A116D1F5vM2YzbneSPy7T+VXoaemp3Yi6o40KlWB5w4qq2QLV0ALLoydePefH8ooN/FtCaNz0nYaQtFlMRL69q8TQ0jgRcLtFpkmdf8kyLGwV3mqX2WnMMuR0Zf779s6ahZXh9cU+zolYP7Cas6P/BqtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=flLHb/rT; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="flLHb/rT" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 62Q7dYeA51073983, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1774510774; bh=PgmCrJ+9O3Y+5rUuYewSMg060W75OZyNCU653i4Ir5U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=flLHb/rTMF/ong+kSJxqeNF4v8gsOmpTQrUU+fj9NE9OXZ/j1eodVCbfqp42dTDIc PlUE/7UtXW507q4ihQ76H+6Lp3agG5kB5QGLN2ZVuTNpJmnssvFJI/gQA16UpQyu3u FJql5U4Qee+d4Fm7ay8CSYkM4DXUVOUnNpcNnu4EzGiHKBqWoslxyaZusvDAGlx2Q5 E2ieY9AIAF1IJohLhSOD89GNnvzQNSzfGZ3urqb3qgJh8VUhIkoLx+hW1Thh3IMH0r kE5HzZcRBuEMqvAWO7vpAz+Bodj15hReBUwiAQImuQppmMTcdmIzpU8fFqQCOZnRR6 UhYe9AJV/EfYA== Received: from mail.realtek.com (rtkexhmbs04.realtek.com.tw[10.21.1.54]) by rtits2.realtek.com.tw (8.15.2/3.26/5.94) with ESMTPS id 62Q7dYeA51073983 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 26 Mar 2026 15:39:34 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 26 Mar 2026 15:39:34 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 26 Mar 2026 15:39:34 +0800 Received: from fc40.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 26 Mar 2026 15:39:34 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , Chih Kai Hsu Subject: [PATCH net-next v4 1/3] r8152: fix incorrect register write to USB_UPHY_XTAL Date: Thu, 26 Mar 2026 15:39:23 +0800 Message-ID: <20260326073925.32976-454-nic_swsd@realtek.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326073925.32976-453-nic_swsd@realtek.com> References: <20260326073925.32976-453-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The old code used ocp_write_byte() to clear the OOBS_POLLING bit (BIT(8)) in the USB_UPHY_XTAL register, but this doesn't correctly clear a bit in the upper byte of the 16-bit register. Fix this by using ocp_write_word() instead. Fixes: 195aae321c82 ("r8152: support new chips") Signed-off-by: Chih Kai Hsu Reviewed-by: Hayes Wang --- drivers/net/usb/r8152.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 3b6d4252d34c..bef0611e7ef0 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -3892,7 +3892,7 @@ static void r8156_ups_en(struct r8152 *tp, bool enabl= e) case RTL_VER_15: ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); ocp_data &=3D ~OOBS_POLLING; - ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); + ocp_write_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); break; default: break; --=20 2.34.1 From nobody Thu Apr 2 22:17:53 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07F4D34C128; Thu, 26 Mar 2026 07:40:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="cVHy5bYE" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 62Q7dZRS11073985, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1774510775; bh=5bIeGIzyqOAs3ZRr8jkkXyUQiwWnC31hcfwHJnlnGL4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=cVHy5bYEqHSI6YUeWPP1pTfl13cH9VLTUyDU6HS1SV+HlrccCTNxzf+hRZNBcF+NT uJBFwZYYdCohiiz0//tUQpoi9rCXRc0RDXaA2600jjYGe8wk/w0lDm+BJlsTfrZwih gFAk5VQiFQos4Y8QoDhic0xKSnJB+8c6GVhFOahsj4yg9HMbZvO/q8M32dczBA32d3 24H6FvBhjLVr7hx9COU+iIpqzZH+MIfZnfALEcx8xMVZJdSmsBp74AdzfjzUE7OxYu B9CANj155ZA0jB881EFuMEcsSQ/3l+x6OOvK+ZmxBriS+cmEb21iH9hYdmhOIfITWK Gcx2hlW061/Vg== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.26/5.94) with ESMTPS id 62Q7dZRS11073985 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 26 Mar 2026 15:39:35 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 26 Mar 2026 15:39:35 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 26 Mar 2026 15:39:34 +0800 Received: from fc40.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 26 Mar 2026 15:39:34 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , Chih Kai Hsu Subject: [PATCH net-next v4 2/3] r8152: add helper functions for PLA/USB OCP registers Date: Thu, 26 Mar 2026 15:39:24 +0800 Message-ID: <20260326073925.32976-455-nic_swsd@realtek.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326073925.32976-453-nic_swsd@realtek.com> References: <20260326073925.32976-453-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the following bitwise operation functions for PLA/USB OCP registers to simplify the code. - ocp_dword_w0w1() - ocp_word_w0w1() - ocp_byte_w0w1() - ocp_dword_clr_bits() - ocp_dword_set_bits() - ocp_word_clr_bits() - ocp_word_set_bits() - ocp_word_test_and_clr_bits() - ocp_byte_clr_bits() - ocp_byte_set_bits() Signed-off-by: Chih Kai Hsu Reviewed-by: Hayes Wang --- drivers/net/usb/r8152.c | 1103 +++++++++++++++------------------------ 1 file changed, 408 insertions(+), 695 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index bef0611e7ef0..32a4e8d42311 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -1654,6 +1654,78 @@ void write_mii_word(struct net_device *netdev, int p= hy_id, int reg, int val) r8152_mdio_write(tp, reg, val); } =20 +static void +ocp_dword_w0w1(struct r8152 *tp, u16 type, u16 index, u32 clear, u32 set) +{ + u32 ocp_data; + + ocp_data =3D ocp_read_dword(tp, type, index); + ocp_data =3D (ocp_data & ~clear) | set; + ocp_write_dword(tp, type, index, ocp_data); +} + +static void +ocp_word_w0w1(struct r8152 *tp, u16 type, u16 index, u16 clear, u16 set) +{ + u16 ocp_data; + + ocp_data =3D ocp_read_word(tp, type, index); + ocp_data =3D (ocp_data & ~clear) | set; + ocp_write_word(tp, type, index, ocp_data); +} + +static void +ocp_byte_w0w1(struct r8152 *tp, u16 type, u16 index, u8 clear, u8 set) +{ + u8 ocp_data; + + ocp_data =3D ocp_read_byte(tp, type, index); + ocp_data =3D (ocp_data & ~clear) | set; + ocp_write_byte(tp, type, index, ocp_data); +} + +static void ocp_dword_clr_bits(struct r8152 *tp, u16 type, u16 index, u32 = clear) +{ + ocp_dword_w0w1(tp, type, index, clear, 0); +} + +static void ocp_dword_set_bits(struct r8152 *tp, u16 type, u16 index, u32 = set) +{ + ocp_dword_w0w1(tp, type, index, 0, set); +} + +static void ocp_word_clr_bits(struct r8152 *tp, u16 type, u16 index, u16 c= lear) +{ + ocp_word_w0w1(tp, type, index, clear, 0); +} + +static void ocp_word_set_bits(struct r8152 *tp, u16 type, u16 index, u16 s= et) +{ + ocp_word_w0w1(tp, type, index, 0, set); +} + +static int +ocp_word_test_and_clr_bits(struct r8152 *tp, u16 type, u16 index, u16 clea= r) +{ + u16 ocp_data; + + ocp_data =3D ocp_read_word(tp, type, index); + if (ocp_data & clear) + ocp_write_word(tp, type, index, ocp_data & ~clear); + + return ocp_data & clear; +} + +static void ocp_byte_clr_bits(struct r8152 *tp, u16 type, u16 index, u8 cl= ear) +{ + ocp_byte_w0w1(tp, type, index, clear, 0); +} + +static void ocp_byte_set_bits(struct r8152 *tp, u16 type, u16 index, u8 se= t) +{ + ocp_byte_w0w1(tp, type, index, 0, set); +} + static int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); =20 @@ -2956,47 +3028,31 @@ static netdev_tx_t rtl8152_start_xmit(struct sk_buf= f *skb, =20 static void r8152b_reset_packet_filter(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); - ocp_data &=3D ~FMC_FCR_MCU_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); - ocp_data |=3D FMC_FCR_MCU_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_FMC, FMC_FCR_MCU_EN); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_FMC, FMC_FCR_MCU_EN); } =20 static void rtl8152_nic_reset(struct r8152 *tp) { - u32 ocp_data; int i; =20 switch (tp->version) { case RTL_TEST_01: case RTL_VER_10: case RTL_VER_11: - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); - ocp_data &=3D ~CR_TE; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_TE); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); - ocp_data &=3D ~BMU_RESET_EP_IN; - ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, + BMU_RESET_EP_IN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data |=3D CDC_ECM_EN; - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); - ocp_data &=3D ~CR_RE; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); - ocp_data |=3D BMU_RESET_EP_IN; - ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, + BMU_RESET_EP_IN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &=3D ~CDC_ECM_EN; - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, CDC_ECM_EN); break; =20 default: @@ -3025,14 +3081,12 @@ static inline u16 rtl8152_get_speed(struct r8152 *t= p) =20 static void rtl_eee_plus_en(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); if (enable) - ocp_data |=3D EEEP_CR_EEEP_TX; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEEP_CR, + EEEP_CR_EEEP_TX); else - ocp_data &=3D ~EEEP_CR_EEEP_TX; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEEP_CR, + EEEP_CR_EEEP_TX); } =20 static void rtl_set_eee_plus(struct r8152 *tp) @@ -3045,14 +3099,10 @@ static void rtl_set_eee_plus(struct r8152 *tp) =20 static void rxdy_gated_en(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); if (enable) - ocp_data |=3D RXDY_GATED_EN; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MISC_1, RXDY_GATED_EN); else - ocp_data &=3D ~RXDY_GATED_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MISC_1, RXDY_GATED_EN); } =20 static int rtl_start_rx(struct r8152 *tp) @@ -3140,24 +3190,16 @@ static int rtl_stop_rx(struct r8152 *tp) =20 static void rtl_set_ifg(struct r8152 *tp, u16 speed) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); - ocp_data &=3D ~IFG_MASK; if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { - ocp_data |=3D IFG_144NS; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_TCR1, IFG_MASK, IFG_144NS); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); - ocp_data &=3D ~TX10MIDLE_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + TX10MIDLE_EN); } else { - ocp_data |=3D IFG_96NS; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_TCR1, IFG_MASK, IFG_96NS); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); - ocp_data |=3D TX10MIDLE_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + TX10MIDLE_EN); } } =20 @@ -3169,13 +3211,9 @@ static inline void r8153b_rx_agg_chg_indicate(struct= r8152 *tp) =20 static int rtl_enable(struct r8152 *tp) { - u32 ocp_data; - r8152b_reset_packet_filter(tp); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); - ocp_data |=3D CR_RE | CR_TE; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CR, CR_RE | CR_TE); =20 switch (tp->version) { case RTL_VER_01: @@ -3283,8 +3321,6 @@ static void r8153_set_rx_early_size(struct r8152 *tp) =20 static int rtl8153_enable(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return -ENODEV; =20 @@ -3298,12 +3334,9 @@ static int rtl8153_enable(struct r8152 *tp) switch (tp->version) { case RTL_VER_09: case RTL_VER_14: - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); - ocp_data &=3D ~FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); usleep_range(1000, 2000); - ocp_data |=3D FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); break; default: break; @@ -3322,9 +3355,7 @@ static void rtl_disable(struct r8152 *tp) return; } =20 - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data &=3D ~RCR_ACPT_ALL; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); =20 rtl_drop_queued_tx(tp); =20 @@ -3357,24 +3388,17 @@ static void rtl_disable(struct r8152 *tp) =20 static void r8152_power_cut_en(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); if (enable) - ocp_data |=3D POWER_CUT; + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_UPS_CTRL, POWER_CUT); else - ocp_data &=3D ~POWER_CUT; - ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_UPS_CTRL, POWER_CUT); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); - ocp_data &=3D ~RESUME_INDICATE; - ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, + RESUME_INDICATE); } =20 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) { - u32 ocp_data; - switch (tp->version) { case RTL_VER_01: case RTL_VER_02: @@ -3386,12 +3410,12 @@ static void rtl_rx_vlan_en(struct r8152 *tp, bool e= nable) case RTL_VER_08: case RTL_VER_09: case RTL_VER_14: - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); if (enable) - ocp_data |=3D CPCR_RX_VLAN; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, + CPCR_RX_VLAN); else - ocp_data &=3D ~CPCR_RX_VLAN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CPCR, + CPCR_RX_VLAN); break; =20 case RTL_TEST_01: @@ -3401,12 +3425,12 @@ static void rtl_rx_vlan_en(struct r8152 *tp, bool e= nable) case RTL_VER_13: case RTL_VER_15: default: - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); if (enable) - ocp_data |=3D OUTER_VLAN | INNER_VLAN; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RCR1, + OUTER_VLAN | INNER_VLAN); else - ocp_data &=3D ~(OUTER_VLAN | INNER_VLAN); - ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR1, + OUTER_VLAN | INNER_VLAN); break; } } @@ -3467,33 +3491,33 @@ static u32 __rtl_get_wol(struct r8152 *tp) =20 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) { - u32 ocp_data; + u16 ocp_data; =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); - ocp_data &=3D ~LINK_ON_WAKE_EN; if (wolopts & WAKE_PHY) - ocp_data |=3D LINK_ON_WAKE_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, + LINK_ON_WAKE_EN); + else + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, + LINK_ON_WAKE_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); - ocp_data &=3D ~(UWF_EN | BWF_EN | MWF_EN); + ocp_data =3D 0; if (wolopts & WAKE_UCAST) ocp_data |=3D UWF_EN; if (wolopts & WAKE_BCAST) ocp_data |=3D BWF_EN; if (wolopts & WAKE_MCAST) ocp_data |=3D MWF_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_CONFIG5, UWF_EN | BWF_EN | MWF_EN, + ocp_data); =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); - ocp_data &=3D ~MAGIC_EN; if (wolopts & WAKE_MAGIC) - ocp_data |=3D MAGIC_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CFG_WOL, MAGIC_EN); + else + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CFG_WOL, MAGIC_EN); =20 if (wolopts & WAKE_ANY) device_set_wakeup_enable(&tp->udev->dev, true); @@ -3503,35 +3527,27 @@ static void __rtl_set_wol(struct r8152 *tp, u32 wol= opts) =20 static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) { - u32 ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); - /* MAC clock speed down */ if (enable) - ocp_data |=3D MAC_CLK_SPDWN_EN; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, + MAC_CLK_SPDWN_EN); else - ocp_data &=3D ~MAC_CLK_SPDWN_EN; - - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, + MAC_CLK_SPDWN_EN); } =20 static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) { - u32 ocp_data; - /* MAC clock speed down */ if (enable) { /* aldps_spdwn_ratio, tp10_spdwn_ratio */ - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, - 0x0403); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0x0403); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); - ocp_data &=3D ~EEE_SPDWN_RATIO_MASK; - ocp_data |=3D MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, + EEE_SPDWN_RATIO_MASK, MAC_CLK_SPDWN_EN | 0x03); } else { - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); - ocp_data &=3D ~MAC_CLK_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, + MAC_CLK_SPDWN_EN); } } =20 @@ -3549,27 +3565,20 @@ static void r8153_u1u2en(struct r8152 *tp, bool ena= ble) =20 static void r8153b_u1u2en(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); if (enable) - ocp_data |=3D LPM_U1U2_EN; + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_LPM_CONFIG, + LPM_U1U2_EN); else - ocp_data &=3D ~LPM_U1U2_EN; - - ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_LPM_CONFIG, + LPM_U1U2_EN); } =20 static void r8153_u2p3en(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); if (enable) - ocp_data |=3D U2P3_ENABLE; + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE); else - ocp_data &=3D ~U2P3_ENABLE; - ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, U2P3_ENABLE); } =20 static void r8153b_ups_flags(struct r8152 *tp) @@ -3784,24 +3793,20 @@ static u16 r8153_phy_status(struct r8152 *tp, u16 d= esired) =20 static void r8153b_ups_en(struct r8152 *tp, bool enable) { - u32 ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); - if (enable) { r8153b_ups_flags(tp); =20 - ocp_data |=3D UPS_EN | USP_PREWAKE | PHASE2_EN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE | PHASE2_EN); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); - ocp_data |=3D UPS_FORCE_PWR_DOWN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2, + UPS_FORCE_PWR_DOWN); } else { - ocp_data &=3D ~(UPS_EN | USP_PREWAKE); - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); - ocp_data &=3D ~UPS_FORCE_PWR_DOWN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, + UPS_FORCE_PWR_DOWN); =20 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { int i; @@ -3825,25 +3830,20 @@ static void r8153b_ups_en(struct r8152 *tp, bool en= able) =20 static void r8153c_ups_en(struct r8152 *tp, bool enable) { - u32 ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); - if (enable) { r8153b_ups_flags(tp); =20 - ocp_data |=3D UPS_EN | USP_PREWAKE | PHASE2_EN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE | PHASE2_EN); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); - ocp_data |=3D UPS_FORCE_PWR_DOWN; - ocp_data &=3D ~BIT(7); - ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); + ocp_byte_w0w1(tp, MCU_TYPE_USB, USB_MISC_2, BIT(7), + UPS_FORCE_PWR_DOWN); } else { - ocp_data &=3D ~(UPS_EN | USP_PREWAKE); - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); - ocp_data &=3D ~UPS_FORCE_PWR_DOWN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, + UPS_FORCE_PWR_DOWN); =20 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { int i; @@ -3865,9 +3865,7 @@ static void r8153c_ups_en(struct r8152 *tp, bool enab= le) =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); - ocp_data |=3D BIT(8); - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, BIT(8)); =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); } @@ -3875,35 +3873,30 @@ static void r8153c_ups_en(struct r8152 *tp, bool en= able) =20 static void r8156_ups_en(struct r8152 *tp, bool enable) { - u32 ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); - if (enable) { r8156_ups_flags(tp); =20 - ocp_data |=3D UPS_EN | USP_PREWAKE | PHASE2_EN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE | PHASE2_EN); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); - ocp_data |=3D UPS_FORCE_PWR_DOWN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_MISC_2, + UPS_FORCE_PWR_DOWN); =20 switch (tp->version) { case RTL_VER_13: case RTL_VER_15: - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); - ocp_data &=3D ~OOBS_POLLING; - ocp_write_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_UPHY_XTAL, + OOBS_POLLING); break; default: break; } } else { - ocp_data &=3D ~(UPS_EN | USP_PREWAKE); - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + UPS_EN | USP_PREWAKE); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); - ocp_data &=3D ~UPS_FORCE_PWR_DOWN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, + UPS_FORCE_PWR_DOWN); =20 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { tp->rtl_ops.hw_phy_cfg(tp); @@ -3916,54 +3909,38 @@ static void r8156_ups_en(struct r8152 *tp, bool ena= ble) =20 static void r8153_power_cut_en(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); if (enable) - ocp_data |=3D PWR_EN | PHASE2_EN; + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + PWR_EN | PHASE2_EN); else - ocp_data &=3D ~(PWR_EN | PHASE2_EN); - ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + PWR_EN | PHASE2_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); - ocp_data &=3D ~PCUT_STATUS; - ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); } =20 static void r8153b_power_cut_en(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); if (enable) - ocp_data |=3D PWR_EN | PHASE2_EN; + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, + PWR_EN | PHASE2_EN); else - ocp_data &=3D ~PWR_EN; - ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_POWER_CUT, PWR_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); - ocp_data &=3D ~PCUT_STATUS; - ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); } =20 static void r8153_queue_wake(struct r8152 *tp, bool enable) { - u32 ocp_data; - - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); if (enable) - ocp_data |=3D UPCOMING_RUNTIME_D3; + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, + UPCOMING_RUNTIME_D3); else - ocp_data &=3D ~UPCOMING_RUNTIME_D3; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, + UPCOMING_RUNTIME_D3); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); - ocp_data &=3D ~LINK_CHG_EVENT; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); - ocp_data &=3D ~LINK_CHANGE_FLAG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, LINK_CHG_EVENT); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, LINK_CHANGE_FLAG); } =20 static bool rtl_can_wakeup(struct r8152 *tp) @@ -3976,27 +3953,21 @@ static bool rtl_can_wakeup(struct r8152 *tp) static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) { if (enable) { - u32 ocp_data; - __rtl_set_wol(tp, WAKE_ANY); =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); - ocp_data |=3D LINK_OFF_WAKE_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, + LINK_OFF_WAKE_EN); =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); } else { - u32 ocp_data; - __rtl_set_wol(tp, tp->saved_wolopts); =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); - ocp_data &=3D ~LINK_OFF_WAKE_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, + LINK_OFF_WAKE_EN); =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); } @@ -4077,8 +4048,6 @@ static void rtl8156_runtime_enable(struct r8152 *tp, = bool enable) =20 static void r8153_teredo_off(struct r8152 *tp) { - u32 ocp_data; - switch (tp->version) { case RTL_VER_01: case RTL_VER_02: @@ -4087,10 +4056,9 @@ static void r8153_teredo_off(struct r8152 *tp) case RTL_VER_05: case RTL_VER_06: case RTL_VER_07: - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); - ocp_data &=3D ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | - OOB_TEREDO_EN); - ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, + TEREDO_SEL | TEREDO_RS_EVENT_MASK | + OOB_TEREDO_EN); break; =20 case RTL_VER_08: @@ -4117,13 +4085,10 @@ static void r8153_teredo_off(struct r8152 *tp) =20 static void rtl_reset_bmu(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); - ocp_data &=3D ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); - ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); - ocp_data |=3D BMU_RESET_EP_IN | BMU_RESET_EP_OUT; - ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, + BMU_RESET_EP_IN | BMU_RESET_EP_OUT); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_RESET, + BMU_RESET_EP_IN | BMU_RESET_EP_OUT); } =20 /* Clear the bp to stop the firmware before loading a new one */ @@ -4944,7 +4909,7 @@ static void rtl_ram_code_speed_up(struct r8152 *tp, s= truct fw_phy_speed_up *phy, return; =20 while (len) { - u32 ocp_data, size; + u32 size; int i; =20 if (len < 2048) @@ -4952,18 +4917,16 @@ static void rtl_ram_code_speed_up(struct r8152 *tp,= struct fw_phy_speed_up *phy, else size =3D 2048; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL); - ocp_data |=3D GPHY_PATCH_DONE | BACKUP_RESTRORE; - ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_GPHY_CTRL, + GPHY_PATCH_DONE | BACKUP_RESTRORE); =20 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_= TYPE_USB); =20 data +=3D size; len -=3D size; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); - ocp_data |=3D POL_GPHY_PATCH; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, + POL_GPHY_PATCH); =20 for (i =3D 0; i < 1000; i++) { if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PAT= CH)) @@ -5337,21 +5300,21 @@ static void r8152_mmd_write(struct r8152 *tp, u16 d= ev, u16 reg, u16 data) static void r8152_eee_en(struct r8152 *tp, bool enable) { u16 config1, config2, config3; - u32 ocp_data; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); config1 =3D ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; config2 =3D ocp_reg_read(tp, OCP_EEE_CONFIG2); config3 =3D ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; =20 if (enable) { - ocp_data |=3D EEE_RX_EN | EEE_TX_EN; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); config1 |=3D EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; config1 |=3D sd_rise_time(1); config2 |=3D RG_DACQUIET_EN | RG_LDVQUIET_EN; config3 |=3D fast_snr(42); } else { - ocp_data &=3D ~(EEE_RX_EN | EEE_TX_EN); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); config1 &=3D ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN); config1 |=3D sd_rise_time(7); @@ -5359,7 +5322,6 @@ static void r8152_eee_en(struct r8152 *tp, bool enabl= e) config3 |=3D fast_snr(511); } =20 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); @@ -5367,21 +5329,20 @@ static void r8152_eee_en(struct r8152 *tp, bool ena= ble) =20 static void r8153_eee_en(struct r8152 *tp, bool enable) { - u32 ocp_data; u16 config; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); config =3D ocp_reg_read(tp, OCP_EEE_CFG); =20 if (enable) { - ocp_data |=3D EEE_RX_EN | EEE_TX_EN; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); config |=3D EEE10_EN; } else { - ocp_data &=3D ~(EEE_RX_EN | EEE_TX_EN); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, + EEE_RX_EN | EEE_TX_EN); config &=3D ~EEE10_EN; } =20 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); ocp_reg_write(tp, OCP_EEE_CFG, config); =20 tp->ups_info.eee =3D enable; @@ -5512,30 +5473,20 @@ static void r8156b_wait_loading_flash(struct r8152 = *tp) =20 static void r8152b_exit_oob(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data &=3D ~RCR_ACPT_ALL; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); =20 rxdy_gated_en(tp, true); r8153_teredo_off(tp); ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data &=3D ~NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data &=3D ~MCU_BORW_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 wait_oob_link_list_ready(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data |=3D RE_INIT_LL; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); =20 wait_oob_link_list_ready(tp); =20 @@ -5571,18 +5522,12 @@ static void r8152b_exit_oob(struct r8152 *tp) =20 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); - ocp_data |=3D TCR0_AUTO_FIFO; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_TCR0, TCR0_AUTO_FIFO); } =20 static void r8152b_enter_oob(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data &=3D ~NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); @@ -5592,9 +5537,7 @@ static void r8152b_enter_oob(struct r8152 *tp) =20 wait_oob_link_list_ready(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data |=3D RE_INIT_LL; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); =20 wait_oob_link_list_ready(tp); =20 @@ -5602,19 +5545,15 @@ static void r8152b_enter_oob(struct r8152 *tp) =20 rtl_rx_vlan_en(tp, true); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); - ocp_data |=3D ALDPS_PROXY_MODE; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data |=3D NOW_IS_OOB | DIS_MCU_CLROOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, + NOW_IS_OOB | DIS_MCU_CLROOB); =20 rxdy_gated_en(tp, false); =20 - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data |=3D RCR_APM | RCR_AM | RCR_AB; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR, + RCR_APM | RCR_AM | RCR_AB); } =20 static int r8153_pre_firmware_1(struct r8152 *tp) @@ -5649,27 +5588,18 @@ static int r8153_post_firmware_1(struct r8152 *tp) =20 static int r8153_pre_firmware_2(struct r8152 *tp) { - u32 ocp_data; - r8153_pre_firmware_1(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); - ocp_data &=3D ~FW_FIX_SUSPEND; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, FW_FIX_SUSPEND); =20 return 0; } =20 static int r8153_post_firmware_2(struct r8152 *tp) { - u32 ocp_data; - /* enable bp0 if support USB_SPEED_SUPER only */ - if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) { - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); - ocp_data |=3D BIT(0); - ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); - } + if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BP_EN, BIT(0)); =20 /* reset UPHY timer to 36 ms */ ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); @@ -5677,28 +5607,20 @@ static int r8153_post_firmware_2(struct r8152 *tp) /* enable U3P3 check, set the counter to 4 */ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); - ocp_data |=3D FW_FIX_SUSPEND; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, FW_FIX_SUSPEND); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); - ocp_data |=3D USB2PHY_L1 | USB2PHY_SUSPEND; - ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY, + USB2PHY_L1 | USB2PHY_SUSPEND); =20 return 0; } =20 static int r8153_post_firmware_3(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); - ocp_data |=3D USB2PHY_L1 | USB2PHY_SUSPEND; - ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY, + USB2PHY_L1 | USB2PHY_SUSPEND); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); - ocp_data |=3D FW_IP_RESET_EN; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN); =20 return 0; } @@ -5718,49 +5640,30 @@ static int r8153b_post_firmware_1(struct r8152 *tp) =20 /* enable bp0 for RTL8153-BND */ ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); - if (ocp_data & BND_MASK) { - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); - ocp_data |=3D BIT(0); - ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); - } + if (ocp_data & BND_MASK) + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BP_EN, BIT(0)); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); - ocp_data |=3D FLOW_CTRL_PATCH_OPT; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, FLOW_CTRL_PATCH_OPT); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); - ocp_data |=3D FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); - ocp_data |=3D FW_IP_RESET_EN; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN); =20 return 0; } =20 static int r8153c_post_firmware_1(struct r8152 *tp) { - u32 ocp_data; + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, FLOW_CTRL_PATCH_2); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); - ocp_data |=3D FLOW_CTRL_PATCH_2; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); - ocp_data |=3D FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); =20 return 0; } =20 static int r8156a_post_firmware_1(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); - ocp_data |=3D FW_IP_RESET_EN; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, FW_IP_RESET_EN); =20 /* Modify U3PHY parameter for compatibility issue */ ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); @@ -5796,7 +5699,6 @@ static void r8153_aldps_en(struct r8152 *tp, bool ena= ble) =20 static void r8153_hw_phy_cfg(struct r8152 *tp) { - u32 ocp_data; u16 data; =20 /* disable ALDPS before updating the PHY parameters */ @@ -5823,11 +5725,10 @@ static void r8153_hw_phy_cfg(struct r8152 *tp) data =3D ocp_reg_read(tp, OCP_POWER_CFG); data |=3D EN_10M_PLLOFF; ocp_reg_write(tp, OCP_POWER_CFG, data); + sram_write(tp, SRAM_IMPEDANCE, 0x0b13); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); - ocp_data |=3D PFM_PWM_SWITCH; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); =20 /* Enable LPF corner auto tune */ sram_write(tp, SRAM_LPF_CFG, 0xf70f); @@ -5873,11 +5774,7 @@ static void r8153b_hw_phy_cfg(struct r8152 *tp) u32 ocp_data; u16 data; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); - if (ocp_data & PCUT_STATUS) { - ocp_data &=3D ~PCUT_STATUS; - ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); - } + ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); =20 /* disable ALDPS before updating the PHY parameters */ r8153_aldps_en(tp, false); @@ -5934,14 +5831,11 @@ static void r8153b_hw_phy_cfg(struct r8152 *tp) u32 swr_cnt_1ms_ini; =20 swr_cnt_1ms_ini =3D (16000000 / ocp_data) & SAW_CNT_1MS_MASK; - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); - ocp_data =3D (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; - ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_UPS_CFG, SAW_CNT_1MS_MASK, + swr_cnt_1ms_ini); } =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); - ocp_data |=3D PFM_PWM_SWITCH; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); =20 /* Advnace EEE */ if (!rtl_phy_patch_request(tp, true, true)) { @@ -5988,31 +5882,21 @@ static void rtl8153_change_mtu(struct r8152 *tp) =20 static void r8153_first_init(struct r8152 *tp) { - u32 ocp_data; - rxdy_gated_en(tp, true); r8153_teredo_off(tp); =20 - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data &=3D ~RCR_ACPT_ALL; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); =20 rtl8152_nic_reset(tp); rtl_reset_bmu(tp); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data &=3D ~NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data &=3D ~MCU_BORW_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 wait_oob_link_list_ready(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data |=3D RE_INIT_LL; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); =20 wait_oob_link_list_ready(tp); =20 @@ -6020,9 +5904,7 @@ static void r8153_first_init(struct r8152 *tp) =20 rtl8153_change_mtu(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); - ocp_data |=3D TCR0_AUTO_FIFO; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_TCR0, TCR0_AUTO_FIFO); =20 rtl8152_nic_reset(tp); =20 @@ -6036,11 +5918,7 @@ static void r8153_first_init(struct r8152 *tp) =20 static void r8153_enter_oob(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data &=3D ~NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 /* RX FIFO settings for OOB */ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); @@ -6052,9 +5930,7 @@ static void r8153_enter_oob(struct r8152 *tp) =20 wait_oob_link_list_ready(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data |=3D RE_INIT_LL; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); =20 wait_oob_link_list_ready(tp); =20 @@ -6066,9 +5942,8 @@ static void r8153_enter_oob(struct r8152 *tp) case RTL_VER_04: case RTL_VER_05: case RTL_VER_06: - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); - ocp_data &=3D ~TEREDO_WAKE_MASK; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, + TEREDO_WAKE_MASK); break; =20 case RTL_VER_08: @@ -6087,23 +5962,17 @@ static void r8153_enter_oob(struct r8152 *tp) =20 rtl_rx_vlan_en(tp, true); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); - ocp_data |=3D ALDPS_PROXY_MODE; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_BDC_CR, ALDPS_PROXY_MODE); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data |=3D NOW_IS_OOB | DIS_MCU_CLROOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, + NOW_IS_OOB | DIS_MCU_CLROOB); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data |=3D MCU_BORW_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 rxdy_gated_en(tp, false); =20 - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data |=3D RCR_APM | RCR_AM | RCR_AB; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR, + RCR_APM | RCR_AM | RCR_AB); } =20 static void rtl8153_disable(struct r8152 *tp) @@ -6135,7 +6004,6 @@ static void r8156_fc_parameter(struct r8152 *tp) =20 static int rtl8156_enable(struct r8152 *tp) { - u32 ocp_data; u16 speed; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) @@ -6150,12 +6018,12 @@ static int rtl8156_enable(struct r8152 *tp) speed =3D rtl8152_get_speed(tp); rtl_set_ifg(tp, speed); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); if (speed & _2500bps) - ocp_data &=3D ~IDLE_SPDWN_EN; + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); else - ocp_data |=3D IDLE_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); =20 if (speed & _1000bps) ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); @@ -6164,21 +6032,15 @@ static int rtl8156_enable(struct r8152 *tp) =20 if (tp->udev->speed =3D=3D USB_SPEED_HIGH) { /* USB 0xb45e[3:0] l1_nyet_hird */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); - ocp_data &=3D ~0xf; if (is_flow_control(speed)) - ocp_data |=3D 0xf; + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf); else - ocp_data |=3D 0x1; - ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1); } =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); - ocp_data &=3D ~FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); usleep_range(1000, 2000); - ocp_data |=3D FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); =20 return rtl_enable(tp); } @@ -6193,7 +6055,6 @@ static void rtl8156_disable(struct r8152 *tp) =20 static int rtl8156b_enable(struct r8152 *tp) { - u32 ocp_data; u16 speed; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) @@ -6202,9 +6063,7 @@ static int rtl8156b_enable(struct r8152 *tp) set_tx_qlen(tp); rtl_set_eee_plus(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM); - ocp_data &=3D ~RX_AGGR_NUM_MASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, RX_AGGR_NUM_MASK); =20 r8153_set_rx_early_timeout(tp); r8153_set_rx_early_size(tp); @@ -6212,29 +6071,23 @@ static int rtl8156b_enable(struct r8152 *tp) speed =3D rtl8152_get_speed(tp); rtl_set_ifg(tp, speed); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); if (speed & _2500bps) - ocp_data &=3D ~IDLE_SPDWN_EN; + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); else - ocp_data |=3D IDLE_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + IDLE_SPDWN_EN); =20 if (tp->udev->speed =3D=3D USB_SPEED_HIGH) { - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); - ocp_data &=3D ~0xf; if (is_flow_control(speed)) - ocp_data |=3D 0xf; + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0xf); else - ocp_data |=3D 0x1; - ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_L1_CTRL, 0xf, 0x1); } =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); - ocp_data &=3D ~FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); usleep_range(1000, 2000); - ocp_data |=3D FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); =20 return rtl_enable(tp); } @@ -6405,8 +6258,6 @@ static void rtl8152_down(struct r8152 *tp) =20 static void rtl8153_up(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 @@ -6415,17 +6266,11 @@ static void rtl8153_up(struct r8152 *tp) r8153_aldps_en(tp, false); r8153_first_init(tp); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); - ocp_data |=3D LANWAKE_CLR_EN; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); - ocp_data &=3D ~LANWAKE_PIN; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, LANWAKE_PIN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1); - ocp_data &=3D ~DELAY_PHY_PWR_CHG; - ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SSPHYLINK1, DELAY_PHY_PWR_CHG); =20 r8153_aldps_en(tp, true); =20 @@ -6445,16 +6290,12 @@ static void rtl8153_up(struct r8152 *tp) =20 static void rtl8153_down(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { rtl_drop_queued_tx(tp); return; } =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); - ocp_data &=3D ~LANWAKE_CLR_EN; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN); =20 r8153_u1u2en(tp, false); r8153_u2p3en(tp, false); @@ -6466,8 +6307,6 @@ static void rtl8153_down(struct r8152 *tp) =20 static void rtl8153b_up(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 @@ -6478,9 +6317,8 @@ static void rtl8153b_up(struct r8152 *tp) r8153_first_init(tp); ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data &=3D ~PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 r8153_aldps_en(tp, true); =20 @@ -6490,16 +6328,13 @@ static void rtl8153b_up(struct r8152 *tp) =20 static void rtl8153b_down(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { rtl_drop_queued_tx(tp); return; } =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data |=3D PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 r8153b_u1u2en(tp, false); r8153_u2p3en(tp, false); @@ -6527,8 +6362,6 @@ static void rtl8153c_change_mtu(struct r8152 *tp) =20 static void rtl8153c_up(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 @@ -6539,26 +6372,18 @@ static void rtl8153c_up(struct r8152 *tp) rxdy_gated_en(tp, true); r8153_teredo_off(tp); =20 - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data &=3D ~RCR_ACPT_ALL; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); =20 rtl8152_nic_reset(tp); rtl_reset_bmu(tp); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data &=3D ~NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data &=3D ~MCU_BORW_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 wait_oob_link_list_ready(tp); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data |=3D RE_INIT_LL; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, RE_INIT_LL); =20 wait_oob_link_list_ready(tp); =20 @@ -6578,15 +6403,12 @@ static void rtl8153c_up(struct r8152 *tp) =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); - ocp_data |=3D BIT(8); - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG34, BIT(8)); =20 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data &=3D ~PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 r8153_aldps_en(tp, true); r8153b_u1u2en(tp, true); @@ -6608,8 +6430,6 @@ static void rtl8156_change_mtu(struct r8152 *tp) =20 static void rtl8156_up(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 @@ -6620,20 +6440,14 @@ static void rtl8156_up(struct r8152 *tp) rxdy_gated_en(tp, true); r8153_teredo_off(tp); =20 - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data &=3D ~RCR_ACPT_ALL; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, RCR_ACPT_ALL); =20 rtl8152_nic_reset(tp); rtl_reset_bmu(tp); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data &=3D ~NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data &=3D ~MCU_BORW_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); =20 @@ -6643,27 +6457,21 @@ static void rtl8156_up(struct r8152 *tp) case RTL_TEST_01: case RTL_VER_10: case RTL_VER_11: - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG); - ocp_data |=3D ACT_ODMA; - ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); break; default: break; } =20 /* share FIFO settings */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL); - ocp_data &=3D ~RXFIFO_FULL_MASK; - ocp_data |=3D 0x08; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, RXFIFO_FULL_MASK, + 0x08); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data &=3D ~PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION); - ocp_data &=3D ~(RG_PWRDN_EN | ALL_SPEED_OFF); - ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_SPEED_OPTION, + RG_PWRDN_EN | ALL_SPEED_OFF); =20 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); =20 @@ -6681,25 +6489,20 @@ static void rtl8156_up(struct r8152 *tp) =20 static void rtl8156_down(struct r8152 *tp) { - u32 ocp_data; - if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { rtl_drop_queued_tx(tp); return; } =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data |=3D PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 r8153b_u1u2en(tp, false); r8153_u2p3en(tp, false); r8153b_power_cut_en(tp, false); r8153_aldps_en(tp, false); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data &=3D ~NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 /* RX FIFO settings for OOB */ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16); @@ -6718,20 +6521,15 @@ static void rtl8156_down(struct r8152 *tp) */ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); - ocp_data |=3D NOW_IS_OOB; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, NOW_IS_OOB); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); - ocp_data |=3D MCU_BORW_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, MCU_BORW_EN); =20 rtl_rx_vlan_en(tp, true); rxdy_gated_en(tp, false); =20 - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data |=3D RCR_APM | RCR_AM | RCR_AB; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_dword_set_bits(tp, MCU_TYPE_PLA, PLA_RCR, + RCR_APM | RCR_AM | RCR_AB); =20 r8153_aldps_en(tp, true); } @@ -7008,11 +6806,7 @@ static int rtl8152_close(struct net_device *netdev) =20 static void rtl_tally_reset(struct r8152 *tp) { - u32 ocp_data; - - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); - ocp_data |=3D TALLY_RESET; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_RSTTALLY, TALLY_RESET); } =20 static void r8152b_init(struct r8152 *tp) @@ -7031,21 +6825,18 @@ static void r8152b_init(struct r8152 *tp) =20 r8152_aldps_en(tp, false); =20 - if (tp->version =3D=3D RTL_VER_01) { - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); - ocp_data &=3D ~LED_MODE_MASK; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); - } + if (tp->version =3D=3D RTL_VER_01) + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, + LED_MODE_MASK); =20 r8152_power_cut_en(tp, false); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); - ocp_data |=3D TX_10M_IDLE_EN | PFM_PWM_SWITCH; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); - ocp_data =3D ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); - ocp_data &=3D ~MCU_CLK_RATIO_MASK; - ocp_data |=3D MCU_CLK_RATIO | D3_CLK_GATED_EN; - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, + TX_10M_IDLE_EN | PFM_PWM_SWITCH); + + ocp_dword_w0w1(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, MCU_CLK_RATIO_MASK, + MCU_CLK_RATIO | D3_CLK_GATED_EN); + ocp_data =3D GPHY_STS_MSK | SPEED_DOWN_MSK | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); @@ -7053,9 +6844,8 @@ static void r8152b_init(struct r8152 *tp) rtl_tally_reset(tp); =20 /* enable rx aggregation */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &=3D ~(RX_AGG_DISABLE | RX_ZERO_EN); - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); } =20 static void r8153_init(struct r8152 *tp) @@ -7096,55 +6886,43 @@ static void r8153_init(struct r8152 *tp) r8153_u2p3en(tp, false); =20 if (tp->version =3D=3D RTL_VER_04) { - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); - ocp_data &=3D ~pwd_dn_scale_mask; - ocp_data |=3D pwd_dn_scale(96); - ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); - - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); - ocp_data |=3D USB2PHY_L1 | USB2PHY_SUSPEND; - ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_SSPHYLINK2, + pwd_dn_scale_mask, pwd_dn_scale(96)); + + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_USB2PHY, + USB2PHY_L1 | USB2PHY_SUSPEND); } else if (tp->version =3D=3D RTL_VER_05) { - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); - ocp_data &=3D ~ECM_ALDPS; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ECM_ALDPS); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) =3D=3D 0) - ocp_data &=3D ~DYNAMIC_BURST; + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, + DYNAMIC_BURST); else - ocp_data |=3D DYNAMIC_BURST; - ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, + DYNAMIC_BURST); } else if (tp->version =3D=3D RTL_VER_06) { - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) =3D=3D 0) - ocp_data &=3D ~DYNAMIC_BURST; + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, + DYNAMIC_BURST); else - ocp_data |=3D DYNAMIC_BURST; - ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, + DYNAMIC_BURST); =20 r8153_queue_wake(tp, false); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); if (rtl8152_get_speed(tp) & LINK_STATUS) - ocp_data |=3D CUR_LINK_OK; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); else - ocp_data &=3D ~CUR_LINK_OK; - ocp_data |=3D POLL_LINK_CHG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK, POLL_LINK_CHG); } =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); - ocp_data |=3D EP4_FULL_FC; - ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, EP4_FULL_FC); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); - ocp_data &=3D ~TIMER11_EN; - ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_WDT11_CTRL, TIMER11_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); - ocp_data &=3D ~LED_MODE_MASK; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, LED_MODE_MASK); =20 ocp_data =3D FIFO_EMPTY_1FB | ROK_EXIT_LPM; if (tp->version =3D=3D RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) @@ -7153,10 +6931,8 @@ static void r8153_init(struct r8152 *tp) ocp_data |=3D LPM_TIMER_500US; ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); - ocp_data &=3D ~SEN_VAL_MASK; - ocp_data |=3D SEN_VAL_NORMAL | SEL_RXIDLE; - ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_AFE_CTRL2, SEN_VAL_MASK, + SEN_VAL_NORMAL | SEL_RXIDLE); =20 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); =20 @@ -7166,21 +6942,17 @@ static void r8153_init(struct r8152 *tp) r8153_u1u2en(tp, true); usb_enable_lpm(tp->udev); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); - ocp_data |=3D LANWAKE_CLR_EN; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_CONFIG6, LANWAKE_CLR_EN); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); - ocp_data &=3D ~LANWAKE_PIN; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, LANWAKE_PIN); =20 /* rx aggregation */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &=3D ~(RX_AGG_DISABLE | RX_ZERO_EN); if (tp->dell_tb_rx_agg_bug) - ocp_data |=3D RX_AGG_DISABLE; - - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_USB_CTRL, RX_ZERO_EN, + RX_AGG_DISABLE); + else + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); =20 rtl_tally_reset(tp); =20 @@ -7200,7 +6972,6 @@ static void r8153_init(struct r8152 *tp) =20 static void r8153b_init(struct r8152 *tp) { - u32 ocp_data; u16 data; int i; =20 @@ -7239,13 +7010,12 @@ static void r8153b_init(struct r8152 *tp) r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); if (rtl8152_get_speed(tp) & LINK_STATUS) - ocp_data |=3D CUR_LINK_OK; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); else - ocp_data &=3D ~CUR_LINK_OK; - ocp_data |=3D POLL_LINK_CHG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, + POLL_LINK_CHG); =20 if (tp->udev->speed >=3D USB_SPEED_SUPER) r8153b_u1u2en(tp, true); @@ -7255,25 +7025,20 @@ static void r8153b_init(struct r8152 *tp) /* MAC clock speed down */ r8153_mac_clk_speed_down(tp, true); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data &=3D ~PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 - if (tp->version =3D=3D RTL_VER_09) { + if (tp->version =3D=3D RTL_VER_09) /* Disable Test IO for 32QFN */ - if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); - ocp_data |=3D TEST_IO_OFF; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); - } - } + if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, + TEST_IO_OFF); =20 set_bit(GREEN_ETHERNET, &tp->flags); =20 /* rx aggregation */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &=3D ~(RX_AGG_DISABLE | RX_ZERO_EN); - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); =20 rtl_tally_reset(tp); =20 @@ -7282,7 +7047,6 @@ static void r8153b_init(struct r8152 *tp) =20 static void r8153c_init(struct r8152 *tp) { - u32 ocp_data; u16 data; int i; =20 @@ -7293,12 +7057,10 @@ static void r8153c_init(struct r8152 *tp) =20 /* Disable spi_en */ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); - ocp_data &=3D ~BIT(3); - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); - ocp_data |=3D BIT(1); - ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); + + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_CONFIG5, BIT(3)); + + ocp_word_set_bits(tp, MCU_TYPE_USB, 0xcbf0, BIT(1)); =20 for (i =3D 0; i < 500; i++) { if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & @@ -7330,14 +7092,12 @@ static void r8153c_init(struct r8152 *tp) r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); if (rtl8152_get_speed(tp) & LINK_STATUS) - ocp_data |=3D CUR_LINK_OK; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); else - ocp_data &=3D ~CUR_LINK_OK; - - ocp_data |=3D POLL_LINK_CHG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, + POLL_LINK_CHG); =20 r8153b_u1u2en(tp, true); =20 @@ -7346,16 +7106,13 @@ static void r8153c_init(struct r8152 *tp) /* MAC clock speed down */ r8153_mac_clk_speed_down(tp, true); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); - ocp_data &=3D ~BIT(7); - ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_MISC_2, BIT(7)); =20 set_bit(GREEN_ETHERNET, &tp->flags); =20 /* rx aggregation */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &=3D ~(RX_AGG_DISABLE | RX_ZERO_EN); - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); =20 rtl_tally_reset(tp); =20 @@ -7364,14 +7121,9 @@ static void r8153c_init(struct r8152 *tp) =20 static void r8156_hw_phy_cfg(struct r8152 *tp) { - u32 ocp_data; u16 data; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); - if (ocp_data & PCUT_STATUS) { - ocp_data &=3D ~PCUT_STATUS; - ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); - } + ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); =20 data =3D r8153_phy_status(tp, 0); switch (data) { @@ -7398,9 +7150,7 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); WARN_ON_ONCE(data !=3D PHY_STAT_LAN_ON); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); - ocp_data |=3D PFM_PWM_SWITCH; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); =20 switch (tp->version) { case RTL_VER_10: @@ -7561,9 +7311,8 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) /* EEE parameter */ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG); - ocp_data |=3D EN_XG_LIP | EN_G_LIP; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG, + EN_XG_LIP | EN_G_LIP); =20 sram_write(tp, 0x8257, 0x020f); /* XG PLL */ sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ @@ -7572,9 +7321,8 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) return; =20 /* Advance EEE */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); - ocp_data |=3D EEE_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, + EEE_SPDWN_EN); =20 data =3D ocp_reg_read(tp, OCP_DOWN_SPEED); data &=3D ~(EN_EEE_100 | EN_EEE_1000); @@ -7714,7 +7462,6 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) =20 static void r8156b_hw_phy_cfg(struct r8152 *tp) { - u32 ocp_data; u16 data; =20 switch (tp->version) { @@ -7744,11 +7491,7 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) break; } =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); - if (ocp_data & PCUT_STATUS) { - ocp_data &=3D ~PCUT_STATUS; - ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); - } + ocp_word_test_and_clr_bits(tp, MCU_TYPE_USB, USB_MISC_0, PCUT_STATUS); =20 data =3D r8153_phy_status(tp, 0); switch (data) { @@ -7785,9 +7528,7 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); WARN_ON_ONCE(data !=3D PHY_STAT_LAN_ON); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); - ocp_data |=3D PFM_PWM_SWITCH; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_PHY_PWR, PFM_PWM_SWITCH); =20 switch (tp->version) { case RTL_VER_12: @@ -7874,9 +7615,9 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) ocp_reg_write(tp, 0xb87c, 0x8fd8); ocp_reg_write(tp, 0xb87e, 0xf600); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG); - ocp_data |=3D EN_XG_LIP | EN_G_LIP; - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_PLA, PLA_USB_CFG, + EN_XG_LIP | EN_G_LIP); + ocp_reg_write(tp, 0xb87c, 0x813d); ocp_reg_write(tp, 0xb87e, 0x390e); ocp_reg_write(tp, 0xb87c, 0x814f); @@ -8090,9 +7831,7 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) if (rtl_phy_patch_request(tp, true, true)) return; =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); - ocp_data |=3D EEE_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); =20 data =3D ocp_reg_read(tp, OCP_DOWN_SPEED); data &=3D ~(EN_EEE_100 | EN_EEE_1000); @@ -8131,22 +7870,17 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) =20 static void r8156_init(struct r8152 *tp) { - u32 ocp_data; u16 data; int i; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); - ocp_data &=3D ~EN_ALL_SPEED; - ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); =20 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); - ocp_data |=3D BYPASS_MAC_RESET; - ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); =20 r8153b_u1u2en(tp, false); =20 @@ -8196,28 +7930,23 @@ static void r8156_init(struct r8152 *tp) =20 r8156_mac_clk_spd(tp, true); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data &=3D ~PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); if (rtl8152_get_speed(tp) & LINK_STATUS) - ocp_data |=3D CUR_LINK_OK; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); else - ocp_data &=3D ~CUR_LINK_OK; - ocp_data |=3D POLL_LINK_CHG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, + POLL_LINK_CHG); =20 set_bit(GREEN_ETHERNET, &tp->flags); =20 /* rx aggregation */ - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &=3D ~(RX_AGG_DISABLE | RX_ZERO_EN); - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_ZERO_EN); =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG); - ocp_data |=3D ACT_ODMA; - ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); + ocp_byte_set_bits(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ACT_ODMA); =20 r8156_mdio_force_mode(tp); rtl_tally_reset(tp); @@ -8227,26 +7956,19 @@ static void r8156_init(struct r8152 *tp) =20 static void r8156b_init(struct r8152 *tp) { - u32 ocp_data; u16 data; int i; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 - ocp_data =3D ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); - ocp_data &=3D ~EN_ALL_SPEED; - ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); + ocp_byte_clr_bits(tp, MCU_TYPE_USB, USB_ECM_OP, EN_ALL_SPEED); =20 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); - ocp_data |=3D BYPASS_MAC_RESET; - ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_ECM_OPTION, BYPASS_MAC_RESET); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); - ocp_data |=3D RX_DETECT8; - ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_U2P3_CTRL, RX_DETECT8); =20 r8153b_u1u2en(tp, false); =20 @@ -8306,48 +8028,39 @@ static void r8156b_init(struct r8152 *tp) =20 usb_enable_lpm(tp->udev); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR); - ocp_data &=3D ~SLOT_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_RCR, SLOT_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); - ocp_data |=3D FLOW_CTRL_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_CPCR, FLOW_CTRL_EN); =20 /* enable fc timer and set timer to 600 ms. */ ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, CTRL_TIMER_EN | (600 / 8)); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) - ocp_data |=3D FLOW_CTRL_PATCH_2; - ocp_data &=3D ~AUTO_SPEEDUP; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP, + FLOW_CTRL_PATCH_2); + else + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); - ocp_data |=3D FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); + ocp_word_set_bits(tp, MCU_TYPE_USB, USB_FW_TASK, FC_PATCH_TASK); =20 r8156_mac_clk_spd(tp, true); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data &=3D ~PLA_MCU_SPDWN_EN; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); + ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, + PLA_MCU_SPDWN_EN); =20 - ocp_data =3D ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); if (rtl8152_get_speed(tp) & LINK_STATUS) - ocp_data |=3D CUR_LINK_OK; + ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + CUR_LINK_OK | POLL_LINK_CHG); else - ocp_data &=3D ~CUR_LINK_OK; - ocp_data |=3D POLL_LINK_CHG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); + ocp_word_w0w1(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, CUR_LINK_OK, + POLL_LINK_CHG); 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Thu, 26 Mar 2026 15:39:35 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 26 Mar 2026 15:39:34 +0800 Received: from fc40.realtek.com.tw (172.22.241.7) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 26 Mar 2026 15:39:34 +0800 From: Chih Kai Hsu To: , CC: , , , , , , , Chih Kai Hsu Subject: [PATCH net-next v4 3/3] r8152: add helper functions for PHY OCP registers Date: Thu, 26 Mar 2026 15:39:25 +0800 Message-ID: <20260326073925.32976-456-nic_swsd@realtek.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260326073925.32976-453-nic_swsd@realtek.com> References: <20260326073925.32976-453-nic_swsd@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the following bitwise operation functions for PHY OCP registers to simplify the code. - ocp_reg_w0w1() - ocp_reg_clr_bits() - ocp_reg_set_bits() - sram_write_w0w1() - sram_clr_bits() - sram_set_bits() - r8152_mdio_clr_bit() - r8152_mdio_set_bit() - r8152_mdio_test_and_clr_bit() In addition, remove variable set but not used from r8153_init(), r8153b_init() and r8153c_init(). Signed-off-by: Chih Kai Hsu Reviewed-by: Hayes Wang --- drivers/net/usb/r8152.c | 697 +++++++++++++--------------------------- 1 file changed, 226 insertions(+), 471 deletions(-) diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c index 32a4e8d42311..8747c55e0a48 100644 --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c @@ -1726,6 +1726,71 @@ static void ocp_byte_set_bits(struct r8152 *tp, u16 = type, u16 index, u8 set) ocp_byte_w0w1(tp, type, index, 0, set); } =20 +static void ocp_reg_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set) +{ + u16 data; + + data =3D ocp_reg_read(tp, addr); + data =3D (data & ~clear) | set; + ocp_reg_write(tp, addr, data); +} + +static void ocp_reg_clr_bits(struct r8152 *tp, u16 addr, u16 clear) +{ + ocp_reg_w0w1(tp, addr, clear, 0); +} + +static void ocp_reg_set_bits(struct r8152 *tp, u16 addr, u16 set) +{ + ocp_reg_w0w1(tp, addr, 0, set); +} + +static void sram_write_w0w1(struct r8152 *tp, u16 addr, u16 clear, u16 set) +{ + u16 data; + + data =3D sram_read(tp, addr); + data =3D (data & ~clear) | set; + ocp_reg_write(tp, OCP_SRAM_DATA, data); +} + +static void sram_clr_bits(struct r8152 *tp, u16 addr, u16 clear) +{ + sram_write_w0w1(tp, addr, clear, 0); +} + +static void sram_set_bits(struct r8152 *tp, u16 addr, u16 set) +{ + sram_write_w0w1(tp, addr, 0, set); +} + +static void r8152_mdio_clr_bit(struct r8152 *tp, u16 addr, u16 clear) +{ + int data; + + data =3D r8152_mdio_read(tp, addr); + r8152_mdio_write(tp, addr, data & ~clear); +} + +static void r8152_mdio_set_bit(struct r8152 *tp, u16 addr, u16 set) +{ + int data; + + data =3D r8152_mdio_read(tp, addr); + r8152_mdio_write(tp, addr, data | set); +} + +static int r8152_mdio_test_and_clr_bit(struct r8152 *tp, u16 addr, u16 cle= ar) +{ + int data; + + data =3D r8152_mdio_read(tp, addr); + if (data & clear) + r8152_mdio_write(tp, addr, data & ~clear); + + return data & clear; +} + static int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); =20 @@ -3740,14 +3805,10 @@ static void r8156_ups_flags(struct r8152 *tp) =20 static void rtl_green_en(struct r8152 *tp, bool enable) { - u16 data; - - data =3D sram_read(tp, SRAM_GREEN_CFG); if (enable) - data |=3D GREEN_ETH_EN; + sram_set_bits(tp, SRAM_GREEN_CFG, GREEN_ETH_EN); else - data &=3D ~GREEN_ETH_EN; - sram_write(tp, SRAM_GREEN_CFG, data); + sram_clr_bits(tp, SRAM_GREEN_CFG, GREEN_ETH_EN); =20 tp->ups_info.green =3D enable; } @@ -4143,18 +4204,16 @@ static inline void rtl_reset_ocp_base(struct r8152 = *tp) =20 static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) { - u16 data, check; + u16 check; int i; =20 - data =3D ocp_reg_read(tp, OCP_PHY_PATCH_CMD); if (request) { - data |=3D PATCH_REQUEST; + ocp_reg_set_bits(tp, OCP_PHY_PATCH_CMD, PATCH_REQUEST); check =3D 0; } else { - data &=3D ~PATCH_REQUEST; + ocp_reg_clr_bits(tp, OCP_PHY_PATCH_CMD, PATCH_REQUEST); check =3D PATCH_READY; } - ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); =20 for (i =3D 0; wait && i < 5000; i++) { u32 ocp_data; @@ -4184,14 +4243,8 @@ static void rtl_patch_key_set(struct r8152 *tp, u16 = key_addr, u16 patch_key) sram_write(tp, key_addr, patch_key); sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); } else if (key_addr) { - u16 data; - sram_write(tp, 0x0000, 0x0000); - - data =3D ocp_reg_read(tp, OCP_PHY_LOCK); - data &=3D ~PATCH_LOCK; - ocp_reg_write(tp, OCP_PHY_LOCK, data); - + ocp_reg_clr_bits(tp, OCP_PHY_LOCK, PATCH_LOCK); sram_write(tp, key_addr, 0x0000); } else { WARN_ON_ONCE(1); @@ -5299,69 +5352,58 @@ static void r8152_mmd_write(struct r8152 *tp, u16 d= ev, u16 reg, u16 data) =20 static void r8152_eee_en(struct r8152 *tp, bool enable) { - u16 config1, config2, config3; - - config1 =3D ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; - config2 =3D ocp_reg_read(tp, OCP_EEE_CONFIG2); - config3 =3D ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; - if (enable) { ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, EEE_RX_EN | EEE_TX_EN); - config1 |=3D EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; - config1 |=3D sd_rise_time(1); - config2 |=3D RG_DACQUIET_EN | RG_LDVQUIET_EN; - config3 |=3D fast_snr(42); + + ocp_reg_w0w1(tp, OCP_EEE_CONFIG1, sd_rise_time_mask, + EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | + RX_QUIET_EN | sd_rise_time(1)); + + ocp_reg_set_bits(tp, OCP_EEE_CONFIG2, + RG_DACQUIET_EN | RG_LDVQUIET_EN); + + ocp_reg_w0w1(tp, OCP_EEE_CONFIG3, fast_snr_mask, fast_snr(42)); } else { ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, EEE_RX_EN | EEE_TX_EN); - config1 &=3D ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | - RX_QUIET_EN); - config1 |=3D sd_rise_time(7); - config2 &=3D ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); - config3 |=3D fast_snr(511); - } =20 - ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); - ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); - ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); + ocp_reg_w0w1(tp, OCP_EEE_CONFIG1, sd_rise_time_mask | + EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | + RX_QUIET_EN, sd_rise_time(7)); + + ocp_reg_clr_bits(tp, OCP_EEE_CONFIG2, + RG_DACQUIET_EN | RG_LDVQUIET_EN); + + ocp_reg_w0w1(tp, OCP_EEE_CONFIG3, fast_snr_mask, fast_snr(511)); + } } =20 static void r8153_eee_en(struct r8152 *tp, bool enable) { - u16 config; - - config =3D ocp_reg_read(tp, OCP_EEE_CFG); - if (enable) { ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, EEE_RX_EN | EEE_TX_EN); - config |=3D EEE10_EN; + + ocp_reg_set_bits(tp, OCP_EEE_CFG, EEE10_EN); } else { ocp_word_clr_bits(tp, MCU_TYPE_PLA, PLA_EEE_CR, EEE_RX_EN | EEE_TX_EN); - config &=3D ~EEE10_EN; - } =20 - ocp_reg_write(tp, OCP_EEE_CFG, config); + ocp_reg_clr_bits(tp, OCP_EEE_CFG, EEE10_EN); + } =20 tp->ups_info.eee =3D enable; } =20 static void r8156_eee_en(struct r8152 *tp, bool enable) { - u16 config; - r8153_eee_en(tp, enable); =20 - config =3D ocp_reg_read(tp, OCP_EEE_ADV2); - if (enable && (tp->eee_adv2 & MDIO_EEE_2_5GT)) - config |=3D MDIO_EEE_2_5GT; + ocp_reg_set_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); else - config &=3D ~MDIO_EEE_2_5GT; - - ocp_reg_write(tp, OCP_EEE_ADV2, config); + ocp_reg_clr_bits(tp, OCP_EEE_ADV2, MDIO_EEE_2_5GT); } =20 static void rtl_eee_enable(struct r8152 *tp, bool enable) @@ -5414,11 +5456,8 @@ static void rtl_eee_enable(struct r8152 *tp, bool en= able) =20 static void r8152b_enable_fc(struct r8152 *tp) { - u16 anar; - - anar =3D r8152_mdio_read(tp, MII_ADVERTISE); - anar |=3D ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; - r8152_mdio_write(tp, MII_ADVERTISE, anar); + r8152_mdio_set_bit(tp, MII_ADVERTISE, + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); =20 tp->ups_info.flow_control =3D true; } @@ -5674,17 +5713,12 @@ static int r8156a_post_firmware_1(struct r8152 *tp) =20 static void r8153_aldps_en(struct r8152 *tp, bool enable) { - u16 data; - - data =3D ocp_reg_read(tp, OCP_POWER_CFG); if (enable) { - data |=3D EN_ALDPS; - ocp_reg_write(tp, OCP_POWER_CFG, data); + ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_ALDPS); } else { int i; =20 - data &=3D ~EN_ALDPS; - ocp_reg_write(tp, OCP_POWER_CFG, data); + ocp_reg_clr_bits(tp, OCP_POWER_CFG, EN_ALDPS); for (i =3D 0; i < 20; i++) { if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; @@ -5699,8 +5733,6 @@ static void r8153_aldps_en(struct r8152 *tp, bool ena= ble) =20 static void r8153_hw_phy_cfg(struct r8152 *tp) { - u16 data; - /* disable ALDPS before updating the PHY parameters */ r8153_aldps_en(tp, false); =20 @@ -5709,22 +5741,14 @@ static void r8153_hw_phy_cfg(struct r8152 *tp) =20 rtl8152_apply_firmware(tp, false); =20 - if (tp->version =3D=3D RTL_VER_03) { - data =3D ocp_reg_read(tp, OCP_EEE_CFG); - data &=3D ~CTAP_SHORT_EN; - ocp_reg_write(tp, OCP_EEE_CFG, data); - } + if (tp->version =3D=3D RTL_VER_03) + ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN); + + ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); =20 - data =3D ocp_reg_read(tp, OCP_POWER_CFG); - data |=3D EEE_CLKDIV_EN; - ocp_reg_write(tp, OCP_POWER_CFG, data); + ocp_reg_set_bits(tp, OCP_DOWN_SPEED, EN_10M_BGOFF); =20 - data =3D ocp_reg_read(tp, OCP_DOWN_SPEED); - data |=3D EN_10M_BGOFF; - ocp_reg_write(tp, OCP_DOWN_SPEED, data); - data =3D ocp_reg_read(tp, OCP_POWER_CFG); - data |=3D EN_10M_PLLOFF; - ocp_reg_write(tp, OCP_POWER_CFG, data); + ocp_reg_set_bits(tp, OCP_POWER_CFG, EN_10M_PLLOFF); =20 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); =20 @@ -5792,9 +5816,7 @@ static void r8153b_hw_phy_cfg(struct r8152 *tp) case PHY_STAT_EXT_INIT: rtl8152_apply_firmware(tp, true); =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); + r8152_mdio_clr_bit(tp, MII_BMCR, BMCR_PDOWN); break; case PHY_STAT_LAN_ON: default: @@ -5804,12 +5826,9 @@ static void r8153b_hw_phy_cfg(struct r8152 *tp) =20 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); =20 - data =3D sram_read(tp, SRAM_GREEN_CFG); - data |=3D R_TUNE_EN; - sram_write(tp, SRAM_GREEN_CFG, data); - data =3D ocp_reg_read(tp, OCP_NCTL_CFG); - data |=3D PGA_RETURN_EN; - ocp_reg_write(tp, OCP_NCTL_CFG, data); + sram_set_bits(tp, SRAM_GREEN_CFG, R_TUNE_EN); + + ocp_reg_set_bits(tp, OCP_NCTL_CFG, PGA_RETURN_EN); =20 /* ADC Bias Calibration: * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake @@ -5839,14 +5858,11 @@ static void r8153b_hw_phy_cfg(struct r8152 *tp) =20 /* Advnace EEE */ if (!rtl_phy_patch_request(tp, true, true)) { - data =3D ocp_reg_read(tp, OCP_POWER_CFG); - data |=3D EEE_CLKDIV_EN; - ocp_reg_write(tp, OCP_POWER_CFG, data); + ocp_reg_set_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); tp->ups_info.eee_ckdiv =3D true; =20 - data =3D ocp_reg_read(tp, OCP_DOWN_SPEED); - data |=3D EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; - ocp_reg_write(tp, OCP_DOWN_SPEED, data); + ocp_reg_set_bits(tp, OCP_DOWN_SPEED, + EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV); tp->ups_info.eee_cmod_lv =3D true; tp->ups_info._10m_ckdiv =3D true; tp->ups_info.eee_plloff_giga =3D true; @@ -6812,16 +6828,11 @@ static void rtl_tally_reset(struct r8152 *tp) static void r8152b_init(struct r8152 *tp) { u32 ocp_data; - u16 data; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) return; =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 r8152_aldps_en(tp, false); =20 @@ -6851,7 +6862,6 @@ static void r8152b_init(struct r8152 *tp) static void r8153_init(struct r8152 *tp) { u32 ocp_data; - u16 data; int i; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) @@ -6869,19 +6879,15 @@ static void r8153_init(struct r8152 *tp) break; } =20 - data =3D r8153_phy_status(tp, 0); + r8153_phy_status(tp, 0); =20 if (tp->version =3D=3D RTL_VER_03 || tp->version =3D=3D RTL_VER_04 || tp->version =3D=3D RTL_VER_05) ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 - data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); + r8153_phy_status(tp, PHY_STAT_LAN_ON); =20 r8153_u2p3en(tp, false); =20 @@ -6972,7 +6978,6 @@ static void r8153_init(struct r8152 *tp) =20 static void r8153b_init(struct r8152 *tp) { - u16 data; int i; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) @@ -6990,15 +6995,11 @@ static void r8153b_init(struct r8152 *tp) break; } =20 - data =3D r8153_phy_status(tp, 0); + r8153_phy_status(tp, 0); =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 - data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); + r8153_phy_status(tp, PHY_STAT_LAN_ON); =20 r8153_u2p3en(tp, false); =20 @@ -7047,7 +7048,6 @@ static void r8153b_init(struct r8152 *tp) =20 static void r8153c_init(struct r8152 *tp) { - u16 data; int i; =20 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) @@ -7072,15 +7072,11 @@ static void r8153c_init(struct r8152 *tp) return; } =20 - data =3D r8153_phy_status(tp, 0); + r8153_phy_status(tp, 0); =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 - data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); + r8153_phy_status(tp, PHY_STAT_LAN_ON); =20 r8153_u2p3en(tp, false); =20 @@ -7130,9 +7126,7 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) case PHY_STAT_EXT_INIT: rtl8152_apply_firmware(tp, true); =20 - data =3D ocp_reg_read(tp, 0xa468); - data &=3D ~(BIT(3) | BIT(1)); - ocp_reg_write(tp, 0xa468, data); + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); break; case PHY_STAT_LAN_ON: case PHY_STAT_PWRDN: @@ -7154,153 +7148,57 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) =20 switch (tp->version) { case RTL_VER_10: - data =3D ocp_reg_read(tp, 0xad40); - data &=3D ~0x3ff; - data |=3D BIT(7) | BIT(2); - ocp_reg_write(tp, 0xad40, data); - - data =3D ocp_reg_read(tp, 0xad4e); - data |=3D BIT(4); - ocp_reg_write(tp, 0xad4e, data); - data =3D ocp_reg_read(tp, 0xad16); - data &=3D ~0x3ff; - data |=3D 0x6; - ocp_reg_write(tp, 0xad16, data); - data =3D ocp_reg_read(tp, 0xad32); - data &=3D ~0x3f; - data |=3D 6; - ocp_reg_write(tp, 0xad32, data); - data =3D ocp_reg_read(tp, 0xac08); - data &=3D ~(BIT(12) | BIT(8)); - ocp_reg_write(tp, 0xac08, data); - data =3D ocp_reg_read(tp, 0xac8a); - data |=3D BIT(12) | BIT(13) | BIT(14); - data &=3D ~BIT(15); - ocp_reg_write(tp, 0xac8a, data); - data =3D ocp_reg_read(tp, 0xad18); - data |=3D BIT(10); - ocp_reg_write(tp, 0xad18, data); - data =3D ocp_reg_read(tp, 0xad1a); - data |=3D 0x3ff; - ocp_reg_write(tp, 0xad1a, data); - data =3D ocp_reg_read(tp, 0xad1c); - data |=3D 0x3ff; - ocp_reg_write(tp, 0xad1c, data); - - data =3D sram_read(tp, 0x80ea); - data &=3D ~0xff00; - data |=3D 0xc400; - sram_write(tp, 0x80ea, data); - data =3D sram_read(tp, 0x80eb); - data &=3D ~0x0700; - data |=3D 0x0300; - sram_write(tp, 0x80eb, data); - data =3D sram_read(tp, 0x80f8); - data &=3D ~0xff00; - data |=3D 0x1c00; - sram_write(tp, 0x80f8, data); - data =3D sram_read(tp, 0x80f1); - data &=3D ~0xff00; - data |=3D 0x3000; - sram_write(tp, 0x80f1, data); - - data =3D sram_read(tp, 0x80fe); - data &=3D ~0xff00; - data |=3D 0xa500; - sram_write(tp, 0x80fe, data); - data =3D sram_read(tp, 0x8102); - data &=3D ~0xff00; - data |=3D 0x5000; - sram_write(tp, 0x8102, data); - data =3D sram_read(tp, 0x8015); - data &=3D ~0xff00; - data |=3D 0x3300; - sram_write(tp, 0x8015, data); - data =3D sram_read(tp, 0x8100); - data &=3D ~0xff00; - data |=3D 0x7000; - sram_write(tp, 0x8100, data); - data =3D sram_read(tp, 0x8014); - data &=3D ~0xff00; - data |=3D 0xf000; - sram_write(tp, 0x8014, data); - data =3D sram_read(tp, 0x8016); - data &=3D ~0xff00; - data |=3D 0x6500; - sram_write(tp, 0x8016, data); - data =3D sram_read(tp, 0x80dc); - data &=3D ~0xff00; - data |=3D 0xed00; - sram_write(tp, 0x80dc, data); - data =3D sram_read(tp, 0x80df); - data |=3D BIT(8); - sram_write(tp, 0x80df, data); - data =3D sram_read(tp, 0x80e1); - data &=3D ~BIT(8); - sram_write(tp, 0x80e1, data); - - data =3D ocp_reg_read(tp, 0xbf06); - data &=3D ~0x003f; - data |=3D 0x0038; - ocp_reg_write(tp, 0xbf06, data); + ocp_reg_w0w1(tp, 0xad40, 0x3ff, BIT(7) | BIT(2)); + + ocp_reg_set_bits(tp, 0xad4e, BIT(4)); + ocp_reg_w0w1(tp, 0xad16, 0x3ff, 0x6); + ocp_reg_w0w1(tp, 0xad32, 0x3f, 0x6); + ocp_reg_clr_bits(tp, 0xac08, BIT(12) | BIT(8)); + ocp_reg_w0w1(tp, 0xac8a, BIT(15), BIT(12) | BIT(13) | BIT(14)); + ocp_reg_set_bits(tp, 0xad18, BIT(10)); + ocp_reg_set_bits(tp, 0xad1a, 0x3ff); + ocp_reg_set_bits(tp, 0xad1c, 0x3ff); + + sram_write_w0w1(tp, 0x80ea, 0xff00, 0xc400); + sram_write_w0w1(tp, 0x80eb, 0x0700, 0x0300); + sram_write_w0w1(tp, 0x80f8, 0xff00, 0x1c00); + sram_write_w0w1(tp, 0x80f1, 0xff00, 0x3000); + + sram_write_w0w1(tp, 0x80fe, 0xff00, 0xa500); + sram_write_w0w1(tp, 0x8102, 0xff00, 0x5000); + sram_write_w0w1(tp, 0x8015, 0xff00, 0x3300); + sram_write_w0w1(tp, 0x8100, 0xff00, 0x7000); + sram_write_w0w1(tp, 0x8014, 0xff00, 0xf000); + sram_write_w0w1(tp, 0x8016, 0xff00, 0x6500); + sram_write_w0w1(tp, 0x80dc, 0xff00, 0xed00); + sram_set_bits(tp, 0x80df, BIT(8)); + sram_clr_bits(tp, 0x80e1, BIT(8)); + + ocp_reg_w0w1(tp, 0xbf06, 0x003f, 0x0038); =20 sram_write(tp, 0x819f, 0xddb6); =20 ocp_reg_write(tp, 0xbc34, 0x5555); - data =3D ocp_reg_read(tp, 0xbf0a); - data &=3D ~0x0e00; - data |=3D 0x0a00; - ocp_reg_write(tp, 0xbf0a, data); + ocp_reg_w0w1(tp, 0xbf0a, 0x0e00, 0x0a00); =20 - data =3D ocp_reg_read(tp, 0xbd2c); - data &=3D ~BIT(13); - ocp_reg_write(tp, 0xbd2c, data); + ocp_reg_clr_bits(tp, 0xbd2c, BIT(13)); break; case RTL_VER_11: - data =3D ocp_reg_read(tp, 0xad16); - data |=3D 0x3ff; - ocp_reg_write(tp, 0xad16, data); - data =3D ocp_reg_read(tp, 0xad32); - data &=3D ~0x3f; - data |=3D 6; - ocp_reg_write(tp, 0xad32, data); - data =3D ocp_reg_read(tp, 0xac08); - data &=3D ~(BIT(12) | BIT(8)); - ocp_reg_write(tp, 0xac08, data); - data =3D ocp_reg_read(tp, 0xacc0); - data &=3D ~0x3; - data |=3D BIT(1); - ocp_reg_write(tp, 0xacc0, data); - data =3D ocp_reg_read(tp, 0xad40); - data &=3D ~0xe7; - data |=3D BIT(6) | BIT(2); - ocp_reg_write(tp, 0xad40, data); - data =3D ocp_reg_read(tp, 0xac14); - data &=3D ~BIT(7); - ocp_reg_write(tp, 0xac14, data); - data =3D ocp_reg_read(tp, 0xac80); - data &=3D ~(BIT(8) | BIT(9)); - ocp_reg_write(tp, 0xac80, data); - data =3D ocp_reg_read(tp, 0xac5e); - data &=3D ~0x7; - data |=3D BIT(1); - ocp_reg_write(tp, 0xac5e, data); + ocp_reg_set_bits(tp, 0xad16, 0x3ff); + ocp_reg_w0w1(tp, 0xad32, 0x3f, 0x6); + ocp_reg_clr_bits(tp, 0xac08, BIT(12) | BIT(8)); + ocp_reg_w0w1(tp, 0xacc0, 0x3, BIT(1)); + ocp_reg_w0w1(tp, 0xad40, 0xe7, BIT(6) | BIT(2)); + ocp_reg_clr_bits(tp, 0xac14, BIT(7)); + ocp_reg_clr_bits(tp, 0xac80, BIT(8) | BIT(9)); + ocp_reg_w0w1(tp, 0xac5e, 0x7, BIT(1)); ocp_reg_write(tp, 0xad4c, 0x00a8); ocp_reg_write(tp, 0xac5c, 0x01ff); - data =3D ocp_reg_read(tp, 0xac8a); - data &=3D ~0xf0; - data |=3D BIT(4) | BIT(5); - ocp_reg_write(tp, 0xac8a, data); + ocp_reg_w0w1(tp, 0xac8a, 0xf0, BIT(4) | BIT(5)); ocp_reg_write(tp, 0xb87c, 0x8157); - data =3D ocp_reg_read(tp, 0xb87e); - data &=3D ~0xff00; - data |=3D 0x0500; - ocp_reg_write(tp, 0xb87e, data); + ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0500); ocp_reg_write(tp, 0xb87c, 0x8159); - data =3D ocp_reg_read(tp, 0xb87e); - data &=3D ~0xff00; - data |=3D 0x0700; - ocp_reg_write(tp, 0xb87e, data); + ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0700); =20 /* AAGC */ ocp_reg_write(tp, 0xb87c, 0x80a2); @@ -7324,17 +7222,13 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); =20 - data =3D ocp_reg_read(tp, OCP_DOWN_SPEED); - data &=3D ~(EN_EEE_100 | EN_EEE_1000); - data |=3D EN_10M_CLKDIV; - ocp_reg_write(tp, OCP_DOWN_SPEED, data); + ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, + EN_10M_CLKDIV); tp->ups_info._10m_ckdiv =3D true; tp->ups_info.eee_plloff_100 =3D false; tp->ups_info.eee_plloff_giga =3D false; =20 - data =3D ocp_reg_read(tp, OCP_POWER_CFG); - data &=3D ~EEE_CLKDIV_EN; - ocp_reg_write(tp, OCP_POWER_CFG, data); + ocp_reg_clr_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); tp->ups_info.eee_ckdiv =3D false; =20 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); @@ -7344,34 +7238,19 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) rtl_phy_patch_request(tp, false, true); =20 /* enable ADC Ibias Cal */ - data =3D ocp_reg_read(tp, 0xd068); - data |=3D BIT(13); - ocp_reg_write(tp, 0xd068, data); + ocp_reg_set_bits(tp, 0xd068, BIT(13)); =20 /* enable Thermal Sensor */ - data =3D sram_read(tp, 0x81a2); - data &=3D ~BIT(8); - sram_write(tp, 0x81a2, data); - data =3D ocp_reg_read(tp, 0xb54c); - data &=3D ~0xff00; - data |=3D 0xdb00; - ocp_reg_write(tp, 0xb54c, data); + sram_clr_bits(tp, 0x81a2, BIT(8)); + ocp_reg_w0w1(tp, 0xb54c, 0xff00, 0xdb00); =20 /* Nway 2.5G Lite */ - data =3D ocp_reg_read(tp, 0xa454); - data &=3D ~BIT(0); - ocp_reg_write(tp, 0xa454, data); + ocp_reg_clr_bits(tp, 0xa454, BIT(0)); =20 /* CS DSP solution */ - data =3D ocp_reg_read(tp, OCP_10GBT_CTRL); - data |=3D RTL_ADV2_5G_F_R; - ocp_reg_write(tp, OCP_10GBT_CTRL, data); - data =3D ocp_reg_read(tp, 0xad4e); - data &=3D ~BIT(4); - ocp_reg_write(tp, 0xad4e, data); - data =3D ocp_reg_read(tp, 0xa86a); - data &=3D ~BIT(0); - ocp_reg_write(tp, 0xa86a, data); + ocp_reg_set_bits(tp, OCP_10GBT_CTRL, RTL_ADV2_5G_F_R); + ocp_reg_clr_bits(tp, 0xad4e, BIT(4)); + ocp_reg_clr_bits(tp, 0xa86a, BIT(0)); =20 /* MDI SWAP */ if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) && @@ -7432,9 +7311,7 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) } =20 /* Notify the MAC when the speed is changed to force mode. */ - data =3D ocp_reg_read(tp, OCP_INTR_EN); - data |=3D INTR_SPEED_FORCE; - ocp_reg_write(tp, OCP_INTR_EN, data); + ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE); break; default: break; @@ -7442,12 +7319,8 @@ static void r8156_hw_phy_cfg(struct r8152 *tp) =20 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); =20 - data =3D ocp_reg_read(tp, 0xa428); - data &=3D ~BIT(9); - ocp_reg_write(tp, 0xa428, data); - data =3D ocp_reg_read(tp, 0xa5ea); - data &=3D ~BIT(0); - ocp_reg_write(tp, 0xa5ea, data); + ocp_reg_clr_bits(tp, 0xa428, BIT(9)); + ocp_reg_clr_bits(tp, 0xa5ea, BIT(0)); tp->ups_info.lite_mode =3D 0; =20 if (tp->eee_en) @@ -7467,21 +7340,12 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) switch (tp->version) { case RTL_VER_12: ocp_reg_write(tp, 0xbf86, 0x9000); - data =3D ocp_reg_read(tp, 0xc402); - data |=3D BIT(10); - ocp_reg_write(tp, 0xc402, data); - data &=3D ~BIT(10); - ocp_reg_write(tp, 0xc402, data); + ocp_reg_set_bits(tp, 0xc402, BIT(10)); + ocp_reg_clr_bits(tp, 0xc402, BIT(10)); ocp_reg_write(tp, 0xbd86, 0x1010); ocp_reg_write(tp, 0xbd88, 0x1010); - data =3D ocp_reg_read(tp, 0xbd4e); - data &=3D ~(BIT(10) | BIT(11)); - data |=3D BIT(11); - ocp_reg_write(tp, 0xbd4e, data); - data =3D ocp_reg_read(tp, 0xbf46); - data &=3D ~0xf00; - data |=3D 0x700; - ocp_reg_write(tp, 0xbf46, data); + ocp_reg_w0w1(tp, 0xbd4e, BIT(10) | BIT(11), BIT(11)); + ocp_reg_w0w1(tp, 0xbf46, 0xf00, 0x700); break; case RTL_VER_13: case RTL_VER_15: @@ -7498,13 +7362,8 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) case PHY_STAT_EXT_INIT: rtl8152_apply_firmware(tp, true); =20 - data =3D ocp_reg_read(tp, 0xa466); - data &=3D ~BIT(0); - ocp_reg_write(tp, 0xa466, data); - - data =3D ocp_reg_read(tp, 0xa468); - data &=3D ~(BIT(3) | BIT(1)); - ocp_reg_write(tp, 0xa468, data); + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); break; case PHY_STAT_LAN_ON: case PHY_STAT_PWRDN: @@ -7513,11 +7372,7 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) break; } =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 /* disable ALDPS before updating the PHY parameters */ r8153_aldps_en(tp, false); @@ -7532,21 +7387,12 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) =20 switch (tp->version) { case RTL_VER_12: - data =3D ocp_reg_read(tp, 0xbc08); - data |=3D BIT(3) | BIT(2); - ocp_reg_write(tp, 0xbc08, data); - - data =3D sram_read(tp, 0x8fff); - data &=3D ~0xff00; - data |=3D 0x0400; - sram_write(tp, 0x8fff, data); - - data =3D ocp_reg_read(tp, 0xacda); - data |=3D 0xff00; - ocp_reg_write(tp, 0xacda, data); - data =3D ocp_reg_read(tp, 0xacde); - data |=3D 0xf000; - ocp_reg_write(tp, 0xacde, data); + ocp_reg_set_bits(tp, 0xbc08, BIT(3) | BIT(2)); + + sram_write_w0w1(tp, 0x8fff, 0xff00, 0x0400); + + ocp_reg_set_bits(tp, 0xacda, 0xff00); + ocp_reg_set_bits(tp, 0xacde, 0xf000); ocp_reg_write(tp, 0xac8c, 0x0ffc); ocp_reg_write(tp, 0xac46, 0xb7b4); ocp_reg_write(tp, 0xac50, 0x0fbc); @@ -7624,21 +7470,15 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) ocp_reg_write(tp, 0xb87e, 0x790e); ocp_reg_write(tp, 0xb87c, 0x80b0); ocp_reg_write(tp, 0xb87e, 0x0f31); - data =3D ocp_reg_read(tp, 0xbf4c); - data |=3D BIT(1); - ocp_reg_write(tp, 0xbf4c, data); - data =3D ocp_reg_read(tp, 0xbcca); - data |=3D BIT(9) | BIT(8); - ocp_reg_write(tp, 0xbcca, data); + ocp_reg_set_bits(tp, 0xbf4c, BIT(1)); + ocp_reg_set_bits(tp, 0xbcca, BIT(9) | BIT(8)); ocp_reg_write(tp, 0xb87c, 0x8141); ocp_reg_write(tp, 0xb87e, 0x320e); ocp_reg_write(tp, 0xb87c, 0x8153); ocp_reg_write(tp, 0xb87e, 0x720e); ocp_reg_write(tp, 0xb87c, 0x8529); ocp_reg_write(tp, 0xb87e, 0x050e); - data =3D ocp_reg_read(tp, OCP_EEE_CFG); - data &=3D ~CTAP_SHORT_EN; - ocp_reg_write(tp, OCP_EEE_CFG, data); + ocp_reg_clr_bits(tp, OCP_EEE_CFG, CTAP_SHORT_EN); =20 sram_write(tp, 0x816c, 0xc4a0); sram_write(tp, 0x8170, 0xc4a0); @@ -7671,64 +7511,33 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) ocp_reg_write(tp, 0xb87c, 0x817b); ocp_reg_write(tp, 0xb87e, 0x1d0a); =20 - data =3D sram_read(tp, 0x8217); - data &=3D ~0xff00; - data |=3D 0x5000; - sram_write(tp, 0x8217, data); - data =3D sram_read(tp, 0x821a); - data &=3D ~0xff00; - data |=3D 0x5000; - sram_write(tp, 0x821a, data); + sram_write_w0w1(tp, 0x8217, 0xff00, 0x5000); + sram_write_w0w1(tp, 0x821a, 0xff00, 0x5000); sram_write(tp, 0x80da, 0x0403); - data =3D sram_read(tp, 0x80dc); - data &=3D ~0xff00; - data |=3D 0x1000; - sram_write(tp, 0x80dc, data); + sram_write_w0w1(tp, 0x80dc, 0xff00, 0x1000); sram_write(tp, 0x80b3, 0x0384); sram_write(tp, 0x80b7, 0x2007); - data =3D sram_read(tp, 0x80ba); - data &=3D ~0xff00; - data |=3D 0x6c00; - sram_write(tp, 0x80ba, data); + sram_write_w0w1(tp, 0x80ba, 0xff00, 0x6c00); sram_write(tp, 0x80b5, 0xf009); - data =3D sram_read(tp, 0x80bd); - data &=3D ~0xff00; - data |=3D 0x9f00; - sram_write(tp, 0x80bd, data); + sram_write_w0w1(tp, 0x80bd, 0xff00, 0x9f00); sram_write(tp, 0x80c7, 0xf083); sram_write(tp, 0x80dd, 0x03f0); - data =3D sram_read(tp, 0x80df); - data &=3D ~0xff00; - data |=3D 0x1000; - sram_write(tp, 0x80df, data); + sram_write_w0w1(tp, 0x80df, 0xff00, 0x1000); sram_write(tp, 0x80cb, 0x2007); - data =3D sram_read(tp, 0x80ce); - data &=3D ~0xff00; - data |=3D 0x6c00; - sram_write(tp, 0x80ce, data); + sram_write_w0w1(tp, 0x80ce, 0xff00, 0x6c00); sram_write(tp, 0x80c9, 0x8009); - data =3D sram_read(tp, 0x80d1); - data &=3D ~0xff00; - data |=3D 0x8000; - sram_write(tp, 0x80d1, data); + sram_write_w0w1(tp, 0x80d1, 0xff00, 0x8000); sram_write(tp, 0x80a3, 0x200a); sram_write(tp, 0x80a5, 0xf0ad); sram_write(tp, 0x809f, 0x6073); sram_write(tp, 0x80a1, 0x000b); - data =3D sram_read(tp, 0x80a9); - data &=3D ~0xff00; - data |=3D 0xc000; - sram_write(tp, 0x80a9, data); + sram_write_w0w1(tp, 0x80a9, 0xff00, 0xc000); =20 if (rtl_phy_patch_request(tp, true, true)) return; =20 - data =3D ocp_reg_read(tp, 0xb896); - data &=3D ~BIT(0); - ocp_reg_write(tp, 0xb896, data); - data =3D ocp_reg_read(tp, 0xb892); - data &=3D ~0xff00; - ocp_reg_write(tp, 0xb892, data); + ocp_reg_clr_bits(tp, 0xb896, BIT(0)); + ocp_reg_clr_bits(tp, 0xb892, 0xff00); ocp_reg_write(tp, 0xb88e, 0xc23e); ocp_reg_write(tp, 0xb890, 0x0000); ocp_reg_write(tp, 0xb88e, 0xc240); @@ -7743,41 +7552,25 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) ocp_reg_write(tp, 0xb890, 0x1012); ocp_reg_write(tp, 0xb88e, 0xc24a); ocp_reg_write(tp, 0xb890, 0x1416); - data =3D ocp_reg_read(tp, 0xb896); - data |=3D BIT(0); - ocp_reg_write(tp, 0xb896, data); + ocp_reg_set_bits(tp, 0xb896, BIT(0)); =20 rtl_phy_patch_request(tp, false, true); =20 - data =3D ocp_reg_read(tp, 0xa86a); - data |=3D BIT(0); - ocp_reg_write(tp, 0xa86a, data); - data =3D ocp_reg_read(tp, 0xa6f0); - data |=3D BIT(0); - ocp_reg_write(tp, 0xa6f0, data); + ocp_reg_set_bits(tp, 0xa86a, BIT(0)); + ocp_reg_set_bits(tp, 0xa6f0, BIT(0)); =20 ocp_reg_write(tp, 0xbfa0, 0xd70d); ocp_reg_write(tp, 0xbfa2, 0x4100); ocp_reg_write(tp, 0xbfa4, 0xe868); ocp_reg_write(tp, 0xbfa6, 0xdc59); ocp_reg_write(tp, 0xb54c, 0x3c18); - data =3D ocp_reg_read(tp, 0xbfa4); - data &=3D ~BIT(5); - ocp_reg_write(tp, 0xbfa4, data); - data =3D sram_read(tp, 0x817d); - data |=3D BIT(12); - sram_write(tp, 0x817d, data); + ocp_reg_clr_bits(tp, 0xbfa4, BIT(5)); + sram_set_bits(tp, 0x817d, BIT(12)); break; case RTL_VER_13: /* 2.5G INRX */ - data =3D ocp_reg_read(tp, 0xac46); - data &=3D ~0x00f0; - data |=3D 0x0090; - ocp_reg_write(tp, 0xac46, data); - data =3D ocp_reg_read(tp, 0xad30); - data &=3D ~0x0003; - data |=3D 0x0001; - ocp_reg_write(tp, 0xad30, data); + ocp_reg_w0w1(tp, 0xac46, 0x00f0, 0x0090); + ocp_reg_w0w1(tp, 0xad30, 0x0003, 0x0001); fallthrough; case RTL_VER_15: /* EEE parameter */ @@ -7786,20 +7579,11 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) ocp_reg_write(tp, 0xb87c, 0x8107); ocp_reg_write(tp, 0xb87e, 0x360e); ocp_reg_write(tp, 0xb87c, 0x8551); - data =3D ocp_reg_read(tp, 0xb87e); - data &=3D ~0xff00; - data |=3D 0x0800; - ocp_reg_write(tp, 0xb87e, data); + ocp_reg_w0w1(tp, 0xb87e, 0xff00, 0x0800); =20 /* ADC_PGA parameter */ - data =3D ocp_reg_read(tp, 0xbf00); - data &=3D ~0xe000; - data |=3D 0xa000; - ocp_reg_write(tp, 0xbf00, data); - data =3D ocp_reg_read(tp, 0xbf46); - data &=3D ~0x0f00; - data |=3D 0x0300; - ocp_reg_write(tp, 0xbf46, data); + ocp_reg_w0w1(tp, 0xbf00, 0xe000, 0xa000); + ocp_reg_w0w1(tp, 0xbf46, 0x0f00, 0x0300); =20 /* Green Table-PGA, 1G full viterbi */ sram_write(tp, 0x8044, 0x2417); @@ -7814,48 +7598,35 @@ static void r8156b_hw_phy_cfg(struct r8152 *tp) sram_write(tp, 0x807a, 0x2417); =20 /* XG PLL */ - data =3D ocp_reg_read(tp, 0xbf84); - data &=3D ~0xe000; - data |=3D 0xa000; - ocp_reg_write(tp, 0xbf84, data); + ocp_reg_w0w1(tp, 0xbf84, 0xe000, 0xa000); break; default: break; } =20 /* Notify the MAC when the speed is changed to force mode. */ - data =3D ocp_reg_read(tp, OCP_INTR_EN); - data |=3D INTR_SPEED_FORCE; - ocp_reg_write(tp, OCP_INTR_EN, data); + ocp_reg_set_bits(tp, OCP_INTR_EN, INTR_SPEED_FORCE); =20 if (rtl_phy_patch_request(tp, true, true)) return; =20 ocp_word_set_bits(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, EEE_SPDWN_EN); =20 - data =3D ocp_reg_read(tp, OCP_DOWN_SPEED); - data &=3D ~(EN_EEE_100 | EN_EEE_1000); - data |=3D EN_10M_CLKDIV; - ocp_reg_write(tp, OCP_DOWN_SPEED, data); + ocp_reg_w0w1(tp, OCP_DOWN_SPEED, EN_EEE_100 | EN_EEE_1000, + EN_10M_CLKDIV); tp->ups_info._10m_ckdiv =3D true; tp->ups_info.eee_plloff_100 =3D false; tp->ups_info.eee_plloff_giga =3D false; =20 - data =3D ocp_reg_read(tp, OCP_POWER_CFG); - data &=3D ~EEE_CLKDIV_EN; - ocp_reg_write(tp, OCP_POWER_CFG, data); + ocp_reg_clr_bits(tp, OCP_POWER_CFG, EEE_CLKDIV_EN); tp->ups_info.eee_ckdiv =3D false; =20 rtl_phy_patch_request(tp, false, true); =20 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); =20 - data =3D ocp_reg_read(tp, 0xa428); - data &=3D ~BIT(9); - ocp_reg_write(tp, 0xa428, data); - data =3D ocp_reg_read(tp, 0xa5ea); - data &=3D ~BIT(0); - ocp_reg_write(tp, 0xa5ea, data); + ocp_reg_clr_bits(tp, 0xa428, BIT(9)); + ocp_reg_clr_bits(tp, 0xa5ea, BIT(0)); tp->ups_info.lite_mode =3D 0; =20 if (tp->eee_en) @@ -7895,17 +7666,10 @@ static void r8156_init(struct r8152 *tp) } =20 data =3D r8153_phy_status(tp, 0); - if (data =3D=3D PHY_STAT_EXT_INIT) { - data =3D ocp_reg_read(tp, 0xa468); - data &=3D ~(BIT(3) | BIT(1)); - ocp_reg_write(tp, 0xa468, data); - } + if (data =3D=3D PHY_STAT_EXT_INIT) + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); WARN_ON_ONCE(data !=3D PHY_STAT_LAN_ON); @@ -7993,20 +7757,11 @@ static void r8156b_init(struct r8152 *tp) =20 data =3D r8153_phy_status(tp, 0); if (data =3D=3D PHY_STAT_EXT_INIT) { - data =3D ocp_reg_read(tp, 0xa468); - data &=3D ~(BIT(3) | BIT(1)); - ocp_reg_write(tp, 0xa468, data); - - data =3D ocp_reg_read(tp, 0xa466); - data &=3D ~BIT(0); - ocp_reg_write(tp, 0xa466, data); + ocp_reg_clr_bits(tp, 0xa468, BIT(3) | BIT(1)); + ocp_reg_clr_bits(tp, 0xa466, BIT(0)); } =20 - data =3D r8152_mdio_read(tp, MII_BMCR); - if (data & BMCR_PDOWN) { - data &=3D ~BMCR_PDOWN; - r8152_mdio_write(tp, MII_BMCR, data); - } + r8152_mdio_test_and_clr_bit(tp, MII_BMCR, BMCR_PDOWN); =20 data =3D r8153_phy_status(tp, PHY_STAT_LAN_ON); =20 --=20 2.34.1