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charset="utf-8" Add the FSP (Firmware System Processor) module for Hopper/Blackwell GPUs. These architectures use a simplified firmware boot sequence: FMC --> FSP --> GSP, with no SEC2 involvement. This commit adds the ability to wait for FSP secure boot completion by polling the I2CS thermal scratch register until FSP signals success. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fsp.rs | 148 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 29 ++++++ 3 files changed, 178 insertions(+) create mode 100644 drivers/gpu/nova-core/fsp.rs diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs new file mode 100644 index 000000000000..6d32e03d89f9 --- /dev/null +++ b/drivers/gpu/nova-core/fsp.rs @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! FSP (Firmware System Processor) interface for Hopper/Blackwell GPUs. +//! +//! Hopper/Blackwell use a simplified firmware boot sequence: FMC --> FSP = --> GSP. +//! Unlike Turing/Ampere/Ada, there is NO SEC2 (Security Engine 2) usage. +//! FSP handles secure boot directly using FMC firmware + Chain of Trust. + +use kernel::{ + device, + io::poll::read_poll_timeout, + prelude::*, + time::Delta, + transmute::{ + AsBytes, + FromBytes, // + }, +}; + +use crate::regs; + +/// FSP secure boot completion timeout in milliseconds. +/// +/// GB20x requires a longer timeout than Hopper/GB10x. +const fn fsp_secure_boot_timeout_ms(arch: crate::gpu::Architecture) -> i64= { + match arch { + crate::gpu::Architecture::BlackwellGB20x =3D> 5000, + _ =3D> 4000, + } +} + +/// GSP FMC initialization parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspFmcInitParams { + /// CC initialization "registry keys". + regkeys: u32, +} + +// SAFETY: GspFmcInitParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspFmcInitParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspFmcInitParams {} + +/// GSP ACR (Authenticated Code RAM) boot parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspAcrBootGspRmParams { + /// Physical memory aperture through which gspRmDescPa is accessed. + target: u32, + /// Size in bytes of the GSP-RM descriptor structure. + gsp_rm_desc_size: u32, + /// Physical offset in the target aperture of the GSP-RM descriptor st= ructure. + gsp_rm_desc_offset: u64, + /// Physical offset in FB to set the start of the WPR containing GSP-R= M. + wpr_carveout_offset: u64, + /// Size in bytes of the WPR containing GSP-RM. + wpr_carveout_size: u32, + /// Whether to boot GSP-RM or GSP-Proxy through ACR. + b_is_gsp_rm_boot: u32, +} + +// SAFETY: GspAcrBootGspRmParams is a simple C struct with only primitive = types. +unsafe impl AsBytes for GspAcrBootGspRmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspAcrBootGspRmParams {} + +/// GSP RM boot parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspRmParams { + /// Physical memory aperture through which bootArgsOffset is accessed. + target: u32, + /// Physical offset in the memory aperture that will be passed to GSP-= RM. + boot_args_offset: u64, +} + +// SAFETY: GspRmParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspRmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspRmParams {} + +/// GSP SPDM (Security Protocol and Data Model) parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspSpdmParams { + /// Physical memory aperture through which all addresses are accessed. + target: u32, + /// Physical offset in the memory aperture where SPDM payload buffer i= s stored. + payload_buffer_offset: u64, + /// Size of the above payload buffer. + payload_buffer_size: u32, +} + +// SAFETY: GspSpdmParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspSpdmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspSpdmParams {} + +/// Complete GSP FMC boot parameters passed to FSP. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +pub(crate) struct GspFmcBootParams { + init_params: GspFmcInitParams, + boot_gsp_rm_params: GspAcrBootGspRmParams, + gsp_rm_params: GspRmParams, + gsp_spdm_params: GspSpdmParams, +} + +// SAFETY: GspFmcBootParams is composed of C structs with only primitive t= ypes. +unsafe impl AsBytes for GspFmcBootParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspFmcBootParams {} + +/// FSP interface for Hopper/Blackwell GPUs. +pub(crate) struct Fsp; + +impl Fsp { + /// Wait for FSP secure boot completion. + /// + /// Polls the thermal scratch register until FSP signals boot completi= on + /// or timeout occurs. + #[expect(dead_code)] + pub(crate) fn wait_secure_boot( + dev: &device::Device, + bar: &crate::driver::Bar0, + arch: crate::gpu::Architecture, + ) -> Result { + debug_assert!( + regs::read_fsp_boot_complete_status(bar, arch).is_some(), + "wait_secure_boot called on non-FSP architecture" + ); + + let timeout =3D Delta::from_millis(fsp_secure_boot_timeout_ms(arch= )); + + read_poll_timeout( + || regs::read_fsp_boot_complete_status(bar, arch).ok_or(ENOTSU= PP), + |&status| status =3D=3D regs::FSP_BOOT_COMPLETE_SUCCESS, + Delta::from_millis(10), + timeout, + ) + .map_err(|_| { + dev_err!(dev, "FSP secure boot completion timeout\n"); + ETIMEDOUT + }) + .map(|_| ()) + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index 595173543d9d..2120d48f424f 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -18,6 +18,7 @@ mod falcon; mod fb; mod firmware; +mod fsp; mod gfw; mod gpu; mod gsp; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 686556bb9f38..e768a1429a2f 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -8,6 +8,7 @@ pub(crate) mod macros; =20 use kernel::{ + io::Io, prelude::*, time, // }; @@ -491,6 +492,34 @@ pub(crate) fn reset_engine(bar: &Bar0= ) { 31:0 address as u32; }); =20 +// PTHERM registers + +// FSP secure boot completion status register used by FSP to signal boot c= ompletion. +// This is the NV_THERM_I2CS_SCRATCH register. +// Different architectures use different addresses: +// - Hopper (GH100) and Blackwell GB10x: 0x000200bc +// - Blackwell GB20x: 0x00ad00bc +pub(crate) fn fsp_thermal_scratch_reg_addr(arch: Architecture) -> Result { + match arch { + Architecture::Hopper | Architecture::BlackwellGB10x =3D> Ok(0x0002= 00bc), + Architecture::BlackwellGB20x =3D> Ok(0x00ad00bc), + _ =3D> Err(kernel::error::code::ENOTSUPP), + } +} + +/// FSP writes this value to indicate successful boot completion. +pub(crate) const FSP_BOOT_COMPLETE_SUCCESS: u32 =3D 0xff; + +/// Read FSP boot completion status from the architecture-specific thermal= scratch register. +/// +/// Returns `None` if the architecture does not have an FSP. +pub(crate) fn read_fsp_boot_complete_status( + bar: &crate::driver::Bar0, + arch: Architecture, +) -> Option { + let addr =3D fsp_thermal_scratch_reg_addr(arch).ok()?; + Some(bar.read32(addr)) +} // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.53.0