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charset="utf-8" Add the FSP messaging infrastructure needed for Chain of Trust communication on Hopper/Blackwell GPUs. Reviewed-by: Joel Fernandes Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 79 ++++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 18 +++++++ 2 files changed, 95 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index 29a68d6934a9..faf923246ae9 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -108,7 +108,6 @@ pub(crate) fn emem<'a>(&self, bar: &'a Bar0) -> Emem<'a= > { /// /// Data is interpreted as little-endian 32-bit words. /// Returns `EINVAL` if offset or data length is not 4-byte aligned. - #[expect(unused)] pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) = -> Result { if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { return Err(EINVAL); @@ -129,7 +128,6 @@ pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32= , data: &[u8]) -> Result /// /// Data is stored as little-endian 32-bit words. /// Returns `EINVAL` if offset or data length is not 4-byte aligned. - #[expect(unused)] pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8= ]) -> Result { if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { return Err(EINVAL); @@ -145,4 +143,81 @@ pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32= , data: &mut [u8]) -> Resu =20 Ok(()) } + + /// Poll FSP for incoming data. + /// + /// Returns the size of available data in bytes, or 0 if no data is av= ailable. + /// + /// The FSP message queue is not circular - pointers are reset to 0 af= ter each + /// message exchange, so `tail >=3D head` is always true when data is = present. + #[expect(unused)] + pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 { + let head =3D regs::NV_PFSP_MSGQ_HEAD::read(bar).address(); + let tail =3D regs::NV_PFSP_MSGQ_TAIL::read(bar).address(); + + if head =3D=3D tail { + return 0; + } + + // TAIL points at last DWORD written, so add 4 to get total size + tail.saturating_sub(head) + 4 + } + + /// Send message to FSP. + /// + /// Writes a message to FSP EMEM and updates queue pointers to notify = FSP. + /// + /// # Arguments + /// * `bar` - BAR0 memory mapping + /// * `packet` - Message data (must be 4-byte aligned in length) + /// + /// # Returns + /// `Ok(())` on success, `Err(EINVAL)` if packet is empty or not 4-byt= e aligned + #[expect(unused)] + pub(crate) fn send_msg(&self, bar: &Bar0, packet: &[u8]) -> Result { + if packet.is_empty() { + return Err(EINVAL); + } + + // Write message to EMEM at offset 0 (validates 4-byte alignment) + self.write_emem(bar, 0, packet)?; + + // Update queue pointers - TAIL points at last DWORD written + let tail_offset =3D u32::try_from(packet.len() - 4).map_err(|_| EI= NVAL)?; + regs::NV_PFSP_QUEUE_TAIL::default() + .set_address(tail_offset) + .write(bar); + regs::NV_PFSP_QUEUE_HEAD::default() + .set_address(0) + .write(bar); + + Ok(()) + } + + /// Receive message from FSP. + /// + /// Reads a message from FSP EMEM and resets queue pointers. + /// + /// # Arguments + /// * `bar` - BAR0 memory mapping + /// * `buffer` - Buffer to receive message data + /// * `size` - Size of message to read in bytes (from `poll_msgq`) + /// + /// # Returns + /// `Ok(bytes_read)` on success, `Err(EINVAL)` if size is 0, exceeds b= uffer, or not aligned + #[expect(unused)] + pub(crate) fn recv_msg(&self, bar: &Bar0, buffer: &mut [u8], size: usi= ze) -> Result { + if size =3D=3D 0 || size > buffer.len() { + return Err(EINVAL); + } + + // Read response from EMEM at offset 0 (validates 4-byte alignment) + self.read_emem(bar, 0, &mut buffer[..size])?; + + // Reset message queue pointers after reading + regs::NV_PFSP_MSGQ_TAIL::default().set_address(0).write(bar); + regs::NV_PFSP_MSGQ_HEAD::default().set_address(0).write(bar); + + Ok(size) + } } diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index f577800db3e3..686556bb9f38 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -473,6 +473,24 @@ pub(crate) fn reset_engine(bar: &Bar0= ) { 31:0 data as u32; // EMEM data register }); =20 +// FSP (Firmware System Processor) queue registers for Hopper/Blackwell Ch= ain of Trust +// These registers manage falcon EMEM communication queues +register!(NV_PFSP_QUEUE_HEAD @ 0x008f2c00 { + 31:0 address as u32; +}); + +register!(NV_PFSP_QUEUE_TAIL @ 0x008f2c04 { + 31:0 address as u32; +}); + +register!(NV_PFSP_MSGQ_HEAD @ 0x008f2c80 { + 31:0 address as u32; +}); + +register!(NV_PFSP_MSGQ_TAIL @ 0x008f2c84 { + 31:0 address as u32; +}); + // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.53.0