From nobody Thu Apr 2 20:26:58 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 617AF41B35D for ; Thu, 26 Mar 2026 16:47:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543653; cv=none; b=F1V6wSdvPZTK/SkblUnawDvP2q/zzNaQQQXu2iyg6jhfnbRSmWwBWHMQ0aPYChi6t/HwcYWiJmmlWx3QNka14z8v33YMUpfPAfHDUKBh3H5uDKokzeYH3cy4aI1QnEuWTExTJnkDTMrkeiSCogrzzgo5esgSBJ9gu+yZbazCdsw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543653; c=relaxed/simple; bh=e0+Gl4gvADKzV1vp87wo+NG3+6GmjvIUIY/wimvNd3w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HHjoFuNHZFXydR4DomXXgVAkAQhAiDDg162TXFSNLpKA5FPD1C9alGjcVo1t1jsu+N+LfejZdH60hAEoIfJrG1unMnbV9cOltKpTJWqJ8Cxa/Lw29FBgyC51a7lxMbufGoU9z5LNYfNH+/uPd1CycM7bL96wOwFdGsEYfJi9Yjk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=QVrOi4Jp; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="QVrOi4Jp" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id DDE4D1A3003; Thu, 26 Mar 2026 16:47:30 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id AB10D601FA; Thu, 26 Mar 2026 16:47:30 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6583D10450CCF; Thu, 26 Mar 2026 17:47:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774543649; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=ebNUwgP/GGdkmoEPbwrY9xjw3LbvdfCwLlwmJ4VgFuQ=; b=QVrOi4JpUMJpUVQsP16RBS+GBel4hrhhmq83cSzANaPfLpVokx7Ajcpdkmm22BjXx1NfTB iyXvmEYjNe69ORbDFwDNmEvJFddySbIRXqOXC1J8WvtkKi2zZBMm3qh14KBUwmWz7i3gq/ v/Uiv7un6B8LYLWwmm2OdeBcJamEVosTmZBPN9/HVRkOfCsoYeQywSUXiHNQn12ggePS0e NfkEBDGF5wxPh86ARdsp3+QbU51s8mevxR6G3Mk0/43v0aMA0OP3Kzl9VtG/f0vxgo12hW znlmqC8czInGrHDlq6fE4VJe8df+qQYbByw6PqU+Ti+NjKLNM3g/fsLLdCMTbA== From: Miquel Raynal Date: Thu, 26 Mar 2026 17:47:15 +0100 Subject: [PATCH 1/4] spi: spi-mem: Add a no_cs_assertion capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-1-0d626e1dfb2b@bootlin.com> References: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> In-Reply-To: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle , Takahiro Kuwano , Pratyush Yadav , Steam Lin , Santhosh Kumar K , Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Some controllers are 'smart', and that's a problem. For instance, the Cadence quadspi controller is capable of deasserting the CS automatically whenever a too long period of time without any data to transfer elapses. This 'feature' combined with a loaded interconnect with arbitration, a "long" transfer may be split into smaller DMA transfers. In this case the controller may allow itself to deassert the CS between chunks. Deasserting the CS stops any ongoing continuous read. Reasserting it later to continue the reading will only result in the host getting garbage. In this case, the host controller driver has no control over the CS state, so we cannot reliably enable continuous reads. Flag this limitation through a spi-mem controller capability. The inversion in the flag name (starting with 'no_') is voluntary, in order to avoid the need to set this flag in all controller drivers. Only the broken controllers shall set this bit, the default being that the controller masters its CS fully. Signed-off-by: Miquel Raynal --- I am open to suggestions regarding the naming of this flag. --- include/linux/spi/spi-mem.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index bd2a73d46980..de153719a08e 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -373,7 +373,10 @@ struct spi_controller_mem_ops { * @swap16: Supports swapping bytes on a 16 bit boundary when configured in * Octal DTR * @per_op_freq: Supports per operation frequency switching - * @secondary_op_tmpl: Supports leveraging a secondary memory operation te= mplate + * @no_cs_assertion: The controller may automatically deassert the CS if t= here + * is a pause in the transfer (eg. internal bus contenti= on or + * DMA arbitration on an interconnect). Features such as= NAND + * continuous reads shall not be leveraged. */ struct spi_controller_mem_caps { bool dtr; @@ -381,6 +384,7 @@ struct spi_controller_mem_caps { bool swap16; bool per_op_freq; bool secondary_op_tmpl; + bool no_cs_assertion; }; =20 #define spi_mem_controller_is_capable(ctlr, cap) \ --=20 2.51.1 From nobody Thu Apr 2 20:26:58 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F215E41C2FE; Thu, 26 Mar 2026 16:47:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543657; cv=none; b=SEkmn0O9U7deh2vIvRMLChG/QYxy6RYjQhKNtYWEtjizRgjXJdufFrVQ0ktR0AD52H4Gz5wQrNHZxKYnwnCXW4I+9foUf4hR0qxjrV2J5r8fp9jYPupkfhkCdBB+/fwqn4FPdIaQLgiTFQ691/shhiaXwXpvymdPQuhfTEOXIjU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543657; c=relaxed/simple; bh=u1c7v30nJY0THy0bUDwZrS72xzO7sbqr8em752qHETs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Zygxv5K83U/FdBsIx4ZJ4E1gxymg07xhVbB9s9n3KBuN+1gdDssmWht4m3NToOy3vEzAhz847Yy8W11ds5r+rJknIXkAzDnFdxgUfqre4HumzImQBwaGC3hy9p+4h3D95Mu1xjn3vA8ZXdnLhKNc7zaVLE9TxHNxOWSkQyCOrEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=bQOKsQ6Q; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bQOKsQ6Q" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 8C5D7C5506D; Thu, 26 Mar 2026 16:48:00 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 486C5601FA; Thu, 26 Mar 2026 16:47:32 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0D17110450CD5; Thu, 26 Mar 2026 17:47:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774543651; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=MfQsMH01sC5rcQAhuynCASMmcusHRJHKOUkM0tEs7+Q=; b=bQOKsQ6QTW6zY4tZTrGpyVQNdfcQexSG6TnhZ+zsTd6oLFowicJL6Uc9KJPg2OPWnH8XDK 0bd8kf+aW3ynhcZE04MNOjmEr1j5A2OfDRDtZAJ9ychAiaNivK3EHHkEC0OMlhCAbC1hK2 GlKJ1VaPvFIelUPP0Z8rsC0WKXOzwPj8QkBtnUwyB5XZL9xsWTG/C1UPWZ0s2QyXxLJYUT 8aasrM3+sL3r0eIUBpYxts+66K98YnpxC5Qb52/wDjnec4U7cxNn+osSAysBYnGWQBQWY5 LdQkBVFRRdDvtt6RXhXh/jDmEnpbJcmbD8TJaZfN+GyjM55kXDog9oBwXCXlIA== From: Miquel Raynal Date: Thu, 26 Mar 2026 17:47:16 +0100 Subject: [PATCH 2/4] mtd: spinand: Make sure continuous read is always disabled during probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-2-0d626e1dfb2b@bootlin.com> References: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> In-Reply-To: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle , Takahiro Kuwano , Pratyush Yadav , Steam Lin , Santhosh Kumar K , Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Recent changes made sure whenever we were using continuous reads, we would first start by disabling the feature to ensure a well proven and stable probe sequence. For development purposes, it might also matter to make sure we always disable continuous reads at first, in case the ECC configuration would change. Doing this "automatically" will become even more relevant when we add extra controller flags to prevent continuous reads at all. Ensure we disable continuous reads if the feature is available on the chip, regardless of whether it will be used or not. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 45c3afb9cceb..dbe2c463fe01 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -953,11 +953,7 @@ static void spinand_cont_read_init(struct spinand_devi= ce *spinand) enum nand_ecc_engine_type engine_type =3D nand->ecc.ctx.conf.engine_type; =20 /* OOBs cannot be retrieved so external/on-host ECC engine won't work */ - if (spinand->set_cont_read && - (engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE || - engine_type =3D=3D NAND_ECC_ENGINE_TYPE_NONE)) { - spinand->cont_read_possible =3D true; - + if (spinand->set_cont_read) { /* * Ensure continuous read is disabled on probe. * Some devices retain this state across soft reset, @@ -965,6 +961,10 @@ static void spinand_cont_read_init(struct spinand_devi= ce *spinand) * in false positive returns from spinand_isbad(). */ spinand_cont_read_enable(spinand, false); + + if (engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE || + engine_type =3D=3D NAND_ECC_ENGINE_TYPE_NONE) + spinand->cont_read_possible =3D true; } } =20 --=20 2.51.1 From nobody Thu Apr 2 20:26:58 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5DB741C2FC; Thu, 26 Mar 2026 16:47:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543657; cv=none; b=nLat2B8Y1pKWjOTaOY1TzVfucHqA/djBwGSuio3buEYcdpvTz5zu91cjBwyyb4eYBGoXNAeBZTR+Sj3XyQ57PfSKMpNborau7JmYa2IkRxn5bN8UaKjqnDpNr+YSQX1+Wm1ZwiQPVJ490h+ZsAhOhFfZdraLcEAOSWBYq+3rcDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543657; c=relaxed/simple; bh=hJtlpYnuer3mYzJtb+Wz4CZbATTfoogGbECTCwLdIrY=; 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Thu, 26 Mar 2026 16:47:34 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1F771601FA; Thu, 26 Mar 2026 16:47:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id C8D0710450015; Thu, 26 Mar 2026 17:47:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774543653; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=teX1nj50p7T/nQpS+gQuoF7Rys4YzHubJDIitOgqOXM=; b=EZLRM5cEiOd+snGueB87q1ZnE9nd5QmVHSiERyZYLBStCh1LN8Q9RZO6BNIWXTU3AYmkTM niE3Ny/oV3lX+qZ87kSFXoxluVQYbo9j+JjWeegtV1nXtJkzDGSEWGrmeyiQU/n0w0rHjc 4Xnyq4B8yMEpOUfN2wj36ZpXF9iznaMjFzh3Q4F8cWvFIf83SzI3UIzCtKdTmwDYsFFgoO sykLNxdAbs83NajR0HIF7OszH1EMTxvvTf67tLSQjSN0wqozGxYYCVSFarz278IuuPJFi2 WwE7tT+nEkg7dq7IVaxaMqhZVNinvAaamU5ZJ0gog77RHQtEdnvzK46D7etD+A== From: Miquel Raynal Date: Thu, 26 Mar 2026 17:47:17 +0100 Subject: [PATCH 3/4] mtd: spinand: Prevent continuous reads on some controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-3-0d626e1dfb2b@bootlin.com> References: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> In-Reply-To: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle , Takahiro Kuwano , Pratyush Yadav , Steam Lin , Santhosh Kumar K , Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Some controllers do not have full control over the CS line state and may deassert it under certain conditions in the middle of a (long) transfer. Continuous reads are stopped with a CS deassert, hence both features cannot live together. Whenever a controller flags that it cannot maintain the CS state reliably, disable continuous reads entirely. Signed-off-by: Miquel Raynal --- SPI NOR reads are not affected, hence only a solution in SPI NAND is needed. --- drivers/mtd/nand/spi/core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index dbe2c463fe01..82f4dd441541 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -951,6 +951,7 @@ static void spinand_cont_read_init(struct spinand_devic= e *spinand) { struct nand_device *nand =3D spinand_to_nand(spinand); enum nand_ecc_engine_type engine_type =3D nand->ecc.ctx.conf.engine_type; + struct spi_controller *ctlr =3D spinand->spimem->spi->controller; =20 /* OOBs cannot be retrieved so external/on-host ECC engine won't work */ if (spinand->set_cont_read) { @@ -962,8 +963,9 @@ static void spinand_cont_read_init(struct spinand_devic= e *spinand) */ spinand_cont_read_enable(spinand, false); =20 - if (engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE || - engine_type =3D=3D NAND_ECC_ENGINE_TYPE_NONE) + if ((engine_type =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE || + engine_type =3D=3D NAND_ECC_ENGINE_TYPE_NONE) && + !spi_mem_controller_is_capable(ctlr, no_cs_assertion)) spinand->cont_read_possible =3D true; } } --=20 2.51.1 From nobody Thu Apr 2 20:26:58 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EDAF42189A for ; Thu, 26 Mar 2026 16:47:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543658; cv=none; b=PP7arlqtceUxENlOD303So875QzQyfvIQKTzemJLP1WYeUSjqko2qEX0O2jBTOfAn2IH5FPzE42rBXon1kXauqfctxuhWXrvxt708/jBW+X6Jm6eFLfmPZy2Olqqi2lzHwJF0thxLVNYxma3PyfoI6nXshDvukjbVn/Atik9drM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774543658; c=relaxed/simple; bh=VZF0c41xIWi4N1BeGor29G7oeIfgt476U7dOQJg9I8U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MEnoQFng9ZseHWom1fF40hQ52SEct3ST5ygmSL7/pKadJI8tDRrOTb+Prmi3jxzR9gvfUqkeonwnBg5DKNdNOn+8mEfi3mo8SiG//GxtkzAlF462Y8j2BbxGk4wtaPR/HAWax7epz0TpXO6jTxNEgXUSqR1OfblSyWH20W29Igk= ARC-Authentication-Results: i=1; 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Thu, 26 Mar 2026 17:47:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774543654; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=oi9vHPgZ6TQ8sWVxiBtvclwkIMonxdZq7gPFy31C+DI=; b=f13qncoxoULR4Z6zD7IG2dWYwE0ImXS4pJrZVzifYdfpGuM2TAObnWGnhtHJLZhxhbbAF1 kKxdYaV9LMajndQnLm5arTfIjj8xeDw9bfEEEq4h87fqCrzrg1ewe10XOVUFfBT3cQw9gt +RqUbj+zOCz6qgFQn8mJClzvsNZIygZfTGt8uqSk3dK692h+eRx/nXkLtZsM/5fdY4hByE 8hYCgxpeqXeCtrzzWUL7uW/rfigawivze800C8LqWXyOIwyB/BxRhbeuFHnejfJDiJyqgC aWYf46VKmIwUnFgEHUVBmdL9tiydFMZnoFNIP3+4wx8BeCn3CMLK0oEOlHHN2Q== From: Miquel Raynal Date: Thu, 26 Mar 2026 17:47:18 +0100 Subject: [PATCH 4/4] spi: cadence-qspi: Prevent SPI NAND continuous reads Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-4-0d626e1dfb2b@bootlin.com> References: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> In-Reply-To: <20260326-winbond-v7-0-rc1-cadence-cont-read-v1-0-0d626e1dfb2b@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Michael Walle , Takahiro Kuwano , Pratyush Yadav , Steam Lin , Santhosh Kumar K , Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 TI AM62Ax errata i2351, entitled "OSPI: Direct Access Controller (DAC) does not support Continuous Read mode with NAND Flash", explains that the CS can be deasserted almost at any time during a transfer (basically there is an interconnect arbitration every 1023 byte). This is an expected internal behaviour of the controller, but this leads to spurious CS deasserts. These are totally forbidden during SPI NAND continuous read transfers, because they indicate an end of transfer and the continuous read is then stopped on the flash side. I initially tried to query the flash type and geometry to decide whether to apply a spi message size limit (there is a spi helper for that) but we cannot reliably get up to the MTD structure to discriminate if it is a NOR or a NAND we are playing with (it is not relevant to limit SPI NOR transfers, they are not affected). If we actually take this path, what limitation shall we enforce? The errata mentions 1023B, this is super low, less than a typical page size (about 2k or 4k, for most of them), so this is not usable. On my side, I only observed this problem on a 2-page read in octal DTR mode with more than 12 dummy cycles. The writesize summed with the oobsize could be a relevant boundary, but it is still quite arbitrary. Hence, I opted for implementing a controller capability flag, which then is used to decide whether the SPI NAND continuous read feature can be enabled. Signed-off-by: Miquel Raynal --- I do not know if all flavours of this controller have the same limitation, or whether it is integration specific. As I only found mention of this errata for the AM62 processor, I opted for limiting the flag to a single compatible. --- drivers/spi/spi-cadence-quadspi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 649ff55333f0..9f9b3013aa5d 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1740,6 +1740,12 @@ static const struct spi_controller_mem_caps cqspi_me= m_caps =3D { .per_op_freq =3D true, }; =20 +static const struct spi_controller_mem_caps cqspi_am654_mem_caps =3D { + .dtr =3D true, + .per_op_freq =3D true, + .no_cs_assertion =3D true, +}; + static int cqspi_setup_flash(struct cqspi_st *cqspi) { struct platform_device *pdev =3D cqspi->pdev; @@ -1797,6 +1803,8 @@ static int cqspi_probe(struct platform_device *pdev) host->mode_bits =3D SPI_RX_QUAD | SPI_RX_DUAL; host->mem_ops =3D &cqspi_mem_ops; host->mem_caps =3D &cqspi_mem_caps; + if (of_device_is_compatible(pdev->dev.of_node, "ti,am654-ospi")) + host->mem_caps =3D &cqspi_am654_mem_caps; =20 cqspi =3D spi_controller_get_devdata(host); if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) --=20 2.51.1