From nobody Thu Apr 2 22:00:10 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57FE12D2390 for ; Thu, 26 Mar 2026 13:12:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774530765; cv=none; b=Qa7NJgOkdvF3RP0H1HxDLBGtFWVDYQpbLM7/jFNLAbF/gXh5Yoj2Xq3iKxHk0VmoR5kl0AuvwRAvuWfuiIKyqH+zXtGIEhCZ/U6YAhkYHZmrFJzcgeWLFR5YC8yZThprOyKZBsKF4mUw9gVlNDna3s45+Un+p2vLf7PW/yP/l3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774530765; c=relaxed/simple; bh=rXG4UaTkhdBDUrBbY+IrNeY5w5J0q/UWD4rfx+BbDqY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CT7pKyD3DlswFvQSFkPLOrMDaC0NawT1YMmsCXaBLsSpOMBzuqYEUjsA5wytbjn9wzKo/l6as0JIEI3MHG3T/4lkV+C9C7A0sLuhW2eNToOkc6E5VMjdLQC7WTeyXfr5GISB942WqrV3Y7YxfCb6NlzVcWlX+XuQXB+b49gNB2E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=WEoLRpMR; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="WEoLRpMR" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 5EDD19A9; Thu, 26 Mar 2026 14:11:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1774530676; bh=rXG4UaTkhdBDUrBbY+IrNeY5w5J0q/UWD4rfx+BbDqY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WEoLRpMRVOmAlS2S4q28co3eC91JwYqgVFSFcvjH/c1FJReRD0/ocUBevrEBjQO3Q 3EB1TdB2Y66zkaR+u5cPH2Ixlh3H/r4/As4my1pxR1QRrmoQt4yVS0BpHIbKr+uSNR AbjprNfdkcdOwxlHEQuz9V1etcGpsYKqb1ubsOHI= From: Tomi Valkeinen Date: Thu, 26 Mar 2026 15:12:11 +0200 Subject: [PATCH 1/8] drm/bridge: tc358762: Clean up register defines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-tc358762-fixes-v1-1-65f479227af5@ideasonboard.com> References: <20260326-tc358762-fixes-v1-0-65f479227af5@ideasonboard.com> In-Reply-To: <20260326-tc358762-fixes-v1-0-65f479227af5@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2518; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=rXG4UaTkhdBDUrBbY+IrNeY5w5J0q/UWD4rfx+BbDqY=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBpxTC9rtx0SrhmfdwgN+Vll0deoIYDIFaTyUfmr xcmPNK1CHuJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCacUwvQAKCRD6PaqMvJYe 9dvRD/9PN/6p3aU2QCxzt8gec148EDgD/hdvjYlSDkrQ8Dgdj/ZqCHsc60HInEy0uxo/BqMMB9b mhO/QX9tJFX5QCUD6xLva2SscERRUyg3/Q6UYbt/Tsd5cBXbNIMrFMtl74S1o9vzs++leRt+Xv1 TKOpwPgZsdo4PxvfaqJwYLa++27ccrFbzXIk3ed5LOl/irIFXY1enQaZy172hss7U4e0YU+uGJ3 A/WpYJMVdkn438E8A9kb1adSige4Vb6sNsxqcnqHAdIicxeNHk1V21IkLLdnlEEYYdxbGqDGbl5 +vbLiqq7pnqDfNBrUSZgdafD7lsQCxC+crvCd3lG6wrfwkjLUPh/1ouS0/4rBoL0V0bpbWoxeKZ Lg3upY0LQqb/Ly6NcEgrzNWUVcxbI6dmA44kvDBjROkqGcz6NJZyRbcvHVfZuuvP/q9JVJlatnv NhF6Q28TMfFCyekRXmM6QQPzuZvCgSvm4+h88NghNakleSJIN+CDynBr1LO6sCem5oLD51nd78M AhRCa7X0W2lwh8v/khqZDz0MkFM3KJ08GZkPunr/Ic4iWfIh9oY2mMZyFALhPlqZGqRG3HKhgN8 6ydRGZExdftochLnggrMdRK+ighQIXF3YgWJqJDx+vx0aCL9LUFhGc7r2y0H8dygiI/ReHRtT+b 5ZtEHwVMtnnzLLw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Move the defines around and rename for clarity and consistency. No functional change. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index 98df3e667d4a..833fd9913c75 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -29,17 +29,22 @@ =20 /* PPI layer registers */ #define PPI_STARTPPI 0x0104 /* START control bit */ +#define PPI_STARTPPI_STARTPPI BIT(0) + #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ #define PPI_D0S_ATMR 0x0144 #define PPI_D1S_ATMR 0x0148 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ -#define PPI_START_FUNCTION 1 =20 /* DSI layer registers */ #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ +#define DSI_STARTDSI_STARTDSI BIT(0) + #define DSI_LANEENABLE 0x0210 /* Enables each lane */ -#define DSI_RX_START 1 +#define DSI_LANEENABLE_CLEN BIT(0) +#define DSI_LANEENABLE_L0EN BIT(1) +#define DSI_LANEENABLE_L1EN BIT(2) =20 /* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 = */ #define LCDCTRL 0x0420 /* Video Path Control */ @@ -60,14 +65,8 @@ /* System Controller Registers */ #define SYSCTRL 0x0464 =20 -/* System registers */ #define LPX_PERIOD 3 =20 -/* Lane enable PPI and DSI register bits */ -#define LANEENABLE_CLEN BIT(0) -#define LANEENABLE_L0EN BIT(1) -#define LANEENABLE_L1EN BIT(2) - struct tc358762 { struct device *dev; struct drm_bridge bridge; @@ -118,7 +117,7 @@ static int tc358762_init(struct tc358762 *ctx) u32 lcdctrl; =20 tc358762_write(ctx, DSI_LANEENABLE, - LANEENABLE_L0EN | LANEENABLE_CLEN); + DSI_LANEENABLE_L0EN | DSI_LANEENABLE_CLEN); tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5); tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5); tc358762_write(ctx, PPI_D0S_ATMR, 0); @@ -141,8 +140,8 @@ static int tc358762_init(struct tc358762 *ctx) tc358762_write(ctx, SYSCTRL, 0x040f); msleep(100); =20 - tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); - tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START); + tc358762_write(ctx, PPI_STARTPPI, PPI_STARTPPI_STARTPPI); + tc358762_write(ctx, DSI_STARTDSI, DSI_STARTDSI_STARTDSI); =20 msleep(100); =20 --=20 2.43.0