From nobody Fri Apr 3 00:00:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E19B3AEF58; Thu, 26 Mar 2026 08:06:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774512401; cv=none; b=ciubWUSrznWY8uoo/ft0ywR7jDWTdRAHrNkb8nDvn7larZyw2IuRosNrqQnyZdnnzrm9SL/Vg3YSK1CPVKF0hwmF33tzTLLTamlmAzp4a6RcL0T7yQw0jNElW3Fjg2po3cEKheW9MK9arZbrgDSX5t9yJnTCTtUUkQ5gz0/6kxw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774512401; c=relaxed/simple; bh=QPg5ucT2J9JR6E3rS7caTqzm372tAM2YlgwRdg7/hwg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MKaiSzj8oT6OmqUO/9Dhf6Lnu58lTCpZpScdser/ecWsHQC4sSe1kSzmZRIOD365cmRbhhkFG0IalAsg0Gicvek6Y8exZ9cSYPPTtvwCsIse7Z054G0wKODjyDh2rQIcKwpE2GtUpVSXpczN4S1g6024ELWGfzEEnJop29adxPU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mdUouJFO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mdUouJFO" Received: by smtp.kernel.org (Postfix) with ESMTPS id E41F6C2BC87; Thu, 26 Mar 2026 08:06:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774512401; bh=QPg5ucT2J9JR6E3rS7caTqzm372tAM2YlgwRdg7/hwg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=mdUouJFOe7iVby+PU1+ECWuAy6xXL4uRrYoOlf2oK9U68N9lM0OlJfevgSOMFfrMx x5FKszNh2kFIBPGd2yFGfb8nriW4UE7SPk9R+gjKm8ndGP2bu3J0l1qAEwPzP2W5DO 0CNi4DiOvewbTJQ0a6QTgkmviXyrqwOR8w6QviSGTebdqDw1oJcAVrNyMYHtcPj2+g WINP5kMJIjkiaDEyuxci+0zroEGoBQtd73rFLU9KTaPz7VM74BY/Ao/qthBcFpwgIK 7SC4Vk81T7ey/Ky+B0rZ5PsB5mBHvK35CdV2s9s6JwPiJDgWQM54m9TV/OCeDfHPNl 5q6ej8qzEChhQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DACB1106F2F4; Thu, 26 Mar 2026 08:06:40 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Thu, 26 Mar 2026 13:36:35 +0530 Subject: [PATCH v7 7/8] power: sequencing: pcie-m2: Add support for PCIe M.2 Key E connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-pci-m2-e-v7-7-43324a7866e6@oss.qualcomm.com> References: <20260326-pci-m2-e-v7-0-43324a7866e6@oss.qualcomm.com> In-Reply-To: <20260326-pci-m2-e-v7-0-43324a7866e6@oss.qualcomm.com> To: Rob Herring , Greg Kroah-Hartman , Jiri Slaby , Nathan Chancellor , Nicolas Schier , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Mark Pearson , "Derek J. Clark" , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , Marcel Holtmann , Luiz Augusto von Dentz , Bartosz Golaszewski , Andy Shevchenko , Bartosz Golaszewski Cc: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-bluetooth@vger.kernel.org, linux-pm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-acpi@vger.kernel.org, Manivannan Sadhasivam , Hans de Goede X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6901; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=HRGptE1JIyA395dlxkM3raRO8gPG2oSfeqDUBhjL6YY=; b=kA0DAAoBVZ8R5v6RzvUByyZiAGnE6Q2hXkEob2zwJaf4tJlYmf+8mDScgkgd22Ujhq84tXZHo IkBMwQAAQoAHRYhBGelQyqBSMvYpFgnl1WfEeb+kc71BQJpxOkNAAoJEFWfEeb+kc710RYIAJdV OwNYBVHVoy340ClaeQUqbv3iuxJutNdyMvn2I3K6Otq8/3Te+1dtfB8VGt4uysULp4Js49LvewG L9cgRMIwX1J+zcxbdtSieXfE0LOp3F4ZBz3UlIA0KPvSHxbn297ojpePAK8pteYhoSyve1uKjEt tjDDALlqDHBy7NVcEEMt+5l+Gc471FWutJrjqaNiZt0aKrMNMAf5CMZze8WKyI7MB9E05WrDKcO 5ujoWawieDxUob74VuzWB6iMVudd5JAWbbcwairLzWqTTwkltPO3mhC3D/s4gsXzaGCiLNFG42d Cxg/cgaF8oIreBPDXwiTfSpIbUjWVtzLNTM44fg= X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add support for handling the power sequence of the PCIe M.2 Key E connectors. These connectors are used to attach the Wireless Connectivity devices to the host machine including combinations of WiFi, BT, NFC using interfaces such as PCIe/SDIO for WiFi, USB/UART for BT and I2C for NFC. Currently, this driver supports only the PCIe interface for WiFi and UART interface for BT. The driver also only supports driving the 3.3v/1.8v power supplies and W_DISABLE{1/2}# GPIOs. The optional signals of the Key E connectors are not currently supported. Tested-by: Hans de Goede # ThinkPad T14s = gen6 (arm64) Signed-off-by: Manivannan Sadhasivam --- drivers/power/sequencing/pwrseq-pcie-m2.c | 107 ++++++++++++++++++++++++++= ++-- 1 file changed, 101 insertions(+), 6 deletions(-) diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequ= encing/pwrseq-pcie-m2.c index d31a7dd8b35c..3507cdcb1e7b 100644 --- a/drivers/power/sequencing/pwrseq-pcie-m2.c +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -5,10 +5,13 @@ */ =20 #include +#include +#include #include #include #include #include +#include #include #include #include @@ -25,16 +28,18 @@ struct pwrseq_pcie_m2_ctx { struct regulator_bulk_data *regs; size_t num_vregs; struct notifier_block nb; + struct gpio_desc *w_disable1_gpio; + struct gpio_desc *w_disable2_gpio; }; =20 -static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq) +static int pwrseq_pcie_m2_vregs_enable(struct pwrseq_device *pwrseq) { struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); =20 return regulator_bulk_enable(ctx->num_vregs, ctx->regs); } =20 -static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq) +static int pwrseq_pcie_m2_vregs_disable(struct pwrseq_device *pwrseq) { struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); =20 @@ -43,18 +48,84 @@ static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq= _device *pwrseq) =20 static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data =3D { .name =3D "regulators-enable", - .enable =3D pwrseq_pcie_m2_m_vregs_enable, - .disable =3D pwrseq_pcie_m2_m_vregs_disable, + .enable =3D pwrseq_pcie_m2_vregs_enable, + .disable =3D pwrseq_pcie_m2_vregs_disable, }; =20 -static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] =3D { +static const struct pwrseq_unit_data *pwrseq_pcie_m2_unit_deps[] =3D { &pwrseq_pcie_m2_vregs_unit_data, NULL }; =20 +static int pwrseq_pci_m2_e_uart_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable2_gpio, 0); +} + +static int pwrseq_pci_m2_e_uart_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable2_gpio, 1); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_e_uart_unit_data =3D { + .name =3D "uart-enable", + .deps =3D pwrseq_pcie_m2_unit_deps, + .enable =3D pwrseq_pci_m2_e_uart_enable, + .disable =3D pwrseq_pci_m2_e_uart_disable, +}; + +static int pwrseq_pci_m2_e_pcie_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable1_gpio, 0); +} + +static int pwrseq_pci_m2_e_pcie_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return gpiod_set_value_cansleep(ctx->w_disable1_gpio, 1); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_e_pcie_unit_data =3D { + .name =3D "pcie-enable", + .deps =3D pwrseq_pcie_m2_unit_deps, + .enable =3D pwrseq_pci_m2_e_pcie_enable, + .disable =3D pwrseq_pci_m2_e_pcie_disable, +}; + static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data =3D { .name =3D "pcie-enable", - .deps =3D pwrseq_pcie_m2_m_unit_deps, + .deps =3D pwrseq_pcie_m2_unit_deps, +}; + +static int pwrseq_pcie_m2_e_pwup_delay(struct pwrseq_device *pwrseq) +{ + /* + * FIXME: This delay is only required for some Qcom WLAN/BT cards like + * WCN7850 and not for all devices. But currently, there is no way to + * identify the device model before enumeration. + */ + msleep(50); + + return 0; +} + +static const struct pwrseq_target_data pwrseq_pcie_m2_e_uart_target_data = =3D { + .name =3D "uart", + .unit =3D &pwrseq_pcie_m2_e_uart_unit_data, + .post_enable =3D pwrseq_pcie_m2_e_pwup_delay, +}; + +static const struct pwrseq_target_data pwrseq_pcie_m2_e_pcie_target_data = =3D { + .name =3D "pcie", + .unit =3D &pwrseq_pcie_m2_e_pcie_unit_data, + .post_enable =3D pwrseq_pcie_m2_e_pwup_delay, }; =20 static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = =3D { @@ -62,11 +133,21 @@ static const struct pwrseq_target_data pwrseq_pcie_m2_= m_pcie_target_data =3D { .unit =3D &pwrseq_pcie_m2_m_pcie_unit_data, }; =20 +static const struct pwrseq_target_data *pwrseq_pcie_m2_e_targets[] =3D { + &pwrseq_pcie_m2_e_pcie_target_data, + &pwrseq_pcie_m2_e_uart_target_data, + NULL +}; + static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] =3D { &pwrseq_pcie_m2_m_pcie_target_data, NULL }; =20 +static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_e_of_data =3D { + .targets =3D pwrseq_pcie_m2_e_targets, +}; + static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data =3D { .targets =3D pwrseq_pcie_m2_m_targets, }; @@ -125,6 +206,16 @@ static int pwrseq_pcie_m2_probe(struct platform_device= *pdev) return dev_err_probe(dev, ret, "Failed to get all regulators\n"); =20 + ctx->w_disable1_gpio =3D devm_gpiod_get_optional(dev, "w-disable1", GPIOD= _OUT_HIGH); + if (IS_ERR(ctx->w_disable1_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->w_disable1_gpio), + "Failed to get the W_DISABLE_1# GPIO\n"); + + ctx->w_disable2_gpio =3D devm_gpiod_get_optional(dev, "w-disable2", GPIOD= _OUT_HIGH); + if (IS_ERR(ctx->w_disable2_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->w_disable2_gpio), + "Failed to get the W_DISABLE_2# GPIO\n"); + ctx->num_vregs =3D ret; =20 ret =3D devm_add_action_or_reset(dev, pwrseq_pcie_m2_free_regulators, ctx= ); @@ -150,6 +241,10 @@ static const struct of_device_id pwrseq_pcie_m2_of_mat= ch[] =3D { .compatible =3D "pcie-m2-m-connector", .data =3D &pwrseq_pcie_m2_m_of_data, }, + { + .compatible =3D "pcie-m2-e-connector", + .data =3D &pwrseq_pcie_m2_e_of_data, + }, { } }; MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match); --=20 2.51.0