From nobody Fri Apr 3 00:00:14 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5012F749C for ; Thu, 26 Mar 2026 01:00:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774486849; cv=none; b=YSIHeWdPYaEYpE2GoTP1rujrbVa8S06IIWJDYAoi+sc/GZNYBYiqiLdGcD3tPhp3Z1D1U/fM++iYD3IoDTsGoATz5BwGs2qr2oOW0AFzEaOEzH7+Na7bA+ib/3RCEzUFOdiZ7v9E2csFt07nQ0+BVaF1f7ST5otzEFrEv4EuGY0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774486849; c=relaxed/simple; bh=lyRbHi+OdyYuf4O4gqm9rBgjcRMxdLni+ze0KPaLbdQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=meKUa/1RU9qNudCxnbNdHgnTl4RuQP2k9wBG81BlA/ZMl04w8VndXPQFi9zM6YZS+4W+mCJFoN0/TF4Nu64WYbllSKwFwZsYZHRS4TNtSwZbjmFqmjjFUl8FaI4q9HF9c72gAGa/V//0k2t5uFqFc3vePr4anh6rrHtWPltKI4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=H8Ol9WCO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H8Ol9WCO" Received: by smtp.kernel.org (Postfix) with ESMTPS id D4F2FC4CEF7; Thu, 26 Mar 2026 01:00:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774486848; bh=lyRbHi+OdyYuf4O4gqm9rBgjcRMxdLni+ze0KPaLbdQ=; h=From:Date:Subject:To:Cc:Reply-To:From; b=H8Ol9WCOVZKWHac5yz3H5F+i71pUzkU52JVRkesbRzWFHzi4pPJ/9R3RjS8pfOmtl RFw31IgpV0OU7IoJq1GUpN3cc1y6bMNZfszIDb5BUgyf0fSvndxGB7bmAVeS8tuxjN 3ryzJQGk4q32diLDjYTLCbxSN8/POKjJwt7BcAU02DU4jB3ax7sqBWbJzr+5M+im0n EslYP7j2DMzhgmlJUyY2CwNOIOmim/lS+KWwNugVkgDDs236l92Z0mj/+qnKCIuz0Z DX42610j23h0HIGrEZuyDlqUW9e2vfeyak6wjpSzjnKLt6YCW9nyc/r+lVMkR+8FJK 9uYiKt/6pA6UA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0388109E52B; Thu, 26 Mar 2026 01:00:48 +0000 (UTC) From: Roman Vivchar via B4 Relay Date: Thu, 26 Mar 2026 03:00:47 +0200 Subject: [PATCH] clocksource/drivers/timer-mediatek: initialize GPT6 as system counter Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-archtimer-v1-1-5328574e5935@protonmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDYyNT3cSi5IySzNzUIl1jU/MkA6M0cxMDUwsloPqCotS0zAqwWdGxtbU AfxNdA1sAAAA= X-Change-ID: 20260325-archtimer-357b02f74058 To: Daniel Lezcano , Thomas Gleixner , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Akari Tsuyukusa , Roman Vivchar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774486847; l=2040; i=rva333@protonmail.com; s=20260325; h=from:subject:message-id; bh=yXLTuLAUXSGAa9XhaQxQZMpIErABYX5VH7iq2PdHl/I=; b=CkjxoHpTP04gLssC28KwNiKO/2GD1L0djaFjsZPxG+Xdk1tr1Ar+H+0rQ8dlleGW5YWaDdQvz KXCJOx3HpXYB5CxlTCwQUDILFRGTPuOmHDxlW4PgJnhBEcsplRiSDro X-Developer-Key: i=rva333@protonmail.com; a=ed25519; pk=euuVBZGtA2Cqb8Dju84qpQPhvwxyUirJlXpqEPQWKBM= X-Endpoint-Received: by B4 Relay for rva333@protonmail.com/20260325 with auth_id=695 X-Original-From: Roman Vivchar Reply-To: rva333@protonmail.com From: Roman Vivchar On certain MediaTek SoCs like mt6572 (likely before the CPUXGPT was introduced), the generic arch timer is fed by the GPT6. Some bootloaders don't initialize it properly, leading to dead arch timer. Fix this by configuring GPT6 when the MediaTek timer is probed. This makes arch timer work properly and removes IPI overhead from MediaTek timer broadcast when arch timer is used. If the timer was configured by the bootloader, this change is no-op. Tested-by: Akari Tsuyukusa # MT6589 Signed-off-by: Roman Vivchar Tested-by: Akari Tsuyukusa --- On certain MediaTek SoCs like mt6572 (likely before the CPUXGPT was introduced), the generic arch timer is fed by the GPT6. Some bootloaders don't initialize it properly, leading to dead arch timer. Fix this by configuring GPT6 when the MediaTek timer is probed. This makes arch timer work properly and removes IPI overhead from MediaTek timer broadcast when arch timer is used. If the timer was configured by the bootloader, this change is no-op. --- drivers/clocksource/timer-mediatek.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/tim= er-mediatek.c index 7bcb4a3f26fb..7de34cace572 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -22,6 +22,8 @@ =20 #define TIMER_SYNC_TICKS (3) =20 +#define TIMER_SYSCNT (6) + /* gpt */ #define GPT_IRQ_EN_REG 0x00 #define GPT_IRQ_ENABLE(val) BIT((val) - 1) @@ -335,6 +337,9 @@ static int __init mtk_gpt_init(struct device_node *node) =20 mtk_gpt_enable_irq(&to, TIMER_CLK_EVT); =20 + /* Configure GPT6 to feed arch timer */ + mtk_gpt_setup(&to, TIMER_SYSCNT, GPT_CTRL_OP_FREERUN); + return 0; } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init); --- base-commit: 05f7e89ab9731565d8a62e3b5d1ec206485eeb0b change-id: 20260325-archtimer-357b02f74058 Best regards, --=20 Roman Vivchar