From nobody Thu Apr 2 23:33:39 2026 Received: from courrier.aliel.fr (pouet.aliel.fr [65.21.61.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5B573BFE4F; Thu, 26 Mar 2026 10:01:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=65.21.61.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774519320; cv=none; b=kTCB7n8XeaPqUBu9nqnphb+oPwLwL26puIWuYyLYfM+6naD/3bZaCPXotHnmJNP7t++3o1iYbwlV6WcqsUcEAW5u+MREDVkMRms9gUnmlCw6oXz6nwiq5cKTCjM0DcTsba+0EoQdHUb5yGFUFCauSkPhG8cO5ui/ApiaVcQOYe8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774519320; c=relaxed/simple; bh=z50cReUoaX9GoqnPxRfb8M2ESTEiHmyiXX+yYCUCnAY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=h6X37VutrJnOz9wyJdcadD3hUCIj5LvxzOtgEWYuF/d+xAfjxUGtUJQQrpUiqxACukSAmmDaLbLuNDHPJoXIUSwUo6UKUTb6woNedXy/DMKiZLFe2oP9VhMknwSUfXnoOnoLOoX0Oz0DDBZB3ZoyEyohcG7fn8j5f8099ITtFXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=aliel.fr; spf=pass smtp.mailfrom=aliel.fr; dkim=pass (1024-bit key) header.d=aliel.fr header.i=@aliel.fr header.b=jUOwOl3G; arc=none smtp.client-ip=65.21.61.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=aliel.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aliel.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=aliel.fr header.i=@aliel.fr header.b="jUOwOl3G" From: Ronald Claveau DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aliel.fr; s=courrier-s1; t=1774519317; bh=z50cReUoaX9GoqnPxRfb8M2ESTEiHmyiXX+yYCUCnAY=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=jUOwOl3GEvucd0hLrjOmNy4lrVdh7/mgdS+yw2qflKrvdJpXtfb9wSJ1bDmzV1jFo sxGj5fgY5PpuNTchASPtnBl+/fvUkztThC1UgDadfroVzX+9qDmlomwODW1c2K1lYZ Yzkk94G+IChMyBDOHqZgO2tkYxXiSzVgpwmmayF0= Date: Thu, 26 Mar 2026 10:59:14 +0100 Subject: [PATCH v5 3/9] arm64: dts: amlogic: t7: Add MMC controller nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260326-add-emmc-t7-vim4-v5-3-d3f182b48e9d@aliel.fr> References: <20260326-add-emmc-t7-vim4-v5-0-d3f182b48e9d@aliel.fr> In-Reply-To: <20260326-add-emmc-t7-vim4-v5-0-d3f182b48e9d@aliel.fr> To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Johannes Berg , van Spriel Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-wireless@vger.kernel.org, Ronald Claveau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openssh-sha256; t=1774519312; l=2309; i=linux-kernel-dev@aliel.fr; s=id_ed25519; h=from:subject:message-id; bh=z50cReUoaX9GoqnPxRfb8M2ESTEiHmyiXX+yYCUCnAY=; b=U1NIU0lHAAAAAQAAADMAAAALc3NoLWVkMjU1MTkAAAAgMGec55oxeeisqykQiUedekMYyOnR9 BG9E/7rDWyqdNoAAAAGcGF0YXR0AAAAAAAAAAZzaGE1MTIAAABTAAAAC3NzaC1lZDI1NTE5AAAA QGA7rZGuJlRS3I4Zqj6o1Wl7h8UH4dEpOYz7EeGFQMRZ/lMD9CqQEq5BSkQHalit9fuCnDRIqfg vrG9sVZABnwI= X-Developer-Key: i=linux-kernel-dev@aliel.fr; a=openssh; fpr=SHA256:kch4osYZ6A1BrPps5AUs6KnfdE2wm4ocMtyTc8TmZMs Add device tree nodes for the three MMC controllers available on the Amlogic T7 SoC, using amlogic,meson-axg-mmc as fallback compatible. All nodes are disabled by default and should be enabled in the board-specific DTS file. Signed-off-by: Ronald Claveau Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 39 +++++++++++++++++++++++++= ++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index 36d13371f56ba..fe1ced0a58967 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -374,6 +374,45 @@ sec_ao: ao-secure@10220 { reg =3D <0x0 0x10220 0x0 0x140>; amlogic,has-chip-id; }; + + sd_emmc_a: mmc@88000 { + compatible =3D "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; + reg =3D <0x0 0x88000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_A>, + <&clkc_periphs CLKID_SD_EMMC_A>, + <&scmi_clk CLKID_FCLK_DIV2>; + clock-names =3D "core", "clkin0", "clkin1"; + assigned-clocks =3D <&clkc_periphs CLKID_SD_EMMC_A_SEL>; + assigned-clock-parents =3D <&xtal>; + status =3D "disabled"; + }; + + sd_emmc_b: mmc@8a000 { + compatible =3D "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; + reg =3D <0x0 0x8a000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_B>, + <&clkc_periphs CLKID_SD_EMMC_B>, + <&scmi_clk CLKID_FCLK_DIV2>; + clock-names =3D "core", "clkin0", "clkin1"; + assigned-clocks =3D <&clkc_periphs CLKID_SD_EMMC_B_SEL>; + assigned-clock-parents =3D <&xtal>; + status =3D "disabled"; + }; + + sd_emmc_c: mmc@8c000 { + compatible =3D "amlogic,t7-mmc", "amlogic,meson-axg-mmc"; + reg =3D <0x0 0x8c000 0x0 0x800>; + interrupts =3D ; + clocks =3D <&clkc_periphs CLKID_SYS_SD_EMMC_C>, + <&clkc_periphs CLKID_SD_EMMC_C>, + <&scmi_clk CLKID_FCLK_DIV2>; + clock-names =3D "core", "clkin0", "clkin1"; + assigned-clocks =3D <&clkc_periphs CLKID_SD_EMMC_C_SEL>; + assigned-clock-parents =3D <&xtal>; + status =3D "disabled"; + }; }; =20 }; --=20 2.49.0