From nobody Thu Apr 2 01:49:54 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 357FC3CEBBB for ; Wed, 25 Mar 2026 19:25:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774466703; cv=none; b=WerIViiE4c0LvOSb+b3Xe5myinPIUFUrFTWoxFgwjD6D8YDPY3oc1Bh6J3LAq87VU1eoK1Ep3tpSouMxvRyTRfqGew5hr/dEfFpuLLvSJOVVaOxGSJhgsBstNOY/mkrjCFg1pNQZ4tf6/rcJsGiKWMgciW/YGgE/qZNs/RW4PmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774466703; c=relaxed/simple; bh=L9pPjTfCwS4VXxN4s2LgusYp6krYScu9ZQkXUDMkk1E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e9bCkeUTDwygPe5J0+RuLSsBQl6wSgPiXPoRkWj9TPDxWPXN96RvtFTcU7jcpomcwkf1E/DisX0tSS2fZ12C+NLTlZoSvXHtwH1eWzObqnntlnswCI4PwFFyKBImyQOXoGwTly/zc/TMuKc71IdYSa6PXDj5phMhkz15pr+iSwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TpiqZXBZ; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TpiqZXBZ" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-439b2965d4bso124867f8f.2 for ; Wed, 25 Mar 2026 12:25:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1774466700; x=1775071500; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FqVycoY+zBPXuLapcLYV9KCIArn7CTAnQNJ+GY59juM=; b=TpiqZXBZiTNe0QjgMiA79DOU1b3Cpxn7eLnne5hP0SvtJiQWDhv8lnsL1jikMC4sFQ P0+paLGnemVBUEzAWtd80gcyZ3zd2VBhoYP+p+zrpzdq+xScTNA2fJ1x0sLtvvzJesNa gOSXuxRbOrsZyO12acP0qVy72RmrhvyUQC8Ot3tp3Sj8Iu+SUjtjl1PmHX6Z+9cEWFPb E9fjZje2qy0NGa1xoq1ELnXlFBLirZEUiDsd0gXhY4vSnK80FE95T/uG+2/1d8X0Gqao wi0NMdUkn16r4FLje0J/drkVf/n6lbchnuWW7BV7N8vQv5UVPkmys0V7JM+JpxBFJZuq 17jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774466700; x=1775071500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=FqVycoY+zBPXuLapcLYV9KCIArn7CTAnQNJ+GY59juM=; b=eSdMo5mCius9/KWVZJHTtnTOqpM4tHvAdBJSUNhhNq6wR9F6IHWr6wFtZnZbGAVQvf CMEneQutUF7QNPqyus99yClamkJQy5xpyKCntr7YrSooQZo77jAWwEjALI5BVqBl1b5D zV86q5beRMMuDzzTmmcZIInJLTp4y77bWHCJ4W+I4P+n4nyebPApKgBmoAb0ytzbdkiC cotRAG97kC+iUmIluYc4HsXy94wBnV8x/og39oreQxtvSnAEsP33+6nfh4PbeQnHH18M 5rKfjseWTsbt+eWotgEaHvAhJ0WXE/HP3eI95RdLltL5M4cE8bJx7sfjHt4gn2tPiHRi fZ5g== X-Forwarded-Encrypted: i=1; AJvYcCVwhvyUjnwwXxvGMzm57/3qJa2f3D5hH5B4ERIBDOtaBS/TlSXy7f/7H1u+kuzWtshzj3XjHMPEmEy8OMA=@vger.kernel.org X-Gm-Message-State: AOJu0YzWdVzwmrxCqz08JOGyruGWSPZxalhHLZ/D0uSc8ckwV4ryh0Z6 s86b4z9tP4FiD+AaaxmbNBUCcdSKfmTRjAa/HSTJFGq3viGfsK+W+j6N X-Gm-Gg: ATEYQzyoN6KjnI2wtHum12R+76uuAyYt4JIfd3wNsELKXRytsbJmMXOjSG87GAMzUfV CUan2+yRTc5jsCYERPsp5YaDURxEq/JfGHROM+yeT0o8tSUp0XHmBjKPPJB0IOlYrjSAe2pn4LK 7w+WV66s1yI/o5I3Dl7oEaaDhN4VvrmfKLT7iEcIL+hXME+EngSoX9np7/DPFcD+OzYP1qFdNyr UxxHWbReLiWUuvPV3wls3ym/GSh6sSWdLaKuZfnaWhTiuUmdGV+ULKXwj/WlY3dvGUvgkNxYFNq Ar8oo7zy35Zs25UGbwamtyVS1s8OU3/gapzj337gnDUuCwYe2p9lP81tW1nUWtHQJjFN8ponx4j vAdFdjEd8mElNsrAv7rAUQZVUAF703q2HZEQzhUzpeUOAW0lY371cxMAtUgzj26J3lk8uQmw7PY Mmc4qt2ZHBpYUlJKSWbExFWcld15ldYC8ZJ3SaAfTiuW8mrTcO X-Received: by 2002:a05:600c:458e:b0:486:fd5c:2b35 with SMTP id 5b1f17b1804b1-48715fe28f4mr62122185e9.13.1774466700512; Wed, 25 Mar 2026 12:25:00 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:8138:17e4:88b1:468c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b9192e533sm2464485f8f.2.2026.03.25.12.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 12:25:00 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v7 07/16] irqchip/renesas-rzg2l: Split set_type handler into separate IRQ and TINT functions Date: Wed, 25 Mar 2026 19:24:22 +0000 Message-ID: <20260325192451.172562-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The single rzg2l_irqc_set_type() handler used hw_irq range checks to dispatch to either rzg2l_irq_set_type() or rzg2l_tint_set_edge(). Split this into two dedicated handlers, rzg2l_irqc_irq_set_type() and rzg2l_irqc_tint_set_type(), each calling only their respective type configuration function without runtime conditionals. Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * No change. v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 664599acbeb6..b3457a419bab 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -393,15 +393,22 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) return 0; } =20 -static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) +static int rzg2l_irqc_irq_set_type(struct irq_data *d, unsigned int type) { - unsigned int hw_irq =3D irqd_to_hwirq(d); - int ret =3D -EINVAL; + int ret; + + ret =3D rzg2l_irq_set_type(d, type); + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static int rzg2l_irqc_tint_set_type(struct irq_data *d, unsigned int type) +{ + int ret; =20 - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) - ret =3D rzg2l_irq_set_type(d, type); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - ret =3D rzg2l_tint_set_edge(d, type); + ret =3D rzg2l_tint_set_edge(d, type); if (ret) return ret; =20 @@ -454,7 +461,7 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_irq_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -471,7 +478,7 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_tint_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -488,7 +495,7 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_irq_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | @@ -505,7 +512,7 @@ static const struct irq_chip rzfive_irqc_tint_chip =3D { .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, - .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_type =3D rzg2l_irqc_tint_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, .flags =3D IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | --=20 2.43.0