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Wed, 25 Mar 2026 12:24:59 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v7 06/16] irqchip/renesas-rzg2l: Split EOI handler into separate IRQ and TINT functions Date: Wed, 25 Mar 2026 19:24:21 +0000 Message-ID: <20260325192451.172562-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The single rzg2l_irqc_eoi() handler used a conditional to determine whether to clear an IRQ or TINT interrupt. Split this into two dedicated handlers, rzg2l_irqc_irq_eoi() and rzg2l_irqc_tint_eoi(), each handling only their respective interrupt type without the need for range checks. While at it, simplify rzg2l_irqc_{irq,tint}_eoi() by replacing raw_spin_lock locking/unlocking with scoped_guard(). Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * Simplified rzg2l_irqc_{irq,tint}_eoi() by replacing raw_spin_lock locking/unlocking with scoped_guard(). * Updated commit description. v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 1d1df4953368..664599acbeb6 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -130,17 +130,25 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_pr= iv *priv, unsigned int hwir } } =20 -static void rzg2l_irqc_eoi(struct irq_data *d) +static void rzg2l_irqc_irq_eoi(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); =20 - raw_spin_lock(&priv->lock); - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) + scoped_guard(raw_spinlock, &priv->lock) rzg2l_clear_irq_int(priv, hw_irq); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + + irq_chip_eoi_parent(d); +} + +static void rzg2l_irqc_tint_eoi(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + + scoped_guard(raw_spinlock, &priv->lock) rzg2l_clear_tint_int(priv, hw_irq); - raw_spin_unlock(&priv->lock); + irq_chip_eoi_parent(d); } =20 @@ -438,7 +446,7 @@ static struct syscore rzg2l_irqc_syscore =3D { =20 static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, @@ -455,7 +463,7 @@ static const struct irq_chip rzg2l_irqc_irq_chip =3D { =20 static const struct irq_chip rzg2l_irqc_tint_chip =3D { .name =3D "rzg2l-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, @@ -472,7 +480,7 @@ static const struct irq_chip rzg2l_irqc_tint_chip =3D { =20 static const struct irq_chip rzfive_irqc_irq_chip =3D { .name =3D "rzfive-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_irq_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, .irq_disable =3D rzfive_irqc_irq_disable, @@ -489,7 +497,7 @@ static const struct irq_chip rzfive_irqc_irq_chip =3D { =20 static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", - .irq_eoi =3D rzg2l_irqc_eoi, + .irq_eoi =3D rzg2l_irqc_tint_eoi, .irq_mask =3D rzfive_irqc_mask, .irq_unmask =3D rzfive_irqc_unmask, .irq_disable =3D rzfive_irqc_irq_disable, --=20 2.43.0