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Wed, 25 Mar 2026 12:24:58 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v7 05/16] irqchip/renesas-rzg2l: Replace single irq_chip with per-region irq_chip instances Date: Wed, 25 Mar 2026 19:24:20 +0000 Message-ID: <20260325192451.172562-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> References: <20260325192451.172562-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The driver previously used a single irq_chip instance shared across all interrupt types, relying on dispatcher callbacks to differentiate between IRQ and TINT regions at runtime. Replace the per-SoC irq_chip and its dispatcher callbacks with dedicated irq_chip instances for each interrupt region: IRQ and TINT. Subsequent patches will add per-region callbacks for IRQ and TINT from the common code. Signed-off-by: Biju Das --- v6->v7: * No change. v5->v6: * No change. v5: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 61 ++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 8587d4c5f110..1d1df4953368 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -71,14 +71,16 @@ struct rzg2l_irqc_reg_cache { /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address - * @irqchip: Pointer to struct irq_chip + * @irq_chip: Pointer to struct irq_chip for irq + * @tint_chip: Pointer to struct irq_chip for tint * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { void __iomem *base; - const struct irq_chip *irqchip; + const struct irq_chip *irq_chip; + const struct irq_chip *tint_chip; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; @@ -434,7 +436,7 @@ static struct syscore rzg2l_irqc_syscore =3D { .ops =3D &rzg2l_irqc_syscore_ops, }; =20 -static const struct irq_chip rzg2l_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D irq_chip_mask_parent, @@ -451,7 +453,41 @@ static const struct irq_chip rzg2l_irqc_chip =3D { IRQCHIP_SKIP_SET_WAKE, }; =20 -static const struct irq_chip rzfive_irqc_chip =3D { +static const struct irq_chip rzg2l_irqc_tint_chip =3D { + .name =3D "rzg2l-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzg2l_irqc_irq_disable, + .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_irq_chip =3D { + .name =3D "rzfive-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D rzfive_irqc_mask, + .irq_unmask =3D rzfive_irqc_unmask, + .irq_disable =3D rzfive_irqc_irq_disable, + .irq_enable =3D rzfive_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static const struct irq_chip rzfive_irqc_tint_chip =3D { .name =3D "rzfive-irqc", .irq_eoi =3D rzg2l_irqc_eoi, .irq_mask =3D rzfive_irqc_mask, @@ -472,6 +508,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, unsigned int nr_irqs, void *arg) { struct rzg2l_irqc_priv *priv =3D domain->host_data; + const struct irq_chip *chip; unsigned long tint =3D 0; irq_hw_number_t hwirq; unsigned int type; @@ -491,13 +528,15 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain= , unsigned int virq, if (hwirq > IRQC_IRQ_COUNT) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); + chip =3D priv->tint_chip; + } else { + chip =3D priv->irq_chip; } =20 if (hwirq > (IRQC_NUM_IRQ - 1)) return -EINVAL; =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, - (void *)(uintptr_t)tint); + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)= (uintptr_t)tint); if (ret) return ret; =20 @@ -529,7 +568,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, } =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, - const struct irq_chip *irq_chip) + const struct irq_chip *irq_chip, + const struct irq_chip *tint_chip) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -545,7 +585,8 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (!rzg2l_irqc_data) return -ENOMEM; =20 - rzg2l_irqc_data->irqchip =3D irq_chip; + rzg2l_irqc_data->irq_chip =3D irq_chip; + rzg2l_irqc_data->tint_chip =3D tint_chip; =20 rzg2l_irqc_data->base =3D devm_of_iomap(dev, dev->of_node, 0, NULL); if (IS_ERR(rzg2l_irqc_data->base)) @@ -585,12 +626,12 @@ static int rzg2l_irqc_common_probe(struct platform_de= vice *pdev, struct device_n =20 static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l= _irqc_tint_chip); } =20 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfi= ve_irqc_tint_chip); } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) --=20 2.43.0