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Wed, 25 Mar 2026 11:28:56 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:8138:17e4:88b1:468c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4871e5ec998sm11924135e9.6.2026.03.25.11.28.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 11:28:55 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , Claudiu Beznea , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2] pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers Date: Wed, 25 Mar 2026 18:28:47 +0000 Message-ID: <20260325182849.84660-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The rzg2l_pinctrl_pm_setup_regs() handles save/restore of {IOLH,IEN,PUPD,SMT} registers during s2ram, but only for ports where all pins share the same pincfg. Extend the code to also support ports with variable pincfg per pin, so that {IOLH,IEN,PUPD,SMT} registers are correctly saved and restored for all pins. Fixes: 254203f9a94c ("pinctrl: renesas: rzg2l: Add suspend/resume support") Signed-off-by: Biju Das --- v1->v2: * Updated commit description * Improved the logic. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 863e779dda02..e20d199833ee 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3001,9 +3001,12 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l= _pinctrl *pctrl, bool suspen { u32 nports =3D pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; struct rzg2l_pinctrl_reg_cache *cache =3D pctrl->cache; + u32 pin_off =3D 0; =20 - for (u32 port =3D 0; port < nports; port++) { + for (u32 port =3D 0; port < nports; port++, pin_off +=3D RZG2L_PINS_PER_P= ORT) { + const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[pin_off]; bool has_iolh, has_ien, has_pupd, has_smt; + u64 *pin_data =3D pin_desc->drv_data; u32 off, caps; u8 pincnt; u64 cfg; @@ -3012,6 +3015,11 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l= _pinctrl *pctrl, bool suspen off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); pincnt =3D hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); =20 + if (cfg & RZG2L_VARIABLE_CFG) { + for (unsigned int i =3D 1; i < RZG2L_PINS_PER_PORT; i++) + cfg |=3D *pin_data++; + } + caps =3D FIELD_GET(PIN_CFG_MASK, cfg); has_iolh =3D !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C= )); has_ien =3D !!(caps & PIN_CFG_IEN); --=20 2.43.0