From nobody Fri Apr 3 02:58:11 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53C163DEFE6; Wed, 25 Mar 2026 14:42:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774449752; cv=none; b=BCOqqPBRQir5ZVFM7NPuoiCW02NuI0Z5vKroTGpW2HtjB1uC9NNfCk/VpEisbO6O28O553pDWBrnps8Nl/7Jm+85BNwYnRXcKPjc84YzI/NlG5etkcHJBxPoivNzh9mGBNXWyy6X5YWbVhRZRejmwIjYC+DEMoCQSjG2dVlLi/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774449752; c=relaxed/simple; bh=/I/gBBSQjoZsOjIL0B+Qyl0IZTqk8YHRpzEsG7bIEWg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YWZhuvdJEhk/pjzebqgtGzYEf0GaTVvesxPM6EtMri3tIDA/ycr7/65apBUjBfutIYBFLcEcqi2+bLYOOz+NUzbvvwQ72xVoUynzNAog+bwCiqEE2Qh2LUtmEgEFKex8zOiE3jdERq/G/YY7Ln1Teg0M4T6EcYeav8QbdEWDMwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=sSLi+gDn; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="sSLi+gDn" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 09B1A1A2FE8; Wed, 25 Mar 2026 14:42:29 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CD63D601E2; Wed, 25 Mar 2026 14:42:28 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7054910451417; Wed, 25 Mar 2026 15:42:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774449745; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=yHQfhazYClBqFiWTBjKI2wJ8nGAA1W+1s1WNH3rEj08=; b=sSLi+gDngKhTCb3YbcmUiWbH3av4+qM9w25P1wNQ2+ZNTZDJDrQb16tU6NC3qDQvoP/B5p mrkZ/HdKSC3o2WNNqAGRtkxGDRLPYmMdm5ITEtoOOmonZnTH5DANIhpjRAjJhEVnMpal1F nOJi2AsHbEz2dSCDp0YHjMjWxAPWFca2GrhsxRXJVVLlyP47Gm+0gmV4E3XAaXdZmAFVSu WhobF2tbjCCdyJXDj/ANT1yl2i8YjDCmExGB85INBy26P+opFcWZL/Zdkxl8R5Pf1qx+Fy MUeFQVqLPz4V2siBhPKTcgCyegOhp5RWpivj5cyYdJkaL39M6cp109pgCWuNFA== From: Herve Codina To: Andrew Lunn , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Kalle Niemi , Matti Vaittinen , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Michael Turquette , Stephen Boyd , Andi Shyti , Wolfram Sang , Peter Rosin , Arnd Bergmann , Herve Codina , Saravana Kannan , Bjorn Helgaas , Charles Keepax , Richard Fitzgerald , David Rhodes , Linus Walleij , Ulf Hansson , Mark Brown , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Shawn Guo Cc: Wolfram Sang , linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-sound@vger.kernel.org, patches@opensource.cirrus.com, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, linux-spi@vger.kernel.org, linux-acpi@vger.kernel.org, linux-cxl@vger.kernel.org, Allan Nielsen , Horatiu Vultur , Steen Hegelund , Luca Ceresoli , Thomas Petazzoni Subject: [PATCH v6 21/27] misc: lan966x_pci: Split dtso in dtsi/dtso Date: Wed, 25 Mar 2026 15:35:48 +0100 Message-ID: <20260325143555.451852-22-herve.codina@bootlin.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260325143555.451852-1-herve.codina@bootlin.com> References: <20260325143555.451852-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" The lan966x_pci.dtso file contains descriptions related to both the LAN966x PCI device chip and the LAN966x PCI device board where the chip is soldered. Split the file in order to have: - lan966x_pci.dtsi The description related to the PCI chip. - lan966x_pci.dtso The description of the PCI board. Signed-off-by: Herve Codina Reviewed-by: Andrew Lunn --- MAINTAINERS | 1 + drivers/misc/lan966x_pci.dtsi | 130 +++++++++++++++++++++++++ drivers/misc/lan966x_pci.dtso | 175 +++++++--------------------------- 3 files changed, 166 insertions(+), 140 deletions(-) create mode 100644 drivers/misc/lan966x_pci.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 55af015174a5..441fe74e7ef7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17305,6 +17305,7 @@ MICROCHIP LAN966X PCI DRIVER M: Herve Codina S: Maintained F: drivers/misc/lan966x_pci.c +F: drivers/misc/lan966x_pci.dtsi F: drivers/misc/lan966x_pci.dtso =20 MICROCHIP LAN969X ETHERNET DRIVER diff --git a/drivers/misc/lan966x_pci.dtsi b/drivers/misc/lan966x_pci.dtsi new file mode 100644 index 000000000000..170298084fa5 --- /dev/null +++ b/drivers/misc/lan966x_pci.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Microchip UNG + */ + +#include + +cpu_clk: clock-600000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <600000000>; /* CPU clock =3D 600MHz */ +}; + +ddr_clk: clock-30000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <30000000>; /* Fabric clock =3D 30MHz */ +}; + +sys_clk: clock-15625000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <15625000>; /* System clock =3D 15.625MHz */ +}; + +pci-ep-bus@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + /* + * map @0xe2000000 (32MB) to BAR0 (CPU) + * map @0xe0000000 (16MB) to BAR1 (AMBA) + */ + ranges =3D <0xe2000000 0x00 0x00 0x00 0x2000000 + 0xe0000000 0x01 0x00 0x00 0x1000000>; + + switch: switch@e0000000 { + compatible =3D "microchip,lan966x-switch"; + reg =3D <0xe0000000 0x0100000>, + <0xe2000000 0x0800000>; + reg-names =3D "cpu", "gcb"; + interrupt-parent =3D <&oic>; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, + <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "xtr", "ana"; + resets =3D <&reset 0>; + reset-names =3D "switch"; + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + }; + }; + + cpu_ctrl: syscon@e00c0000 { + compatible =3D "microchip,lan966x-cpu-syscon", "syscon"; + reg =3D <0xe00c0000 0xa8>; + }; + + oic: oic@e00c0120 { + compatible =3D "microchip,lan966x-oic"; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D <0>; /* PCI INTx assigned interrupt */ + reg =3D <0xe00c0120 0x190>; + }; + + reset: reset@e200400c { + compatible =3D "microchip,lan966x-switch-reset"; + reg =3D <0xe200400c 0x4>, <0xe00c0000 0xa8>; + reg-names =3D "gcb","cpu"; + #reset-cells =3D <1>; + cpu-syscon =3D <&cpu_ctrl>; + }; + + gpio: pinctrl@e2004064 { + compatible =3D "microchip,lan966x-pinctrl"; + reg =3D <0xe2004064 0xb4>, + <0xe2010024 0x138>; + resets =3D <&reset 0>; + reset-names =3D "switch"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&gpio 0 0 78>; + interrupt-parent =3D <&oic>; + interrupt-controller; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + }; + + mdio1: mdio@e200413c { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "microchip,lan966x-miim"; + reg =3D <0xe200413c 0x24>, + <0xe2010020 0x4>; + resets =3D <&reset 0>; + reset-names =3D "switch"; + status =3D "disabled"; + + lan966x_phy0: ethernet-lan966x_phy@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + lan966x_phy1: ethernet-lan966x_phy@2 { + reg =3D <2>; + status =3D "disabled"; + }; + }; + + serdes: serdes@e202c000 { + compatible =3D "microchip,lan966x-serdes"; + reg =3D <0xe202c000 0x9c>, + <0xe2004010 0x4>; + #phy-cells =3D <2>; + }; +}; diff --git a/drivers/misc/lan966x_pci.dtso b/drivers/misc/lan966x_pci.dtso index 94a967b384f3..3ad50abee72d 100644 --- a/drivers/misc/lan966x_pci.dtso +++ b/drivers/misc/lan966x_pci.dtso @@ -3,10 +3,7 @@ * Copyright (C) 2022 Microchip UNG */ =20 -#include #include -#include -#include #include =20 /dts-v1/; @@ -29,148 +26,46 @@ __overlay__ { #address-cells =3D <3>; #size-cells =3D <2>; =20 - cpu_clk: clock-600000000 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <600000000>; /* CPU clock =3D 600MHz */ - }; - - ddr_clk: clock-30000000 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <30000000>; /* Fabric clock =3D 30MHz */ - }; - - sys_clk: clock-15625000 { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <15625000>; /* System clock =3D 15.625MHz */ - }; - - pci-ep-bus@0 { - compatible =3D "simple-bus"; - #address-cells =3D <1>; - #size-cells =3D <1>; - - /* - * map @0xe2000000 (32MB) to BAR0 (CPU) - * map @0xe0000000 (16MB) to BAR1 (AMBA) - */ - ranges =3D <0xe2000000 0x00 0x00 0x00 0x2000000 - 0xe0000000 0x01 0x00 0x00 0x1000000>; - - switch: switch@e0000000 { - compatible =3D "microchip,lan966x-switch"; - reg =3D <0xe0000000 0x0100000>, - <0xe2000000 0x0800000>; - reg-names =3D "cpu", "gcb"; - - interrupt-parent =3D <&oic>; - interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>, - <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names =3D "xtr", "ana"; - - resets =3D <&reset 0>; - reset-names =3D "switch"; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tod_pins>; - - ethernet-ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port0: port@0 { - phy-handle =3D <&lan966x_phy0>; - - reg =3D <0>; - phy-mode =3D "gmii"; - phys =3D <&serdes 0 CU(0)>; - }; - - port1: port@1 { - phy-handle =3D <&lan966x_phy1>; - - reg =3D <1>; - phy-mode =3D "gmii"; - phys =3D <&serdes 1 CU(1)>; - }; - }; - }; - - cpu_ctrl: syscon@e00c0000 { - compatible =3D "microchip,lan966x-cpu-syscon", "syscon"; - reg =3D <0xe00c0000 0xa8>; - }; - - oic: oic@e00c0120 { - compatible =3D "microchip,lan966x-oic"; - #interrupt-cells =3D <2>; - interrupt-controller; - interrupts =3D <0>; /* PCI INTx assigned interrupt */ - reg =3D <0xe00c0120 0x190>; - }; - - reset: reset@e200400c { - compatible =3D "microchip,lan966x-switch-reset"; - reg =3D <0xe200400c 0x4>, <0xe00c0000 0xa8>; - reg-names =3D "gcb","cpu"; - #reset-cells =3D <1>; - cpu-syscon =3D <&cpu_ctrl>; - }; - - gpio: pinctrl@e2004064 { - compatible =3D "microchip,lan966x-pinctrl"; - reg =3D <0xe2004064 0xb4>, - <0xe2010024 0x138>; - resets =3D <&reset 0>; - reset-names =3D "switch"; - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&gpio 0 0 78>; - interrupt-parent =3D <&oic>; - interrupt-controller; - interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells =3D <2>; + #include "lan966x_pci.dtsi" + }; + }; +}; =20 - tod_pins: tod_pins { - pins =3D "GPIO_36"; - function =3D "ptpsync_1"; - }; +&gpio { + tod_pins: tod_pins { + pins =3D "GPIO_36"; + function =3D "ptpsync_1"; + }; +}; =20 - fc0_a_pins: fcb4-i2c-pins { - /* RXD, TXD */ - pins =3D "GPIO_9", "GPIO_10"; - function =3D "fc0_a"; - }; - }; +&lan966x_phy0 { + status =3D "okay"; +}; =20 - mdio1: mdio@e200413c { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "microchip,lan966x-miim"; - reg =3D <0xe200413c 0x24>, - <0xe2010020 0x4>; +&lan966x_phy1 { + status =3D "okay"; +}; =20 - resets =3D <&reset 0>; - reset-names =3D "switch"; +&mdio1 { + status =3D "okay"; +}; =20 - lan966x_phy0: ethernet-lan966x_phy@1 { - reg =3D <1>; - }; +&port0 { + phy-handle =3D <&lan966x_phy0>; + phy-mode =3D "gmii"; + phys =3D <&serdes 0 CU(0)>; + status =3D "okay"; +}; =20 - lan966x_phy1: ethernet-lan966x_phy@2 { - reg =3D <2>; - }; - }; +&port1 { + phy-handle =3D <&lan966x_phy1>; + phy-mode =3D "gmii"; + phys =3D <&serdes 1 CU(1)>; + status =3D "okay"; +}; =20 - serdes: serdes@e202c000 { - compatible =3D "microchip,lan966x-serdes"; - reg =3D <0xe202c000 0x9c>, - <0xe2004010 0x4>; - #phy-cells =3D <2>; - }; - }; - }; - }; +&switch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tod_pins>; + status =3D "okay"; }; --=20 2.53.0