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charset="utf-8" The existing helper k3_ringacc_ring_get_free() updates the count of free elements only when the software maintained counter decrements to zero. As a result, for batch processing, we may read a lower count of free elements than the actual count. To address this, introduce a new helper that provides realtime count of free elements. Signed-off-by: Siddharth Vadapalli --- drivers/soc/ti/k3-ringacc.c | 11 +++++++++++ include/linux/soc/ti/k3-ringacc.h | 8 ++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 7602b8a909b0..1751d42ee2d3 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -905,6 +905,17 @@ u32 k3_ringacc_ring_get_free(struct k3_ring *ring) } EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_free); =20 +u32 k3_ringacc_ring_get_rt_free(struct k3_ring *ring) +{ + if (!ring || !(ring->flags & K3_RING_FLAG_BUSY)) + return -EINVAL; + + ring->state.free =3D ring->size - k3_ringacc_ring_read_occ(ring); + + return ring->state.free; +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_rt_free); + u32 k3_ringacc_ring_get_occ(struct k3_ring *ring) { if (!ring || !(ring->flags & K3_RING_FLAG_BUSY)) diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ri= ngacc.h index 39b022b92598..091cf551932d 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -184,6 +184,14 @@ u32 k3_ringacc_ring_get_size(struct k3_ring *ring); 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charset="utf-8" To allow pushing and popping a batch of descriptors at once to improve efficiency, introduce two helpers: 1. k3_ringacc_ring_push_batch 2. k3_ringacc_ring_pop_batch Signed-off-by: Siddharth Vadapalli --- drivers/soc/ti/k3-ringacc.c | 88 +++++++++++++++++++++++++++++++ include/linux/soc/ti/k3-ringacc.h | 27 ++++++++++ 2 files changed, 115 insertions(+) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 1751d42ee2d3..33ae7db9c2a1 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -1223,6 +1223,41 @@ int k3_ringacc_ring_push(struct k3_ring *ring, void = *elem) } EXPORT_SYMBOL_GPL(k3_ringacc_ring_push); =20 +int k3_ringacc_ring_push_batch(struct k3_ring *ring, void *elem_arr, + u32 batch_size) +{ + void *elem_ptr, *elem; + int ret =3D 0; + u32 i; + + if (!ring || !(ring->flags & K3_RING_FLAG_BUSY)) + return -EINVAL; + + if (k3_ringacc_ring_get_free(ring) < batch_size) + if (k3_ringacc_ring_get_rt_free(ring) < batch_size) + return -ENOMEM; + + dev_dbg(ring->parent->dev, "ring_push_batch: free%d index%d\n", + ring->state.free, ring->state.windex); + + for (i =3D 0; i < batch_size; i++) { + elem_ptr =3D k3_ringacc_get_elm_addr(ring, ring->state.windex); + elem =3D &((dma_addr_t *)elem_arr)[i]; + memcpy(elem_ptr, elem, (4 << ring->elm_size)); + if (ring->parent->dma_rings) { + u64 *addr =3D elem_ptr; + *addr |=3D ((u64)ring->asel << K3_ADDRESS_ASEL_SHIFT); + } + ring->state.windex =3D (ring->state.windex + 1) % ring->size; + } + + ring->state.free -=3D batch_size; + writel(batch_size, &ring->rt->db); + + return ret; +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_push_batch); + int k3_ringacc_ring_push_head(struct k3_ring *ring, void *elem) { int ret =3D -EOPNOTSUPP; @@ -1266,6 +1301,59 @@ int k3_ringacc_ring_pop(struct k3_ring *ring, void *= elem) } EXPORT_SYMBOL_GPL(k3_ringacc_ring_pop); =20 +int k3_ringacc_ring_pop_batch(struct k3_ring *ring, void *elem_arr, + u32 *batch_size, u32 max_batch) +{ + void *elem_ptr, *elem; + u32 ring_occupancy, i; + u32 num_to_pop; + + if (!ring || !(ring->flags & K3_RING_FLAG_BUSY)) + return -EINVAL; + + if (!ring->state.occ || ring->state.occ < max_batch) + k3_ringacc_ring_update_occ(ring); + + if (!ring->state.occ) { + if (likely(!ring->state.tdown_complete)) + return -ENODATA; + + /* Handle teardown */ + elem =3D &((dma_addr_t *)elem_arr)[0]; + dma_addr_t *value =3D elem; + *value =3D CPPI5_TDCM_MARKER; + writel(K3_DMARING_RT_DB_TDOWN_ACK, &ring->rt->db); + ring->state.tdown_complete =3D false; + *batch_size =3D 1; + return 0; + } + + ring_occupancy =3D ring->state.occ; + if (ring_occupancy > max_batch) + num_to_pop =3D max_batch; + else + num_to_pop =3D ring_occupancy; + + dev_dbg(ring->parent->dev, "ring_pop_batch: occ%d index%d\n", + ring->state.occ, ring->state.rindex); + + for (i =3D 0; i < num_to_pop; i++) { + elem_ptr =3D k3_ringacc_get_elm_addr(ring, ring->state.rindex); + elem =3D &((dma_addr_t *)elem_arr)[i]; + memcpy(elem, elem_ptr, (4 << ring->elm_size)); + k3_dmaring_remove_asel_from_elem(elem); + ring->state.rindex =3D (ring->state.rindex + 1) % ring->size; + dev_dbg(ring->parent->dev, "occ%d index%d pos_ptr%p\n", + ring->state.occ, ring->state.rindex, elem_ptr); + } + ring->state.occ -=3D num_to_pop; + writel(-1 * num_to_pop, &ring->rt->db); + *batch_size =3D num_to_pop; + + return 0; +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_pop_batch); + int k3_ringacc_ring_pop_tail(struct k3_ring *ring, void *elem) { int ret =3D -EOPNOTSUPP; diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ri= ngacc.h index 091cf551932d..6fffa65ee760 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -220,6 +220,19 @@ u32 k3_ringacc_ring_is_full(struct k3_ring *ring); */ int k3_ringacc_ring_push(struct k3_ring *ring, void *elem); =20 +/** + * k3_ringacc_ring_push_batch - push a batch of elements to the ring tail + * @ring: pointer on ring + * @elem_arr: pointer to array of ring element buffers + * @batch_size: count of element buffers to be pushed + * + * Push the batch of element buffers to the ring tail. + * + * Returns 0 on success, errno otherwise. + */ +int k3_ringacc_ring_push_batch(struct k3_ring *ring, void *elem_arr, + u32 batch_size); + /** * k3_ringacc_ring_pop - pop element from the ring head * @ring: pointer on ring @@ -232,6 +245,20 @@ int k3_ringacc_ring_push(struct k3_ring *ring, void *e= lem); */ int k3_ringacc_ring_pop(struct k3_ring *ring, void *elem); =20 +/** + * k3_ringacc_ring_pop_batch - pop all elements from the ring head + * @ring: pointer on ring + * @elem_ar: pointer to array of ring element buffers + * @batch_size: pointer to count of elements popped from ring + * @max_batch: maximum number of elements to pop + * + * Pop a batch of element buffers from the ring head. + * + * Returns 0 on success, errno otherwise. + */ +int k3_ringacc_ring_pop_batch(struct k3_ring *ring, void *elem_arr, + u32 *batch_size, u32 max_batch); + /** * k3_ringacc_ring_push_head - push element to the ring head * @ring: pointer on ring --=20 2.51.1 From nobody Fri Apr 3 01:29:34 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010054.outbound.protection.outlook.com [52.101.46.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 195603D4132; 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charset="utf-8" To allow pushing and popping a batch of DMA Descriptors on the Transmit and Receive DMA Channels (Flows), introduce four helpers: 1. k3_udma_glue_push_tx_chn_batch 2. k3_udma_glue_pop_tx_chn_batch 3. k3_udma_glue_push_rx_chn_batch 4. k3_udma_glue_pop_rx_chn_batch Signed-off-by: Siddharth Vadapalli --- drivers/dma/ti/k3-udma-glue.c | 55 ++++++++++++++++++++++++++++++++ include/linux/dma/k3-udma-glue.h | 12 +++++++ 2 files changed, 67 insertions(+) diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c index f87d244cc2d6..15835c521977 100644 --- a/drivers/dma/ti/k3-udma-glue.c +++ b/drivers/dma/ti/k3-udma-glue.c @@ -485,6 +485,25 @@ int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_ch= annel *tx_chn, } EXPORT_SYMBOL_GPL(k3_udma_glue_push_tx_chn); =20 +int k3_udma_glue_push_tx_chn_batch(struct k3_udma_glue_tx_channel *tx_chn, + struct cppi5_host_desc_t **desc_tx, + dma_addr_t *desc_dma, u32 batch_size) +{ + u32 ringtxcq_id; + int i; + + if (!atomic_add_unless(&tx_chn->free_pkts, -1 * batch_size, 0)) + return -ENOMEM; + + ringtxcq_id =3D k3_ringacc_get_ring_id(tx_chn->ringtxcq); + + for (i =3D 0; i < batch_size; i++) + cppi5_desc_set_retpolicy(&desc_tx[i]->hdr, 0, ringtxcq_id); + + return k3_ringacc_ring_push_batch(tx_chn->ringtx, desc_dma, batch_size); +} +EXPORT_SYMBOL_GPL(k3_udma_glue_push_tx_chn_batch); + int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, dma_addr_t *desc_dma) { @@ -498,6 +517,21 @@ int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_cha= nnel *tx_chn, } EXPORT_SYMBOL_GPL(k3_udma_glue_pop_tx_chn); =20 +int k3_udma_glue_pop_tx_chn_batch(struct k3_udma_glue_tx_channel *tx_chn, + dma_addr_t *desc_dma, u32 *batch_size, + u32 max_batch) +{ + int ret; + + ret =3D k3_ringacc_ring_pop_batch(tx_chn->ringtxcq, desc_dma, batch_size, + max_batch); + if (!ret) + atomic_add(*batch_size, &tx_chn->free_pkts); + + return ret; +} +EXPORT_SYMBOL_GPL(k3_udma_glue_pop_tx_chn_batch); + int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) { int ret; @@ -1512,6 +1546,16 @@ int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_= channel *rx_chn, } EXPORT_SYMBOL_GPL(k3_udma_glue_push_rx_chn); =20 +int k3_udma_glue_push_rx_chn_batch(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, dma_addr_t desc_dma, + u32 batch_size) +{ + struct k3_udma_glue_rx_flow *flow =3D &rx_chn->flows[flow_num]; + + return k3_ringacc_ring_push_batch(flow->ringrxfdq, &desc_dma, batch_size); +} +EXPORT_SYMBOL_GPL(k3_udma_glue_push_rx_chn_batch); + int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, u32 flow_num, dma_addr_t *desc_dma) { @@ -1521,6 +1565,17 @@ int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_c= hannel *rx_chn, } EXPORT_SYMBOL_GPL(k3_udma_glue_pop_rx_chn); =20 +int k3_udma_glue_pop_rx_chn_batch(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, dma_addr_t *desc_dma, + u32 *batch_size, u32 max_batch) +{ + struct k3_udma_glue_rx_flow *flow =3D &rx_chn->flows[flow_num]; + + return k3_ringacc_ring_pop_batch(flow->ringrx, desc_dma, batch_size, + max_batch); +} +EXPORT_SYMBOL_GPL(k3_udma_glue_pop_rx_chn_batch); + int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn, u32 flow_num) { diff --git a/include/linux/dma/k3-udma-glue.h b/include/linux/dma/k3-udma-g= lue.h index 5d43881e6fb7..9fe3f51c230c 100644 --- a/include/linux/dma/k3-udma-glue.h +++ b/include/linux/dma/k3-udma-glue.h @@ -35,8 +35,14 @@ void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_= channel *tx_chn); int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, struct cppi5_host_desc_t *desc_tx, dma_addr_t desc_dma); +int k3_udma_glue_push_tx_chn_batch(struct k3_udma_glue_tx_channel *tx_chn, + struct cppi5_host_desc_t **desc_tx, + dma_addr_t *desc_dma, u32 batch_size); int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, dma_addr_t *desc_dma); +int k3_udma_glue_pop_tx_chn_batch(struct k3_udma_glue_tx_channel *tx_chn, + dma_addr_t *desc_dma, u32 *batch_size, + u32 max_batch); int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn); void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn); void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, @@ -127,8 +133,14 @@ void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_= channel *rx_chn, int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, u32 flow_num, struct cppi5_host_desc_t *desc_tx, dma_addr_t desc_dma); +int k3_udma_glue_push_rx_chn_batch(struct k3_udma_glue_rx_channel *rx_chn, + u32 flow_num, dma_addr_t desc_dma, + u32 batch_size); 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charset="utf-8" There are two kinds of descriptors: 1. Host Packet Descriptor 2. Host Buffer Descriptor Unfragmented SKBs are always associated with a single Host Packet Descriptor. Fragmented SKBs on the other hand have the Start-of-Packet SKB associated with a single Host Packet Descriptor and the remaining fragments are associated with a Host Buffer Descriptor. A single Host Packet Descriptor is linked to a chain of Host Buffer Descriptors for fragmented SKBs with as many Host Buffer Descriptors as the number of SKB fragments. Since packet completion handling only uses the buffer type of the Host Packet Descriptor, setting the buffer type of the linked Host Buffer Descriptors is an unnecessary operation which wastes CPU cycles per SKB fragment. Hence, do not set buffer type for SKB fragments. Signed-off-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/etherne= t/ti/am65-cpsw-nuss.c index d9400599e80a..6df6cb52d952 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -1678,9 +1678,6 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(stru= ct sk_buff *skb, goto busy_free_descs; } =20 - am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, - AM65_CPSW_TX_BUF_TYPE_SKB); - buf_dma =3D skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { --=20 2.51.1 From nobody Fri Apr 3 01:29:34 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011010.outbound.protection.outlook.com [52.101.52.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFAA93D6479; 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charset="utf-8" The existing implementation allocates the CPPI Descriptors from the Descriptor Pool of the TX and RX Channels on demand and returns them to the Pool on completion. Recycle descriptors to speed up the transmit and receive paths. Use a Cyclic Queue (Ring) to hold the TX and RX Descriptors for the respective TX Channel and RX Flow and utilize atomic operations for guarding against concurrent modification. Signed-off-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 237 ++++++++++++++++++++--- drivers/net/ethernet/ti/am65-cpsw-nuss.h | 19 ++ 2 files changed, 233 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/etherne= t/ti/am65-cpsw-nuss.c index 6df6cb52d952..fc165579a479 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -145,9 +145,6 @@ AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) =20 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 -/* Number of TX/RX descriptors per channel/flow */ -#define AM65_CPSW_MAX_TX_DESC 500 -#define AM65_CPSW_MAX_RX_DESC 500 =20 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 @@ -374,6 +371,122 @@ static void am65_cpsw_slave_set_promisc(struct am65_c= psw_port *port, } } =20 +static size_t am65_cpsw_nuss_num_free_tx_desc(struct am65_cpsw_tx_chn *tx_= chn) +{ + struct am65_cpsw_tx_ring *tx_ring =3D &tx_chn->tx_ring; + int head_idx, tail_idx, num_free; + + /* Atomically read both head and tail indices */ + head_idx =3D atomic_read(&tx_ring->tx_desc_ring_head_idx); + tail_idx =3D atomic_read(&tx_ring->tx_desc_ring_tail_idx); + + /* Calculate number of available descriptors in circular queue */ + num_free =3D (tail_idx - head_idx + (AM65_CPSW_MAX_TX_DESC + 1)) % + (AM65_CPSW_MAX_TX_DESC + 1); + + return num_free; +} + +static void am65_cpsw_nuss_put_tx_desc(struct am65_cpsw_tx_chn *tx_chn, + struct cppi5_host_desc_t *desc) +{ + struct am65_cpsw_tx_ring *tx_ring =3D &tx_chn->tx_ring; + int tail_idx, new_tail_idx; + + /* Atomically get current tail index and calculate new wrapped index */ + do { + tail_idx =3D atomic_read(&tx_ring->tx_desc_ring_tail_idx); + new_tail_idx =3D tail_idx + 1; + if (new_tail_idx > AM65_CPSW_MAX_TX_DESC) + new_tail_idx =3D 0; + } while (atomic_cmpxchg(&tx_ring->tx_desc_ring_tail_idx, + tail_idx, new_tail_idx) !=3D tail_idx); + + /* Store the descriptor at the tail position */ + tx_ring->tx_descs[tail_idx] =3D desc; +} + +static void am65_cpsw_nuss_put_rx_desc(struct am65_cpsw_rx_flow *flow, + struct cppi5_host_desc_t *desc) +{ + struct am65_cpsw_rx_ring *rx_ring =3D &flow->rx_ring; + int tail_idx, new_tail_idx; + + /* Atomically get current tail index and calculate new wrapped index */ + do { + tail_idx =3D atomic_read(&rx_ring->rx_desc_ring_tail_idx); + new_tail_idx =3D tail_idx + 1; + if (new_tail_idx > AM65_CPSW_MAX_RX_DESC) + new_tail_idx =3D 0; + } while (atomic_cmpxchg(&rx_ring->rx_desc_ring_tail_idx, + tail_idx, new_tail_idx) !=3D tail_idx); + + /* Store the descriptor at the tail position */ + rx_ring->rx_descs[tail_idx] =3D desc; +} + +static void *am65_cpsw_nuss_get_tx_desc(struct am65_cpsw_tx_chn *tx_chn) +{ + struct am65_cpsw_tx_ring *tx_ring =3D &tx_chn->tx_ring; + int head_idx, tail_idx, new_head_idx; + + /* Atomically get current head index and check if queue is empty */ + do { + head_idx =3D atomic_read(&tx_ring->tx_desc_ring_head_idx); + tail_idx =3D atomic_read(&tx_ring->tx_desc_ring_tail_idx); + + /* Queue is empty when head =3D=3D tail */ + if (head_idx =3D=3D tail_idx) + return NULL; + + /* Calculate new head with wraparound */ + new_head_idx =3D head_idx + 1; + if (new_head_idx > AM65_CPSW_MAX_TX_DESC) + new_head_idx =3D 0; + + } while (atomic_cmpxchg(&tx_ring->tx_desc_ring_head_idx, + head_idx, new_head_idx) !=3D head_idx); + + return tx_ring->tx_descs[head_idx]; +} + +static void *am65_cpsw_nuss_get_rx_desc(struct am65_cpsw_rx_flow *flow) +{ + struct am65_cpsw_rx_ring *rx_ring =3D &flow->rx_ring; + int head_idx, tail_idx, new_head_idx; + + /* Atomically get current head index and check if queue is empty */ + do { + head_idx =3D atomic_read(&rx_ring->rx_desc_ring_head_idx); + tail_idx =3D atomic_read(&rx_ring->rx_desc_ring_tail_idx); + + /* Queue is empty when head =3D=3D tail */ + if (head_idx =3D=3D tail_idx) + return NULL; + + /* Calculate new head with wraparound */ + new_head_idx =3D head_idx + 1; + if (new_head_idx > AM65_CPSW_MAX_RX_DESC) + new_head_idx =3D 0; + + } while (atomic_cmpxchg(&rx_ring->rx_desc_ring_head_idx, + head_idx, new_head_idx) !=3D head_idx); + + return rx_ring->rx_descs[head_idx]; +} + +static inline int am65_cpsw_nuss_tx_descs_available(struct am65_cpsw_tx_ch= n *tx_chn) +{ + struct am65_cpsw_tx_ring *tx_ring =3D &tx_chn->tx_ring; + int head_idx, tail_idx; + + head_idx =3D atomic_read(&tx_ring->tx_desc_ring_head_idx); + tail_idx =3D atomic_read(&tx_ring->tx_desc_ring_tail_idx); + + return (tail_idx - head_idx + (AM65_CPSW_MAX_TX_DESC + 1)) % + (AM65_CPSW_MAX_TX_DESC + 1); +} + static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) { struct am65_cpsw_common *common =3D am65_ndev_to_common(ndev); @@ -423,7 +536,7 @@ static void am65_cpsw_nuss_ndo_host_tx_timeout(struct n= et_device *ndev, netif_tx_queue_stopped(netif_txq), jiffies_to_msecs(jiffies - trans_start), netdev_queue_dql_avail(netif_txq), - k3_cppi_desc_pool_avail(tx_chn->desc_pool)); + am65_cpsw_nuss_num_free_tx_desc(tx_chn)); =20 if (netif_tx_queue_stopped(netif_txq)) { /* try recover if stopped by us */ @@ -442,7 +555,7 @@ static int am65_cpsw_nuss_rx_push(struct am65_cpsw_comm= on *common, dma_addr_t desc_dma; dma_addr_t buf_dma; =20 - desc_rx =3D k3_cppi_desc_pool_alloc(rx_chn->desc_pool); + desc_rx =3D am65_cpsw_nuss_get_rx_desc(&rx_chn->flows[flow_idx]); if (!desc_rx) { dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); return -ENOMEM; @@ -453,7 +566,7 @@ static int am65_cpsw_nuss_rx_push(struct am65_cpsw_comm= on *common, page_address(page) + AM65_CPSW_HEADROOM, AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { - k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); + am65_cpsw_nuss_put_rx_desc(&rx_chn->flows[flow_idx], desc_rx); dev_err(dev, "Failed to map rx buffer\n"); return -EINVAL; } @@ -508,6 +621,7 @@ static void am65_cpsw_nuss_tx_cleanup(void *data, dma_a= ddr_t desc_dma); static void am65_cpsw_destroy_rxq(struct am65_cpsw_common *common, int id) { struct am65_cpsw_rx_chn *rx_chn =3D &common->rx_chns; + struct cppi5_host_desc_t *rx_desc; struct am65_cpsw_rx_flow *flow; struct xdp_rxq_info *rxq; int port; @@ -515,6 +629,12 @@ static void am65_cpsw_destroy_rxq(struct am65_cpsw_com= mon *common, int id) flow =3D &rx_chn->flows[id]; napi_disable(&flow->napi_rx); hrtimer_cancel(&flow->rx_hrtimer); + /* return descriptors to pool */ + rx_desc =3D am65_cpsw_nuss_get_rx_desc(flow); + while (rx_desc) { + k3_cppi_desc_pool_free(rx_chn->desc_pool, rx_desc); + rx_desc =3D am65_cpsw_nuss_get_rx_desc(flow); + } k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, id, rx_chn, am65_cpsw_nuss_rx_cleanup); =20 @@ -603,7 +723,12 @@ static int am65_cpsw_create_rxq(struct am65_cpsw_commo= n *common, int id) goto err; } =20 + /* Preallocate all RX Descriptors */ + atomic_set(&flow->rx_ring.rx_desc_ring_head_idx, 0); + atomic_set(&flow->rx_ring.rx_desc_ring_tail_idx, AM65_CPSW_MAX_RX_DESC); + for (i =3D 0; i < AM65_CPSW_MAX_RX_DESC; i++) { + flow->rx_ring.rx_descs[i] =3D k3_cppi_desc_pool_alloc(rx_chn->desc_pool); page =3D page_pool_dev_alloc_pages(flow->page_pool); if (!page) { dev_err(common->dev, "cannot allocate page in flow %d\n", @@ -661,9 +786,16 @@ static int am65_cpsw_create_rxqs(struct am65_cpsw_comm= on *common) static void am65_cpsw_destroy_txq(struct am65_cpsw_common *common, int id) { struct am65_cpsw_tx_chn *tx_chn =3D &common->tx_chns[id]; + struct cppi5_host_desc_t *tx_desc; =20 napi_disable(&tx_chn->napi_tx); hrtimer_cancel(&tx_chn->tx_hrtimer); + /* return descriptors to pool */ + tx_desc =3D am65_cpsw_nuss_get_tx_desc(tx_chn); + while (tx_desc) { + k3_cppi_desc_pool_free(tx_chn->desc_pool, tx_desc); + tx_desc =3D am65_cpsw_nuss_get_tx_desc(tx_chn); + } k3_udma_glue_reset_tx_chn(tx_chn->tx_chn, tx_chn, am65_cpsw_nuss_tx_cleanup); k3_udma_glue_disable_tx_chn(tx_chn->tx_chn); @@ -695,7 +827,13 @@ static void am65_cpsw_destroy_txqs(struct am65_cpsw_co= mmon *common) static int am65_cpsw_create_txq(struct am65_cpsw_common *common, int id) { struct am65_cpsw_tx_chn *tx_chn =3D &common->tx_chns[id]; - int ret; + int ret, i; + + /* Preallocate all TX Descriptors */ + atomic_set(&tx_chn->tx_ring.tx_desc_ring_head_idx, 0); + atomic_set(&tx_chn->tx_ring.tx_desc_ring_tail_idx, AM65_CPSW_MAX_TX_DESC); + for (i =3D 0; i < AM65_CPSW_MAX_TX_DESC; i++) + tx_chn->tx_ring.tx_descs[i] =3D k3_cppi_desc_pool_alloc(tx_chn->desc_poo= l); =20 ret =3D k3_udma_glue_enable_tx_chn(tx_chn->tx_chn); if (ret) @@ -1103,7 +1241,7 @@ static int am65_cpsw_xdp_tx_frame(struct net_device *= ndev, u32 pkt_len =3D xdpf->len; int ret; =20 - host_desc =3D k3_cppi_desc_pool_alloc(tx_chn->desc_pool); + host_desc =3D am65_cpsw_nuss_get_tx_desc(tx_chn); if (unlikely(!host_desc)) { ndev->stats.tx_dropped++; return AM65_CPSW_XDP_CONSUMED; /* drop */ @@ -1161,7 +1299,7 @@ static int am65_cpsw_xdp_tx_frame(struct net_device *= ndev, k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); pool_free: - k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); + am65_cpsw_nuss_put_tx_desc(tx_chn, host_desc); return ret; } =20 @@ -1320,7 +1458,7 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw= _rx_flow *flow, dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); =20 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); - k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); + am65_cpsw_nuss_put_rx_desc(flow, desc_rx); =20 if (port->xdp_prog) { xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq[flow->id]); @@ -1444,13 +1582,48 @@ static void am65_cpsw_nuss_tx_wake(struct am65_cpsw= _tx_chn *tx_chn, struct net_d */ __netif_tx_lock(netif_txq, smp_processor_id()); if (netif_running(ndev) && - (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=3D MAX_SKB_FRAGS)) + (am65_cpsw_nuss_num_free_tx_desc(tx_chn) >=3D MAX_SKB_FRAGS)) netif_tx_wake_queue(netif_txq); =20 __netif_tx_unlock(netif_txq); } } =20 +static inline void am65_cpsw_nuss_xmit_recycle(struct am65_cpsw_tx_chn *tx= _chn, + struct cppi5_host_desc_t *desc) +{ + struct cppi5_host_desc_t *first_desc, *next_desc; + dma_addr_t buf_dma, next_desc_dma; + u32 buf_dma_len; + + first_desc =3D desc; + next_desc =3D first_desc; + + cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); + + dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); + + next_desc_dma =3D cppi5_hdesc_get_next_hbdesc(first_desc); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); + while (next_desc_dma) { + next_desc =3D k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, + next_desc_dma); + cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); + + dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, + DMA_TO_DEVICE); + + next_desc_dma =3D cppi5_hdesc_get_next_hbdesc(next_desc); + k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); + + am65_cpsw_nuss_put_tx_desc(tx_chn, next_desc); + } + + am65_cpsw_nuss_put_tx_desc(tx_chn, first_desc); +} + static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, int chn, unsigned int budget, bool *tdown) { @@ -1509,7 +1682,7 @@ static int am65_cpsw_nuss_tx_compl_packets(struct am6= 5_cpsw_common *common, =20 total_bytes +=3D pkt_len; num_tx++; - am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); + am65_cpsw_nuss_xmit_recycle(tx_chn, desc_tx); dev_sw_netstats_tx_add(ndev, 1, pkt_len); if (!single_port) { /* as packets from multi ports can be interleaved @@ -1624,7 +1797,7 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(stru= ct sk_buff *skb, goto err_free_skb; } =20 - first_desc =3D k3_cppi_desc_pool_alloc(tx_chn->desc_pool); + first_desc =3D am65_cpsw_nuss_get_tx_desc(tx_chn); if (!first_desc) { dev_dbg(dev, "Failed to allocate descriptor\n"); dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, @@ -1672,7 +1845,7 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(stru= ct sk_buff *skb, skb_frag_t *frag =3D &skb_shinfo(skb)->frags[i]; u32 frag_size =3D skb_frag_size(frag); =20 - next_desc =3D k3_cppi_desc_pool_alloc(tx_chn->desc_pool); + next_desc =3D am65_cpsw_nuss_get_tx_desc(tx_chn); if (!next_desc) { dev_err(dev, "Failed to allocate descriptor\n"); goto busy_free_descs; @@ -1682,7 +1855,7 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(stru= ct sk_buff *skb, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { dev_err(dev, "Failed to map tx skb page\n"); - k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); + am65_cpsw_nuss_put_tx_desc(tx_chn, next_desc); ndev->stats.tx_errors++; goto err_free_descs; } @@ -1725,14 +1898,14 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(st= ruct sk_buff *skb, goto err_free_descs; } =20 - if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { + if (am65_cpsw_nuss_num_free_tx_desc(tx_chn) < MAX_SKB_FRAGS) { netif_tx_stop_queue(netif_txq); /* Barrier, so that stop_queue visible to other cpus */ smp_mb__after_atomic(); dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); =20 /* re-check for smp */ - if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=3D + if (am65_cpsw_nuss_num_free_tx_desc(tx_chn) >=3D MAX_SKB_FRAGS) { netif_tx_wake_queue(netif_txq); dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); @@ -1742,14 +1915,14 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(st= ruct sk_buff *skb, return NETDEV_TX_OK; =20 err_free_descs: - am65_cpsw_nuss_xmit_free(tx_chn, first_desc); + am65_cpsw_nuss_xmit_recycle(tx_chn, first_desc); err_free_skb: ndev->stats.tx_dropped++; dev_kfree_skb_any(skb); return NETDEV_TX_OK; =20 busy_free_descs: - am65_cpsw_nuss_xmit_free(tx_chn, first_desc); + am65_cpsw_nuss_xmit_recycle(tx_chn, first_desc); busy_stop_q: netif_tx_stop_queue(netif_txq); return NETDEV_TX_BUSY; @@ -2195,7 +2368,7 @@ static void am65_cpsw_nuss_free_tx_chns(void *data) static void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) { struct device *dev =3D common->dev; - int i; + int i, j; =20 common->tx_ch_rate_msk =3D 0; for (i =3D 0; i < common->tx_ch_num; i++) { @@ -2205,6 +2378,10 @@ static void am65_cpsw_nuss_remove_tx_chns(struct am6= 5_cpsw_common *common) devm_free_irq(dev, tx_chn->irq, tx_chn); =20 netif_napi_del(&tx_chn->napi_tx); + + for (j =3D 0; j < AM65_CPSW_MAX_TX_DESC; j++) + k3_cppi_desc_pool_free(tx_chn->desc_pool, + tx_chn->tx_ring.tx_descs[j]); } =20 am65_cpsw_nuss_free_tx_chns(common); @@ -2260,7 +2437,7 @@ static int am65_cpsw_nuss_init_tx_chns(struct am65_cp= sw_common *common) .flags =3D 0 }; u32 hdesc_size, hdesc_size_out; - int i, ret =3D 0; + int i, j, ret =3D 0; =20 hdesc_size =3D cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, AM65_CPSW_NAV_SW_DATA_SIZE); @@ -2329,6 +2506,13 @@ static int am65_cpsw_nuss_init_tx_chns(struct am65_c= psw_common *common) return 0; =20 err: + /* Free descriptors */ + while (i--) { + struct am65_cpsw_tx_chn *tx_chn =3D &common->tx_chns[i]; + + for (j =3D 0; j < AM65_CPSW_MAX_TX_DESC; j++) + k3_cppi_desc_pool_free(tx_chn->desc_pool, tx_chn->tx_ring.tx_descs[j]); + } am65_cpsw_nuss_free_tx_chns(common); =20 return ret; @@ -2353,7 +2537,7 @@ static void am65_cpsw_nuss_remove_rx_chns(struct am65= _cpsw_common *common) struct device *dev =3D common->dev; struct am65_cpsw_rx_chn *rx_chn; struct am65_cpsw_rx_flow *flows; - int i; + int i, j; =20 rx_chn =3D &common->rx_chns; flows =3D rx_chn->flows; @@ -2362,6 +2546,9 @@ static void am65_cpsw_nuss_remove_rx_chns(struct am65= _cpsw_common *common) if (!(flows[i].irq < 0)) devm_free_irq(dev, flows[i].irq, &flows[i]); netif_napi_del(&flows[i].napi_rx); + for (j =3D 0; j < AM65_CPSW_MAX_RX_DESC; j++) + k3_cppi_desc_pool_free(rx_chn->desc_pool, + flows[i].rx_ring.rx_descs[j]); } =20 am65_cpsw_nuss_free_rx_chns(common); @@ -2378,7 +2565,7 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cp= sw_common *common) struct am65_cpsw_rx_flow *flow; u32 hdesc_size, hdesc_size_out; u32 fdqring_id; - int i, ret =3D 0; + int i, j, ret =3D 0; =20 hdesc_size =3D cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, AM65_CPSW_NAV_SW_DATA_SIZE); @@ -2498,10 +2685,14 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_= cpsw_common *common) =20 err_request_irq: netif_napi_del(&flow->napi_rx); + for (j =3D 0; j < AM65_CPSW_MAX_RX_DESC; j++) + k3_cppi_desc_pool_free(rx_chn->desc_pool, flow->rx_ring.rx_descs[j]); =20 err_flow: for (--i; i >=3D 0; i--) { flow =3D &rx_chn->flows[i]; + for (j =3D 0; j < AM65_CPSW_MAX_RX_DESC; j++) + k3_cppi_desc_pool_free(rx_chn->desc_pool, flow->rx_ring.rx_descs[j]); devm_free_irq(dev, flow->irq, flow); netif_napi_del(&flow->napi_rx); } diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/etherne= t/ti/am65-cpsw-nuss.h index 7750448e4746..e64b4cfd6f2c 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -6,6 +6,7 @@ #ifndef AM65_CPSW_NUSS_H_ #define AM65_CPSW_NUSS_H_ =20 +#include #include #include #include @@ -23,6 +24,10 @@ struct am65_cpts; =20 #define AM65_CPSW_MAX_QUEUES 8 /* both TX & RX */ =20 +/* Number of TX/RX descriptors per channel/flow */ +#define AM65_CPSW_MAX_TX_DESC 500 +#define AM65_CPSW_MAX_RX_DESC 500 + #define AM65_CPSW_PORT_VLAN_REG_OFFSET 0x014 =20 struct am65_cpsw_slave_data { @@ -75,6 +80,12 @@ struct am65_cpsw_host { u32 vid_context; }; =20 +struct am65_cpsw_tx_ring { + struct cppi5_host_desc_t *tx_descs[AM65_CPSW_MAX_TX_DESC + 1]; + atomic_t tx_desc_ring_head_idx; /* Points to dequeuing place for free des= criptor */ + atomic_t tx_desc_ring_tail_idx; /* Points to queuing place for freed desc= riptor */ +}; + struct am65_cpsw_tx_chn { struct device *dma_dev; struct napi_struct napi_tx; @@ -82,6 +93,7 @@ struct am65_cpsw_tx_chn { struct k3_cppi_desc_pool *desc_pool; struct k3_udma_glue_tx_channel *tx_chn; spinlock_t lock; /* protect TX rings in multi-port mode */ + struct am65_cpsw_tx_ring tx_ring; struct hrtimer tx_hrtimer; unsigned long tx_pace_timeout; int irq; @@ -92,12 +104,19 @@ struct am65_cpsw_tx_chn { u32 rate_mbps; }; =20 +struct am65_cpsw_rx_ring { + struct cppi5_host_desc_t *rx_descs[AM65_CPSW_MAX_RX_DESC + 1]; + atomic_t rx_desc_ring_head_idx; /* Points to dequeuing place for free des= criptor */ + atomic_t rx_desc_ring_tail_idx; /* Points to queuing place for freed desc= riptor */ +}; + struct am65_cpsw_rx_flow { u32 id; struct napi_struct napi_rx; struct am65_cpsw_common *common; int irq; bool irq_disabled; + struct am65_cpsw_rx_ring rx_ring; struct hrtimer rx_hrtimer; unsigned long rx_pace_timeout; struct page_pool *page_pool; --=20 2.51.1 From nobody Fri Apr 3 01:29:34 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010004.outbound.protection.outlook.com [52.101.46.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E97583D649F; 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charset="utf-8" Enable batch processing on the transmit and transmit completion paths by submitting a batch of packet descriptors on transmit and similarly by dequeueing a batch of packet descriptors on transmit completion. Signed-off-by: Siddharth Vadapalli --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 201 +++++++++++++++++++---- drivers/net/ethernet/ti/am65-cpsw-nuss.h | 12 ++ 2 files changed, 178 insertions(+), 35 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/etherne= t/ti/am65-cpsw-nuss.c index fc165579a479..2b354af14cb7 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -1624,14 +1624,14 @@ static inline void am65_cpsw_nuss_xmit_recycle(stru= ct am65_cpsw_tx_chn *tx_chn, am65_cpsw_nuss_put_tx_desc(tx_chn, first_desc); } =20 -static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, - int chn, unsigned int budget, bool *tdown) +static int am65_cpsw_nuss_tx_cmpl_free_batch(struct am65_cpsw_common *comm= on, int chn, + u32 batch_size, unsigned int budget, + bool *tdown) { bool single_port =3D AM65_CPSW_IS_CPSW2G(common); enum am65_cpsw_tx_buf_type buf_type; struct am65_cpsw_tx_swdata *swdata; struct cppi5_host_desc_t *desc_tx; - struct device *dev =3D common->dev; struct am65_cpsw_tx_chn *tx_chn; struct netdev_queue *netif_txq; unsigned int total_bytes =3D 0; @@ -1640,21 +1640,13 @@ static int am65_cpsw_nuss_tx_compl_packets(struct a= m65_cpsw_common *common, unsigned int pkt_len; struct sk_buff *skb; dma_addr_t desc_dma; - int res, num_tx =3D 0; + int num_tx =3D 0, i; =20 tx_chn =3D &common->tx_chns[chn]; =20 - while (true) { - if (!single_port) - spin_lock(&tx_chn->lock); - res =3D k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); - if (!single_port) - spin_unlock(&tx_chn->lock); - - if (res =3D=3D -ENODATA) - break; - - if (cppi5_desc_is_tdcm(desc_dma)) { + for (i =3D 0; i < batch_size; i++) { + desc_dma =3D tx_chn->cmpl_desc_dma_array[i]; + if (unlikely(cppi5_desc_is_tdcm(desc_dma))) { if (atomic_dec_and_test(&common->tdown_cnt)) complete(&common->tdown_complete); *tdown =3D true; @@ -1701,7 +1693,34 @@ static int am65_cpsw_nuss_tx_compl_packets(struct am= 65_cpsw_common *common, am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); } =20 - dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); + return num_tx; +} + +static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, + int chn, unsigned int budget, bool *tdown) +{ + bool single_port =3D AM65_CPSW_IS_CPSW2G(common); + struct am65_cpsw_tx_chn *tx_chn; + u32 batch_size =3D 0; + int res, num_tx; + + tx_chn =3D &common->tx_chns[chn]; + + if (!single_port) + spin_lock(&tx_chn->lock); + + res =3D k3_udma_glue_pop_tx_chn_batch(tx_chn->tx_chn, tx_chn->cmpl_desc_d= ma_array, + &batch_size, AM65_CPSW_TX_BATCH_SIZE); + if (!batch_size) { + if (!single_port) + spin_unlock(&tx_chn->lock); + return 0; + } + + num_tx =3D am65_cpsw_nuss_tx_cmpl_free_batch(common, chn, batch_size, bud= get, tdown); + + if (!single_port) + spin_unlock(&tx_chn->lock); =20 return num_tx; } @@ -1760,18 +1779,48 @@ static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, v= oid *dev_id) return IRQ_HANDLED; } =20 +static void am65_cpsw_nuss_submit_ndev_batch(struct am65_cpsw_common *comm= on) +{ + bool single_port =3D AM65_CPSW_IS_CPSW2G(common); + struct am65_cpsw_tx_desc_batch *tx_desc_batch; + struct am65_cpsw_tx_chn *tx_chn; + int ret, i; + + /* Submit packets across netdevs across TX Channels */ + for (i =3D 0; i < AM65_CPSW_MAX_QUEUES; i++) { + if (common->tx_desc_batch[i].tx_batch_idx) { + tx_chn =3D &common->tx_chns[i]; + tx_desc_batch =3D &common->tx_desc_batch[i]; + if (!single_port) + spin_lock_bh(&tx_chn->lock); + ret =3D k3_udma_glue_push_tx_chn_batch(tx_chn->tx_chn, + tx_desc_batch->desc_tx_array, + tx_desc_batch->desc_dma_array, + tx_desc_batch->tx_batch_idx); + if (!single_port) + spin_unlock_bh(&tx_chn->lock); + if (ret) + dev_err(common->dev, "failed to push %u pkts on queue %d\n", + tx_desc_batch->tx_batch_idx, i); + tx_desc_batch->tx_batch_idx =3D 0; + } + } + atomic_set(&common->tx_batch_count, 0); +} + static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, struct net_device *ndev) { struct am65_cpsw_common *common =3D am65_ndev_to_common(ndev); struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; struct am65_cpsw_port *port =3D am65_ndev_to_port(ndev); + struct am65_cpsw_tx_desc_batch *tx_desc_batch; struct am65_cpsw_tx_swdata *swdata; struct device *dev =3D common->dev; struct am65_cpsw_tx_chn *tx_chn; struct netdev_queue *netif_txq; dma_addr_t desc_dma, buf_dma; - int ret, q_idx, i; + int q_idx, i; u32 *psdata; u32 pkt_len; =20 @@ -1883,20 +1932,31 @@ static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(st= ruct sk_buff *skb, =20 cppi5_hdesc_set_pktlen(first_desc, pkt_len); desc_dma =3D k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); - if (AM65_CPSW_IS_CPSW2G(common)) { - ret =3D k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); - } else { - spin_lock_bh(&tx_chn->lock); - ret =3D k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); - spin_unlock_bh(&tx_chn->lock); - } - if (ret) { - dev_err(dev, "can't push desc %d\n", ret); - /* inform bql */ - netdev_tx_completed_queue(netif_txq, 1, pkt_len); - ndev->stats.tx_errors++; - goto err_free_descs; - } + + /* Batch processing begins */ + spin_lock_bh(&common->tx_batch_lock); + + tx_desc_batch =3D &common->tx_desc_batch[q_idx]; + tx_desc_batch->desc_tx_array[tx_desc_batch->tx_batch_idx] =3D first_desc; + tx_desc_batch->desc_dma_array[tx_desc_batch->tx_batch_idx] =3D desc_dma; + tx_desc_batch->tx_batch_idx++; + + /* Push the batch across all queues and all netdevs in any of the + * following scenarios: + * 1. If we reach the batch size + * 2. If queue is stopped + * 3. No more packets are expected for ndev + * 4. We do not have sufficient free descriptors for upcoming packets + * and need to push the batch to reclaim them via completion + */ + if ((atomic_inc_return(&common->tx_batch_count) =3D=3D AM65_CPSW_TX_BATCH= _SIZE) || + netif_xmit_stopped(netif_txq) || + !netdev_xmit_more() || + (am65_cpsw_nuss_num_free_tx_desc(tx_chn) < MAX_SKB_FRAGS)) + am65_cpsw_nuss_submit_ndev_batch(common); + + /* Batch processing ends */ + spin_unlock_bh(&common->tx_batch_lock); =20 if (am65_cpsw_nuss_num_free_tx_desc(tx_chn) < MAX_SKB_FRAGS) { netif_tx_stop_queue(netif_txq); @@ -2121,19 +2181,88 @@ static int am65_cpsw_ndo_xdp_xmit(struct net_device= *ndev, int n, struct xdp_frame **frames, u32 flags) { struct am65_cpsw_common *common =3D am65_ndev_to_common(ndev); + struct am65_cpsw_port *port =3D am65_ndev_to_port(ndev); + struct am65_cpsw_tx_desc_batch *tx_desc_batch; + struct cppi5_host_desc_t *host_desc; + struct am65_cpsw_tx_swdata *swdata; struct am65_cpsw_tx_chn *tx_chn; struct netdev_queue *netif_txq; + dma_addr_t dma_desc, dma_buf; int cpu =3D smp_processor_id(); - int i, nxmit =3D 0; + int i, q_idx, nxmit =3D 0; + struct xdp_frame *xdpf; + u32 pkt_len; =20 - tx_chn =3D &common->tx_chns[cpu % common->tx_ch_num]; + q_idx =3D cpu % common->tx_ch_num; + tx_chn =3D &common->tx_chns[q_idx]; netif_txq =3D netdev_get_tx_queue(ndev, tx_chn->id); =20 __netif_tx_lock(netif_txq, cpu); for (i =3D 0; i < n; i++) { - if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], - AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) + host_desc =3D am65_cpsw_nuss_get_tx_desc(tx_chn); + if (unlikely(!host_desc)) { + ndev->stats.tx_dropped++; + break; + } + + xdpf =3D frames[i]; + pkt_len =3D xdpf->len; + + am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, AM65_CPSW_TX_BUF_TYPE_XDP= _NDO); + + dma_buf =3D dma_map_single(tx_chn->dma_dev, xdpf->data, + pkt_len, DMA_TO_DEVICE); + if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { + ndev->stats.tx_dropped++; + am65_cpsw_nuss_put_tx_desc(tx_chn, host_desc); break; + } + + cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, + AM65_CPSW_NAV_PS_DATA_SIZE); + cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); + cppi5_hdesc_set_pktlen(host_desc, pkt_len); + cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); + cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); + + k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); + cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); + + swdata =3D cppi5_hdesc_get_swdata(host_desc); + swdata->ndev =3D ndev; + swdata->xdpf =3D xdpf; + + /* Report BQL before sending the packet */ + netif_txq =3D netdev_get_tx_queue(ndev, tx_chn->id); + netdev_tx_sent_queue(netif_txq, pkt_len); + + dma_desc =3D k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); + + /* Batch processing begins */ + spin_lock_bh(&common->tx_batch_lock); + + tx_desc_batch =3D &common->tx_desc_batch[q_idx]; + tx_desc_batch->desc_tx_array[tx_desc_batch->tx_batch_idx] =3D host_desc; + tx_desc_batch->desc_dma_array[tx_desc_batch->tx_batch_idx] =3D dma_desc; + tx_desc_batch->tx_batch_idx++; + + /* Push the batch across all queues and all netdevs in any of the + * following scenarios: + * 1. If we reach the batch size + * 2. If queue is stopped + * 3. We are at the last XDP frame in the batch + * 4. We do not have sufficient free descriptors for upcoming packets + * and need to push the batch to reclaim them via completion + */ + if ((atomic_inc_return(&common->tx_batch_count) =3D=3D AM65_CPSW_TX_BATC= H_SIZE) || + netif_xmit_stopped(netif_txq) || + (i =3D=3D (n - 1)) || + (am65_cpsw_nuss_num_free_tx_desc(tx_chn) < MAX_SKB_FRAGS)) + am65_cpsw_nuss_submit_ndev_batch(common); + + /* Batch processing ends */ + spin_unlock_bh(&common->tx_batch_lock); + nxmit++; } __netif_tx_unlock(netif_txq); @@ -2497,6 +2626,8 @@ static int am65_cpsw_nuss_init_tx_chns(struct am65_cp= sw_common *common) dev_name(dev), tx_chn->id); } =20 + atomic_set(&common->tx_batch_count, 0); + ret =3D am65_cpsw_nuss_ndev_add_tx_napi(common); if (ret) { dev_err(dev, "Failed to add tx NAPI %d\n", ret); diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/etherne= t/ti/am65-cpsw-nuss.h index e64b4cfd6f2c..81405e3bed79 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -28,6 +28,8 @@ struct am65_cpts; #define AM65_CPSW_MAX_TX_DESC 500 #define AM65_CPSW_MAX_RX_DESC 500 =20 +#define AM65_CPSW_TX_BATCH_SIZE 128 + #define AM65_CPSW_PORT_VLAN_REG_OFFSET 0x014 =20 struct am65_cpsw_slave_data { @@ -93,6 +95,7 @@ struct am65_cpsw_tx_chn { struct k3_cppi_desc_pool *desc_pool; struct k3_udma_glue_tx_channel *tx_chn; spinlock_t lock; /* protect TX rings in multi-port mode */ + dma_addr_t cmpl_desc_dma_array[AM65_CPSW_TX_BATCH_SIZE]; struct am65_cpsw_tx_ring tx_ring; struct hrtimer tx_hrtimer; unsigned long tx_pace_timeout; @@ -165,6 +168,12 @@ struct am65_cpsw_devlink { struct am65_cpsw_common *common; }; =20 +struct am65_cpsw_tx_desc_batch { + struct cppi5_host_desc_t *desc_tx_array[AM65_CPSW_TX_BATCH_SIZE]; + dma_addr_t desc_dma_array[AM65_CPSW_TX_BATCH_SIZE]; + u8 tx_batch_idx; +}; + struct am65_cpsw_common { struct device *dev; struct device *mdio_dev; @@ -188,6 +197,9 @@ struct am65_cpsw_common { struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_QUEUES]; struct completion tdown_complete; atomic_t tdown_cnt; + atomic_t tx_batch_count; + spinlock_t tx_batch_lock; /* protect TX batch operations */ + struct am65_cpsw_tx_desc_batch tx_desc_batch[AM65_CPSW_MAX_QUEUES]; =20 int rx_ch_num_flows; struct am65_cpsw_rx_chn rx_chns; --=20 2.51.1