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charset="utf-8" Some i.MX boards (i.MX8MP EVK and i.MX95-15x15 EVK) have M.2 connectors that are physically wired to both USDHC and PCIe controllers. The default device tree enables USDHC for SDIO WiFi modules and disables PCIe to avoid regulator conflicts. Add a common imx-m2-pcie.dtso that can be applied to enable PCIe and disable USDHC when a PCIe module is installed in the M.2 connector. This creates the following DTB files: - imx8mp-evk-pcie.dtb: i.MX8MP EVK with PCIe enabled - imx95-15x15-evk-pcie.dtb: i.MX95-15x15 EVK with PCIe enabled Signed-off-by: Sherry Sun --- arch/arm64/boot/dts/freescale/Makefile | 9 +++++++-- arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso | 15 +++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 155213c45319..1f542324b4fc 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -333,12 +333,14 @@ imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs +=3D imx8mp-evk.d= tb imx8mp-evk-lvds0-imx-lvds- imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs +=3D imx8mp-evk.dtb imx8mp-e= vk-lvds1-imx-dlvds-hdmi-channel0.dtbo imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs +=3D imx8mp-evk.dtb imx8mp-evk-lvds1-i= mx-lvds-hdmi.dtbo imx8mp-evk-mx8-dlvds-lcd1-dtbs +=3D imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lc= d1.dtbo -imx8mp-evk-pcie-ep-dtbs +=3D imx8mp-evk.dtb imx-pcie0-ep.dtbo +imx8mp-evk-pcie-dtbs +=3D imx8mp-evk.dtb imx-m2-pcie.dtbo +imx8mp-evk-pcie-ep-dtbs +=3D imx8mp-evk-pcie.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds0-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds1-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-mx8-dlvds-lcd1.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-pcie.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-pcie-ep.dtb =20 imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33-dtbs +=3D imx8mp-tqma8mpql-mba8= mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo @@ -481,7 +483,10 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-tqma9596sa-mb-smarc-2.dtb =20 -imx95-15x15-evk-pcie0-ep-dtbs =3D imx95-15x15-evk.dtb imx-pcie0-ep.dtbo +imx95-15x15-evk-pcie-dtbs +=3D imx95-15x15-evk.dtb imx-m2-pcie.dtbo +dtb-$(CONFIG_ARCH_MXC) +=3D imx95-15x15-evk-pcie.dtb + +imx95-15x15-evk-pcie0-ep-dtbs =3D imx95-15x15-evk-pcie.dtb imx-pcie0-ep.dt= bo dtb-$(CONFIG_ARCH_MXC) +=3D imx95-15x15-evk-pcie0-ep.dtb imx95-19x19-evk-pcie0-ep-dtbs +=3D imx95-19x19-evk.dtb imx-pcie0-ep.dtbo imx95-19x19-evk-pcie1-ep-dtbs +=3D imx95-19x19-evk.dtb imx-pcie1-ep.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso b/arch/arm64/bo= ot/dts/freescale/imx-m2-pcie.dtso new file mode 100644 index 000000000000..1930de058a08 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx-m2-pcie.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +&pcie0 { + status =3D "okay"; +}; + +&m2_usdhc { + status =3D "disabled"; +}; --=20 2.37.1