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Wed, 25 Mar 2026 00:58:41 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:7ff0:bee3:7d45:eab]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b08366c3f7sm219682465ad.60.2026.03.25.00.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 00:58:41 -0700 (PDT) From: Chen-Yu Tsai To: Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: Icenowy Zheng , Icenowy Zheng , Chen-Yu Tsai , David Airlie , Simona Vetter , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] arm64: dts: mediatek: mt8173: Add GPU device nodes Date: Wed, 25 Mar 2026 15:19:49 +0800 Message-ID: <20260325071951.544031-6-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.1018.g2bb0e51243-goog In-Reply-To: <20260325071951.544031-1-wenst@chromium.org> References: <20260325071951.544031-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part of the Series6XT, another variation of the Rogue family of GPUs. On top of the GPU is a glue layer that handles some clock and power signals. Add device nodes for both. While there is supposed to be two different power domains to the GPU, MediaTek does not have any information on how this is integrated internally. Assign the same GPU power domain to both. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index 556e806b7787..169ba4fd183e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1002,6 +1002,37 @@ u2port1: usb-phy@11291000 { }; }; =20 + gpu: gpu@13000000 { + compatible =3D "mediatek,mt8173-gpu", "img,img-gx6250", + "img,img-rogue"; + reg =3D <0 0x13000000 0 0x10000>; + interrupts =3D ; + clocks =3D <&mfgtop CLK_MFG_G3D>, + <&mfgtop CLK_MFG_MEM>, + <&mfgtop CLK_MFG_AXI>; + clock-names =3D "core", "mem", "sys"; + /* + * Binding and GPU core HW have two power domain + * inputs, but MediaTek does not have information + * on how this is done internally. + */ + power-domains =3D <&mfgtop>, <&mfgtop>; + power-domain-names =3D "a", "b"; + }; + + mfgtop: clock-controller@13fff000 { + compatible =3D "mediatek,mt8173-mfgtop"; + reg =3D <0 0x13fff000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_AXI_MFG_IN_SEL>, + <&topckgen CLK_TOP_MEM_MFG_IN_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&clk26m>; + clock-names =3D "sys", "mem", "core", "clk26m"; + power-domains =3D <&spm MT8173_POWER_DOMAIN_MFG>; + #clock-cells =3D <1>; + #power-domain-cells =3D <0>; + }; + mmsys: syscon@14000000 { compatible =3D "mediatek,mt8173-mmsys", "syscon"; reg =3D <0 0x14000000 0 0x1000>; --=20 2.53.0.1018.g2bb0e51243-goog