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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82b0410870csm14220689b3a.52.2026.03.24.20.54.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 20:54:08 -0700 (PDT) From: Sibi Sankar To: robh@kernel.org, srini@kernel.org, amahesh@qti.qualcomm.com, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mohammad Rafi Shaik Subject: [PATCH V6 4/5] arm64: dts: glymur: Add LPASS macro codecs and pinctrl Date: Wed, 25 Mar 2026 09:23:37 +0530 Message-Id: <20260325035338.1393287-5-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260325035338.1393287-1-sibi.sankar@oss.qualcomm.com> References: <20260325035338.1393287-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: DafSVL6Ade4okULthAxMDjiZJoISkdCQ X-Authority-Analysis: v=2.4 cv=F4lat6hN c=1 sm=1 tr=0 ts=69c35c62 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=mx1dUFmayEYO8tNA33gA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: DafSVL6Ade4okULthAxMDjiZJoISkdCQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDAyMyBTYWx0ZWRfX9uv+NGW3Ltwv Qe3y6fD7hLXgpBe+ERI151aSNOXKROfb2m5scqNzVwJIRzewDZqdlCxXDV1EWwi+rL/bq74eURs xO+sSqCkQsxgHBQmLyx903Jpidec//u1OQLypzIEP+Y5ps767cW8R8T7aj0p42GOJTb9kZifWCm jr3PS4l8Qa1Is3HUBqVXAgOzJuv1zo1XD9cWSDor+ZgJJqmb8Pwffoj5Jj5GVjf46g9xkenZc41 YoLfvf66PndHZngfrUZb0ZUr1n3hf70ZsqIRuEUu+LlQbtgPHKHC4elwfaPSmV8M9HD+t/Pv11P 8QGOEL0W0TyZ9JdgzsFWIe4za0hbaBFGK7KEyMwxNe2Eei7Jp7z1/3Xky6M3Kxx0bbDesNrkbfc VoAR2xNCr1hxKJ9NpYffyle+o7Z4ChP3tfMN3/Ws8mBUOturSVanvvtenaEs8kp+NpmxjbALjK3 87H0Y0u9wGdKC6Kk2GQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_01,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250023 Content-Type: text/plain; charset="utf-8" From: Srinivas Kandagatla Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur. for proper sound support. Also add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Srinivas Kandagatla Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/glymur.dtsi | 263 +++++++++++++++++++++++++++ 1 file changed, 263 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e571710de40e..61a5f263f5ad 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include =20 #include "glymur-ipcc.h" @@ -3818,9 +3820,138 @@ compute-cb@8 { dma-coherent; }; }; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + compatible =3D "qcom,q6apm"; + reg =3D ; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + iommus =3D <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1061 0x20>; + }; + }; + + q6prm: service@2 { + compatible =3D "qcom,q6prm"; + reg =3D ; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + }; }; }; =20 + swr0: soundwire@6c80000 { + compatible =3D "qcom,soundwire-v3.1.0"; + reg =3D <0x0 0x06c80000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsamacro>; + clock-names =3D "iface"; + label =3D "WSA"; + + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8= 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_wsamacro: codec@6c90000 { + compatible =3D "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-ma= cro"; + reg =3D <0x0 0x06c90000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_= COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + sound-name-prefix =3D "WSA"; + }; + + swr3: soundwire@6ca0000 { + compatible =3D "qcom,soundwire-v3.1.0"; + reg =3D <0x0 0x06ca0000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsa2macro>; + clock-names =3D "iface"; + label =3D "WSA2"; + + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8= 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_wsa2macro: codec@6cb0000 { + compatible =3D "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-ma= cro"; + reg =3D <0x0 0x06cb0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE= _COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + sound-name-prefix =3D "WSA2"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible =3D "qcom,glymur-lpass-lpiaon-noc"; reg =3D <0x0 0x07400000 0x0 0x19080>; @@ -3835,6 +3966,138 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells =3D <2>; }; =20 + lpass_vamacro: codec@7660000 { + compatible =3D "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macr= o"; + reg =3D <0x0 0x07660000 0x0 0x2000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", + "macro", + "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible =3D "qcom,glymur-lpass-lpi-pinctrl", "qcom,sm8650-lpass-lpi-= pinctrl"; + reg =3D <0x0 0x07760000 0x0 0x20000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + }; + lpass_ag_noc: interconnect@7e40000 { compatible =3D "qcom,glymur-lpass-ag-noc"; reg =3D <0x0 0x07e40000 0x0 0xe080>; --=20 2.34.1