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charset="utf-8" Move the SEC2 reset/load/boot sequence into a BooterFirmware::run() method, and call it from a thin run_booter() helper on Gsp. This is almost a pure refactoring with no behavior change, done in preparation for adding an alternative FSP boot path. The one slight difference is that an MBOX1 printing typo is fixed: Previous output: NovaCore 0000:e1:00.0: SEC2 MBOX0: 0x0, MBOX10x1 Fixed output: NovaCore 0000:e1:00.0: SEC2 MBOX0: 0x0, MBOX1: 0x1 Suggested-by: Danilo Krummrich Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot Signed-off-by: John Hubbard --- drivers/gpu/nova-core/firmware/booter.rs | 30 ++++++++++++++++ drivers/gpu/nova-core/fsp.rs | 45 ++++++++++-------------- drivers/gpu/nova-core/gsp/boot.rs | 43 +++++++++++----------- 3 files changed, 69 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index de2a4536b532..6a41690e72c6 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -8,6 +8,7 @@ =20 use kernel::{ device, + dma::Coherent, prelude::*, transmute::FromBytes, // }; @@ -396,6 +397,35 @@ pub(crate) fn new( ucode: ucode_signed, }) } + + /// Load and run the booter firmware on SEC2. + /// + /// Resets SEC2, loads this firmware image, then boots with the WPR me= tadata + /// address passed via the SEC2 mailboxes. + pub(crate) fn run( + &self, + dev: &device::Device, + bar: &Bar0, + sec2_falcon: &Falcon, + wpr_meta: &Coherent, + ) -> Result { + sec2_falcon.reset(bar)?; + sec2_falcon.load(dev, bar, self)?; + let wpr_handle =3D wpr_meta.dma_handle(); + let (mbox0, mbox1) =3D sec2_falcon.boot( + bar, + Some(wpr_handle as u32), + Some((wpr_handle >> 32) as u32), + )?; + dev_dbg!(dev, "SEC2 MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); + + if mbox0 !=3D 0 { + dev_err!(dev, "Booter-load failed with error {:#x}\n", mbox0); + return Err(ENODEV); + } + + Ok(()) + } } =20 impl FalconDmaLoadable for BooterFirmware { diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index faa0b3ae88ba..1d3092e6b14f 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -8,7 +8,10 @@ =20 use kernel::{ device, - dma::CoherentAllocation, + dma::{ + Coherent, + CoherentBox, // + }, io::poll::read_poll_timeout, prelude::*, ptr::{ @@ -222,7 +225,7 @@ impl MessageToFsp for FspMessage { pub(crate) struct FmcBootArgs<'a> { chipset: crate::gpu::Chipset, fmc_image_fw: &'a crate::dma::DmaObject, - fmc_boot_params: CoherentAllocation, + fmc_boot_params: Coherent, resume: bool, signatures: &'a FmcSignatures, } @@ -246,34 +249,24 @@ pub(crate) fn new( const GSP_DMA_TARGET_COHERENT_SYSTEM: u32 =3D 1; const GSP_DMA_TARGET_NONCOHERENT_SYSTEM: u32 =3D 2; =20 - let fmc_boot_params =3D CoherentAllocation::::al= loc_coherent( - dev, - 1, - GFP_KERNEL | __GFP_ZERO, - )?; + let mut fmc_boot_params =3D CoherentBox::::zeroe= d(dev, GFP_KERNEL)?; =20 // Blackwell FSP expects wpr_carveout_offset and wpr_carveout_size= to be zero; // it obtains WPR info from other sources. - kernel::dma_write!( - fmc_boot_params, - [0]?.boot_gsp_rm_params, - GspAcrBootGspRmParams { - target: GSP_DMA_TARGET_COHERENT_SYSTEM, - gsp_rm_desc_size: wpr_meta_size, - gsp_rm_desc_offset: wpr_meta_addr, - b_is_gsp_rm_boot: 1, - ..Default::default() - } - ); + fmc_boot_params.boot_gsp_rm_params =3D GspAcrBootGspRmParams { + target: GSP_DMA_TARGET_COHERENT_SYSTEM, + gsp_rm_desc_size: wpr_meta_size, + gsp_rm_desc_offset: wpr_meta_addr, + b_is_gsp_rm_boot: 1, + ..Default::default() + }; =20 - kernel::dma_write!( - fmc_boot_params, - [0]?.gsp_rm_params, - GspRmParams { - target: GSP_DMA_TARGET_NONCOHERENT_SYSTEM, - boot_args_offset: libos_addr, - } - ); + fmc_boot_params.gsp_rm_params =3D GspRmParams { + target: GSP_DMA_TARGET_NONCOHERENT_SYSTEM, + boot_args_offset: libos_addr, + }; + + let fmc_boot_params: Coherent =3D fmc_boot_param= s.into(); =20 Ok(Self { chipset, diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index e55210ebb6d1..9d0e29e82574 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -128,6 +128,25 @@ fn run_fwsec_frts( } } =20 + fn run_booter( + dev: &device::Device, + bar: &Bar0, + chipset: Chipset, + sec2_falcon: &Falcon, + wpr_meta: &Coherent, + ) -> Result { + let booter =3D BooterFirmware::new( + dev, + BooterKind::Loader, + chipset, + FIRMWARE_VERSION, + sec2_falcon, + bar, + )?; + + booter.run(dev, bar, sec2_falcon, wpr_meta) + } + /// Attempt to boot the GSP. /// /// This is a GPU-dependent and complex procedure that involves loadin= g firmware files from @@ -154,15 +173,6 @@ pub(crate) fn boot( =20 Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb_lay= out)?; =20 - let booter_loader =3D BooterFirmware::new( - dev, - BooterKind::Loader, - chipset, - FIRMWARE_VERSION, - sec2_falcon, - bar, - )?; - let wpr_meta =3D Coherent::init(dev, GFP_KERNEL, GspFwWprMeta::new= (&gsp_fw, &fb_layout))?; =20 self.cmdq @@ -184,20 +194,7 @@ pub(crate) fn boot( "Using SEC2 to load and run the booter_load firmware...\n" ); =20 - sec2_falcon.reset(bar)?; - sec2_falcon.load(dev, bar, &booter_loader)?; - let wpr_handle =3D wpr_meta.dma_handle(); - let (mbox0, mbox1) =3D sec2_falcon.boot( - bar, - Some(wpr_handle as u32), - Some((wpr_handle >> 32) as u32), - )?; - dev_dbg!(pdev, "SEC2 MBOX0: {:#x}, MBOX1{:#x}\n", mbox0, mbox1); - - if mbox0 !=3D 0 { - dev_err!(pdev, "Booter-load failed with error {:#x}\n", mbox0); - return Err(ENODEV); - } + Self::run_booter(dev, bar, chipset, sec2_falcon, &wpr_meta)?; =20 gsp_falcon.write_os_version(bar, gsp_fw.bootloader.app_version); =20 --=20 2.53.0