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charset="utf-8" Add external memory (EMEM) read/write operations to the GPU's FSP falcon engine. These operations use Falcon PIO (Programmed I/O) to communicate with the FSP through indirect memory access. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 120 +++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 12 +++ 2 files changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index c5ba1c2412cd..29a68d6934a9 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -5,13 +5,26 @@ //! The FSP falcon handles secure boot and Chain of Trust operations //! on Hopper and Blackwell architectures, replacing SEC2's role. =20 +use kernel::{ + io::{ + Io, + IoCapable, // + }, + prelude::*, // +}; + use crate::{ + driver::Bar0, falcon::{ + Falcon, FalconEngine, PFalcon2Base, PFalconBase, // }, - regs::macros::RegisterBase, + regs::{ + self, + macros::RegisterBase, // + }, }; =20 /// Type specifying the `Fsp` falcon engine. Cannot be instantiated. @@ -28,3 +41,108 @@ impl RegisterBase for Fsp { impl FalconEngine for Fsp { const ID: Self =3D Fsp(()); } + +/// Maximum addressable EMEM size, derived from the 24-bit offset field +/// in NV_PFALCON_FALCON_EMEM_CTL. +const EMEM_MAX_SIZE: usize =3D 1 << 24; + +/// I/O backend for the FSP falcon's external memory (EMEM). +/// +/// Each 32-bit access programs a byte offset via the EMEM_CTL register, +/// then reads or writes through the EMEM_DATA register. +pub(crate) struct Emem<'a> { + bar: &'a Bar0, +} + +impl<'a> Emem<'a> { + fn new(bar: &'a Bar0) -> Self { + Self { bar } + } +} + +impl IoCapable for Emem<'_> { + unsafe fn io_read(&self, address: usize) -> u32 { + // The Io trait validates that EMEM accesses fit within the 24-bit= offset field. + let offset =3D address as u32; + + regs::NV_PFALCON_FALCON_EMEM_CTL::default() + .set_rd_mode(true) + .set_offset(offset) + .write(self.bar, &Fsp::ID); + + regs::NV_PFALCON_FALCON_EMEM_DATA::read(self.bar, &Fsp::ID).data() + } + + unsafe fn io_write(&self, value: u32, address: usize) { + // The Io trait validates that EMEM accesses fit within the 24-bit= offset field. + let offset =3D address as u32; + + regs::NV_PFALCON_FALCON_EMEM_CTL::default() + .set_wr_mode(true) + .set_offset(offset) + .write(self.bar, &Fsp::ID); + + regs::NV_PFALCON_FALCON_EMEM_DATA::default() + .set_data(value) + .write(self.bar, &Fsp::ID); + } +} + +impl Io for Emem<'_> { + fn addr(&self) -> usize { + 0 + } + + fn maxsize(&self) -> usize { + EMEM_MAX_SIZE + } +} + +impl Falcon { + /// Returns an EMEM I/O accessor for this FSP falcon. + pub(crate) fn emem<'a>(&self, bar: &'a Bar0) -> Emem<'a> { + Emem::new(bar) + } + + /// Writes `data` to FSP external memory at byte `offset`. + /// + /// Data is interpreted as little-endian 32-bit words. + /// Returns `EINVAL` if offset or data length is not 4-byte aligned. + #[expect(unused)] + pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) = -> Result { + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + let emem =3D self.emem(bar); + let mut off =3D offset as usize; + for chunk in data.chunks_exact(4) { + let word =3D u32::from_le_bytes([chunk[0], chunk[1], chunk[2],= chunk[3]]); + emem.try_write32(word, off)?; + off +=3D 4; + } + + Ok(()) + } + + /// Reads FSP external memory at byte `offset` into `data`. + /// + /// Data is stored as little-endian 32-bit words. + /// Returns `EINVAL` if offset or data length is not 4-byte aligned. + #[expect(unused)] + pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8= ]) -> Result { + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + let emem =3D self.emem(bar); + let mut off =3D offset as usize; + for chunk in data.chunks_exact_mut(4) { + let word =3D emem.try_read32(off)?; + chunk.copy_from_slice(&word.to_le_bytes()); + off +=3D 4; + } + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 53f412f0ca32..f577800db3e3 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -461,6 +461,18 @@ pub(crate) fn reset_engine(bar: &Bar0= ) { 8:8 br_fetch as bool; }); =20 +// Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). +// These provide the falcon external memory communication interface. +register!(NV_PFALCON_FALCON_EMEM_CTL @ PFalconBase[0x00000ac0] { + 23:0 offset as u32; // EMEM byte offset (must be 4-byte aligne= d) + 24:24 wr_mode as bool; // Write mode + 25:25 rd_mode as bool; // Read mode +}); + +register!(NV_PFALCON_FALCON_EMEM_DATA @ PFalconBase[0x00000ac4] { + 31:0 data as u32; // EMEM data register +}); + // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.53.0