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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-t264-pwm-v2-4-998d885984b3@nvidia.com> References: <20260325-t264-pwm-v2-0-998d885984b3@nvidia.com> In-Reply-To: <20260325-t264-pwm-v2-0-998d885984b3@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yi-Wei Wang , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TPYP295CA0047.TWNP295.PROD.OUTLOOK.COM (2603:1096:7d0:8::16) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|DS5PPFA3734E4BA:EE_ X-MS-Office365-Filtering-Correlation-Id: 28eab333-179d-4983-ffdc-08de8a57c838 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|10070799003|376014|22082099003|56012099003|18002099003; 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Hence, introduce an enablement offset field in the tegra_pwm_soc structure to describe the offset of the register. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index cf54f75d92a5..22d709986e8c 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -61,6 +61,7 @@ =20 struct tegra_pwm_soc { unsigned int num_channels; + unsigned int enable_reg; }; =20 struct tegra_pwm_chip { @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, err =3D pm_runtime_resume_and_get(pwmchip_parent(chip)); if (err) return err; - } else + } else if (pc->soc->enable_reg =3D=3D PWM_CSR_0) { val |=3D PWM_ENABLE; + } =20 pwm_writel(pwm, PWM_CSR_0, val); =20 @@ -213,6 +215,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); int rc =3D 0; u32 val; =20 @@ -220,20 +223,22 @@ static int tegra_pwm_enable(struct pwm_chip *chip, st= ruct pwm_device *pwm) if (rc) return rc; =20 - val =3D pwm_readl(pwm, PWM_CSR_0); + + val =3D pwm_readl(pwm, pc->soc->enable_reg); val |=3D PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); =20 return 0; } =20 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pw= m) { + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); u32 val; =20 - val =3D pwm_readl(pwm, PWM_CSR_0); + val =3D pwm_readl(pwm, pc->soc->enable_reg); val &=3D ~PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); =20 pm_runtime_put_sync(pwmchip_parent(chip)); } @@ -398,10 +403,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(st= ruct device *dev) =20 static const struct tegra_pwm_soc tegra20_pwm_soc =3D { .num_channels =3D 4, + .enable_reg =3D PWM_CSR_0, }; =20 static const struct tegra_pwm_soc tegra186_pwm_soc =3D { .num_channels =3D 1, + .enable_reg =3D PWM_CSR_0, }; =20 static const struct of_device_id tegra_pwm_of_match[] =3D { --=20 2.53.0