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Wed, 25 Mar 2026 18:11:12 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface From: Javier Tia Date: Wed, 25 Mar 2026 16:10:58 -0600 Subject: [PATCH v3 09/13] wifi: mt76: mt7925: add chip-specific DMA configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-mt7927-wifi-support-v2-v3-9-5ca66c97a755@jetm.me> To: Felix Fietkau , Lorenzo Bianconi , Ryder Lee , Shayne Chen , Sean Wang , Matthias Brugger , AngeloGioacchino Del Regno , Ming Yen Hsieh , Deren Wu Cc: linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Marcin FM , Cristian-Florin Radoi , George Salukvadze , Evgeny Kapusta <3193631@gmail.com>, Samu Toljamo , Ariel Rosenfeld , Chapuis Dario , =?utf-8?q?Thibaut_Fran=C3=A7ois?= , =?utf-8?q?=E5=BC=A0=E6=97=AD=E6=B6=B5?= X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=15351; i=floss@jetm.me; h=from:subject:message-id; bh=wWU757xwqx0hIgj80GlHGMOCQOT/7mAO0JYyHm76zMY=; b=owEB7QES/pANAwAKAbXuwwuoZ3cfAcsmYgBpxF1qaLmG3d0jgEa4IZk3zxZSDi8tvnejJ/NY5 fstA/d0YumJAbMEAAEKAB0WIQSbE7ILzw7eI0VKk8m17sMLqGd3HwUCacRdagAKCRC17sMLqGd3 H368C/9CoPzpXnqP4xE/ZUUJD+iGkbpInfyzcYgHlePuo0V9OGaecLM2Z4adbIsDtMjHaOu4rLJ KfPnDFZaylr4QqW9YQReGEbTMcWQMiFlYquP4kKUdG5Qo+YVd0qx4Or8CyV+NJ8yir44EbMcGWM HgImZSYietEDzq0I7trOmkPudxLh5NEpGZgdkPJlZaPRATgsxGVgl65A+hz6P6m2yr/44SlUCVM wKKYVJTzSmGAMXAh+oGsAGdukqshyRkczVtSZ014LLxvX74zkc6qoWUfJobmQBOgVPOF07IRsm7 4/sT1LqprZK2qJs1TpvcFbBHmFBtPLkSM6UMaXCcWNnR1Z8Z1Y2LbPbtfoN125f6/PI/evM4mW1 vHxF7bF2PnbFauolifiw/bWqnuKOltF8TYUVRaiCC29LefHPEUkMuvRnK/GH83BRk8ArS/07gK0 hex9hQBiqSvtwrhP85T+cPXaOwX4XwzO7R3aMG2Vs2WLgnFmzz1QZtVALz78NgHovyym0= X-Developer-Key: i=floss@jetm.me; a=openpgp; fpr=9B13B20BCF0EDE23454A93C9B5EEC30BA867771F In-Reply-To: <20260325-mt7927-wifi-support-v2-v3-0-5ca66c97a755@jetm.me> References: <20260325-mt7927-wifi-support-v2-v3-0-5ca66c97a755@jetm.me> MT7927 uses different DMA ring indices (RX rings 4, 6, 7 vs MT7925's 0, 1, 2), a different prefetch register layout, and requires additional GLO_CFG bits (ADDR_EXT_EN, FW_DWLD_BYPASS_DMASHDL) that must be restored after every PM wake cycle. Introduce struct mt792x_dma_config to parameterize per-chip DMA differences: - RX ring indices for MCU events, data, and auxiliary queues - Prefetch configuration callback - GLO_CFG quirk bits (set/clear masks applied after DMA enable) - Pre-ring-setup hook for MT7927's SET_OWN/CLR_OWN sequence Refactor mt7925_dma_init() to read ring indices from the config struct, eliminating the need for a standalone mt7927_dma_init(). The single init function handles both chips by dispatching through the config. Update mt792x_dma_enable() to apply chip-specific GLO_CFG bits from the config and select the correct GLO_CFG_EXT1 register address per chip. Ring layout and prefetch values derived from Loong0x00's reverse-engineered MT7927 driver. Tested-by: Marcin FM Tested-by: Cristian-Florin Radoi Tested-by: George Salukvadze Tested-by: Evgeny Kapusta <3193631@gmail.com> Tested-by: Samu Toljamo Tested-by: Ariel Rosenfeld Tested-by: Chapuis Dario Tested-by: Thibaut Fran=C3=A7ois Tested-by: =E5=BC=A0=E6=97=AD=E6=B6=B5 Signed-off-by: Javier Tia --- drivers/net/wireless/mediatek/mt76/mt7925/pci.c | 137 +++++++++++++++++++= ++-- drivers/net/wireless/mediatek/mt76/mt792x.h | 21 ++++ drivers/net/wireless/mediatek/mt76/mt792x_dma.c | 68 +++++------ drivers/net/wireless/mediatek/mt76/mt792x_regs.h | 12 ++ 4 files changed, 198 insertions(+), 40 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c b/drivers/net/= wireless/mediatek/mt76/mt7925/pci.c index 604c0e9ae7ba..415194a440f8 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7925/pci.c +++ b/drivers/net/wireless/mediatek/mt76/mt7925/pci.c @@ -210,17 +210,128 @@ static u32 mt7925_rmw(struct mt76_dev *mdev, u32 off= set, u32 mask, u32 val) return dev->bus_ops->rmw(mdev, addr, mask, val); } =20 +/* MT7927 uses different RX ring indices than MT7925 */ +enum mt7927_rxq_id { + MT7927_RXQ_BAND0 =3D 4, + MT7927_RXQ_MCU_WM =3D 6, + MT7927_RXQ_DATA2 =3D 7, +}; + +#define PREFETCH(base, depth) ((base) << 16 | (depth)) + +static void mt7925_dma_prefetch(struct mt792x_dev *dev) +{ + /* rx ring */ + mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x4)); + mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0040, 0x4)); + mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x0080, 0x4)); + mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x00c0, 0x4)); + /* tx ring */ + mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0100, 0x10)); + mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x0200, 0x10)); + mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x0300, 0x10)); + mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x0400, 0x10)); + mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0500, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0540, 0x4)); +} + +static void mt7927_dma_prefetch(struct mt792x_dev *dev) +{ + /* Trigger prefetch controller reset before reprogramming */ + mt76_wr(dev, MT_WFDMA_PREFETCH_CTRL, + mt76_rr(dev, MT_WFDMA_PREFETCH_CTRL)); + /* MT7927 uses packed prefetch registers */ + mt76_wr(dev, MT_WFDMA_PREFETCH_CFG0, 0x660077); + mt76_wr(dev, MT_WFDMA_PREFETCH_CFG1, 0x1100); + mt76_wr(dev, MT_WFDMA_PREFETCH_CFG2, 0x30004f); + mt76_wr(dev, MT_WFDMA_PREFETCH_CFG3, 0x542200); + /* per-ring EXT_CTRL */ + mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0x0000, 0x8)); + mt76_wr(dev, MT_WFDMA0_RX_RING6_EXT_CTRL, PREFETCH(0x0080, 0x8)); + mt76_wr(dev, MT_WFDMA0_RX_RING7_EXT_CTRL, PREFETCH(0x0100, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0140, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0180, 0x10)); + mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0280, 0x4)); +} + +static int mt7927_pre_ring_setup(struct mt792x_dev *dev) +{ + int ret; + + /* SET_OWN -> CLR_OWN: triggers ROM to initialize WFDMA */ + ret =3D mt792xe_mcu_fw_pmctrl(dev); + if (ret) + return ret; + + ret =3D __mt792xe_mcu_drv_pmctrl(dev); + if (ret) + return ret; + + /* Clear pending interrupts from previous state */ + mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, ~0); + + return 0; +} + +static const struct mt792x_dma_config mt7925_dma_cfg =3D { + .rxq_band0 =3D MT7925_RXQ_BAND0, /* 2 */ + .rxq_mcu_wm =3D MT7925_RXQ_MCU_WM, /* 0 */ + .dma_prefetch =3D mt7925_dma_prefetch, + .glo_cfg_ext1 =3D MT_UWFDMA0_GLO_CFG_EXT1, +}; + +static const struct mt792x_dma_config mt7927_dma_cfg =3D { + .rxq_band0 =3D MT7927_RXQ_BAND0, /* 4 */ + .rxq_mcu_wm =3D MT7927_RXQ_MCU_WM, /* 6 */ + .rxq_data2 =3D MT7927_RXQ_DATA2, /* 7 */ + .dma_prefetch =3D mt7927_dma_prefetch, + .glo_cfg_set =3D MT_WFDMA0_GLO_CFG_ADDR_EXT_EN | + MT_WFDMA0_GLO_CFG_FW_DWLD_BYPASS_DMASHDL, + .glo_cfg_clear =3D MT_WFDMA0_GLO_CFG_CSR_LBK_RX_Q_SEL_EN, + .glo_cfg_ext1 =3D MT_WFDMA0_GLO_CFG_EXT1, + .pre_ring_setup =3D mt7927_pre_ring_setup, +}; + static int mt7925_dma_init(struct mt792x_dev *dev) { + const struct mt792x_dma_config *cfg =3D dev->dma_config; int ret; =20 mt76_dma_attach(&dev->mt76); =20 - ret =3D mt792x_dma_disable(dev, true); - if (ret) - return ret; + if (cfg->pre_ring_setup) { + ret =3D cfg->pre_ring_setup(dev); + if (ret) + return ret; =20 - /* init tx queue */ + /* Disable DMA before ring allocation */ + mt76_clear(dev, MT_WFDMA0_GLO_CFG, + MT_WFDMA0_GLO_CFG_TX_DMA_EN | + MT_WFDMA0_GLO_CFG_RX_DMA_EN | + MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN | + MT_WFDMA0_GLO_CFG_OMIT_TX_INFO | + MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2); + /* Ensure all DMA writes complete before polling status. */ + wmb(); + + if (!mt76_poll_msec_tick(dev, MT_WFDMA0_GLO_CFG, + MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | + MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, + 0, 100, 1)) + return -ETIMEDOUT; + + mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); + mt76_wr(dev, MT_WFDMA0_RST_DRX_PTR, ~0); + /* Ensure all DMA writes complete before polling status. */ + wmb(); + msleep(10); + } else { + ret =3D mt792x_dma_disable(dev, true); + if (ret) + return ret; + } + + /* init tx queue - ring 0 */ ret =3D mt76_connac_init_tx_queues(dev->phy.mt76, MT7925_TXQ_BAND0, MT7925_TX_RING_SIZE, MT_TX_RING_BASE, NULL, 0); @@ -241,20 +352,31 @@ static int mt7925_dma_init(struct mt792x_dev *dev) if (ret) return ret; =20 - /* rx event */ + /* rx MCU events */ ret =3D mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], - MT7925_RXQ_MCU_WM, MT7925_RX_MCU_RING_SIZE, + cfg->rxq_mcu_wm, MT7925_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE); if (ret) return ret; =20 /* rx data */ ret =3D mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], - MT7925_RXQ_BAND0, MT7925_RX_RING_SIZE, + cfg->rxq_band0, MT7925_RX_RING_SIZE, MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE); if (ret) return ret; =20 + /* rx auxiliary data (MT7927: management frames on ring 7) */ + if (cfg->rxq_data2) { + ret =3D mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], + cfg->rxq_data2, + MT7925_RX_MCU_RING_SIZE, + MT_RX_BUF_SIZE, + MT_RX_DATA_RING_BASE); + if (ret) + return ret; + } + ret =3D mt76_init_queues(dev, mt792x_poll_rx); if (ret < 0) return ret; @@ -373,6 +495,7 @@ static int mt7925_pci_probe(struct pci_dev *pdev, dev->hif_ops =3D &mt7925_pcie_ops; is_mt7927_hw =3D (pdev->device =3D=3D 0x6639 || pdev->device =3D=3D 0x792= 7); dev->irq_map =3D is_mt7927_hw ? &mt7927_irq_map : &irq_map; + dev->dma_config =3D is_mt7927_hw ? &mt7927_dma_cfg : &mt7925_dma_cfg; mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev); =20 diff --git a/drivers/net/wireless/mediatek/mt76/mt792x.h b/drivers/net/wire= less/mediatek/mt76/mt792x.h index 38790ef83e51..8a10438e26f9 100644 --- a/drivers/net/wireless/mediatek/mt76/mt792x.h +++ b/drivers/net/wireless/mediatek/mt76/mt792x.h @@ -203,6 +203,26 @@ struct mt792x_irq_map { } rx; }; =20 +struct mt792x_dma_config { + /* RX ring indices */ + u8 rxq_band0; + u8 rxq_mcu_wm; + u8 rxq_data2; /* 0 =3D not used */ + + /* Prefetch configuration */ + void (*dma_prefetch)(struct mt792x_dev *dev); + + /* GLO_CFG quirk bits to set/clear after DMA enable */ + u32 glo_cfg_set; + u32 glo_cfg_clear; + + /* GLO_CFG_EXT1 register address (chip-specific MMIO base) */ + u32 glo_cfg_ext1; + + /* Pre-ring-setup hook (NULL =3D not needed) */ + int (*pre_ring_setup)(struct mt792x_dev *dev); +}; + #define mt792x_init_reset(dev) ((dev)->hif_ops->init_reset(dev)) #define mt792x_dev_reset(dev) ((dev)->hif_ops->reset(dev)) #define mt792x_mcu_init(dev) ((dev)->hif_ops->mcu_init(dev)) @@ -250,6 +270,7 @@ struct mt792x_dev { struct mt76_connac_coredump coredump; const struct mt792x_hif_ops *hif_ops; const struct mt792x_irq_map *irq_map; + const struct mt792x_dma_config *dma_config; =20 struct work_struct ipv6_ns_work; struct delayed_work mlo_pm_work; diff --git a/drivers/net/wireless/mediatek/mt76/mt792x_dma.c b/drivers/net/= wireless/mediatek/mt76/mt792x_dma.c index 1ddec7788b66..4a6794ca86b9 100644 --- a/drivers/net/wireless/mediatek/mt76/mt792x_dma.c +++ b/drivers/net/wireless/mediatek/mt76/mt792x_dma.c @@ -90,42 +90,36 @@ EXPORT_SYMBOL_GPL(mt792x_rx_poll_complete); #define PREFETCH(base, depth) ((base) << 16 | (depth)) static void mt792x_dma_prefetch(struct mt792x_dev *dev) { - if (is_mt7925(&dev->mt76)) { - /* rx ring */ - mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x4)); - mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0040, 0x4)); - mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x0080, 0x4)); - mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x00c0, 0x4)); - /* tx ring */ - mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0100, 0x10)); - mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x0200, 0x10)); - mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x0300, 0x10)); - mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x0400, 0x10)); - mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0500, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0540, 0x4)); - } else { - /* rx ring */ - mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4)); - mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4)); - mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4)); - mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4)); - mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4)); - /* tx ring */ - mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4)); - mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4)); + /* mt7925 family uses per-chip prefetch via dma_config callback */ + if (dev->dma_config && dev->dma_config->dma_prefetch) { + dev->dma_config->dma_prefetch(dev); + return; } + + /* mt7921/mt7922 legacy prefetch */ + /* rx ring */ + mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4)); + mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4)); + mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4)); + mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4)); + mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4)); + /* tx ring */ + mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4)); + mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4)); } =20 int mt792x_dma_enable(struct mt792x_dev *dev) { - /* configure perfetch settings */ + const struct mt792x_dma_config *cfg =3D dev->dma_config; + + /* configure prefetch settings */ mt792x_dma_prefetch(dev); =20 /* reset dma idx */ @@ -150,8 +144,16 @@ int mt792x_dma_enable(struct mt792x_dev *dev) mt76_set(dev, MT_WFDMA0_GLO_CFG, MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); =20 - if (is_mt7925(&dev->mt76)) { - mt76_rmw(dev, MT_UWFDMA0_GLO_CFG_EXT1, BIT(28), BIT(28)); + /* Apply chip-specific GLO_CFG quirk bits from DMA config */ + if (cfg) { + if (cfg->glo_cfg_set) + mt76_set(dev, MT_WFDMA0_GLO_CFG, cfg->glo_cfg_set); + if (cfg->glo_cfg_clear) + mt76_clear(dev, MT_WFDMA0_GLO_CFG, cfg->glo_cfg_clear); + } + + if (cfg && cfg->glo_cfg_ext1) { + mt76_rmw(dev, cfg->glo_cfg_ext1, BIT(28), BIT(28)); mt76_set(dev, MT_WFDMA0_INT_RX_PRI, 0x0F00); mt76_set(dev, MT_WFDMA0_INT_TX_PRI, 0x7F00); } diff --git a/drivers/net/wireless/mediatek/mt76/mt792x_regs.h b/drivers/net= /wireless/mediatek/mt76/mt792x_regs.h index a8c8d7d6f565..1b9b51d43f79 100644 --- a/drivers/net/wireless/mediatek/mt76/mt792x_regs.h +++ b/drivers/net/wireless/mediatek/mt76/mt792x_regs.h @@ -299,7 +299,9 @@ #define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) #define MT_WFDMA0_GLO_CFG_RX_WB_DDONE BIT(13) #define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15) +#define MT_WFDMA0_GLO_CFG_CSR_LBK_RX_Q_SEL_EN BIT(20) #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) +#define MT_WFDMA0_GLO_CFG_ADDR_EXT_EN BIT(26) #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) #define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30) @@ -366,6 +368,16 @@ #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) =20 +/* MT7927 packed prefetch registers */ +#define MT_WFDMA_PREFETCH_CTRL MT_WFDMA_EXT_CSR(0x30) +#define MT_WFDMA_PREFETCH_CFG0 MT_WFDMA_EXT_CSR(0xf0) +#define MT_WFDMA_PREFETCH_CFG1 MT_WFDMA_EXT_CSR(0xf4) +#define MT_WFDMA_PREFETCH_CFG2 MT_WFDMA_EXT_CSR(0xf8) +#define MT_WFDMA_PREFETCH_CFG3 MT_WFDMA_EXT_CSR(0xfc) + +/* MT7927 GLO_CFG extended register */ +#define MT_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4) + #define MT_SWDEF_BASE 0x41f200 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) #define MT_SWDEF_MODE MT_SWDEF(0x3c) --=20 2.53.0