From nobody Fri Apr 3 01:26:30 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 115BB3E275D for ; Wed, 25 Mar 2026 16:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774454531; cv=none; b=n6eOeJaIyLWVvxdQH8JqKGXwDB4Jo8LEmk+mMhOAvsUsyhxrTk46wf1/UqdNWoP6bCXR2agqrBzghMG/DrZwxsngKDEuGiDhoe8uJmKdfXhJetfRoW/vHPcPUrc2EQXBW4178+jaMDdJ7HpUY31LOMIJM58JdV3h//nutW/Q1D0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774454531; c=relaxed/simple; bh=iesU595OGFCbBU7AuhLZ7LNQE3wjfBByFcgyyl3r1YM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=aHEaAbN8Kh3LVqJ8wGcZlflzZl1A3JEVPR1i3ozEs4T65HUysHefQDTmTNw6J1kjuG/KK0O3EFMUnx8STULleC+5tCqbuEHEpK8A9VqDvxY8KATPidDg8HcHNU89EiAXBMM3Vq37tBiCKLktSC6Xp8IFg7PWeE9fZv5vzTQROAI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1w5QgA-0002Iy-8C; Wed, 25 Mar 2026 17:01:58 +0100 From: Fabian Pfitzner Date: Wed, 25 Mar 2026 17:01:49 +0100 Subject: [PATCH v3] arm64: dts: imx8mp-frdm: add sd, ethernet, wifi, usb and hdmi support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-fpf-imx8mp-frdm-v3-1-1c98eade991a@pengutronix.de> X-B4-Tracking: v=1; b=H4sIAOwGxGkC/3XNsQ6DIBDG8VcxzKWBw6rp1PdoOigceoNIwBIb4 7sXXTqYjv8vud+tLGIgjOxerCxgokiTy6EuBdND63rkZHIzEFAJgJJbbzmNSzN6boMZeSlAl8a KSglg+coHtLQc4vOVe6A4T+FzPEhyX/9bSXLJTW1Vd6u1bFA8PLr+PYfJ0XI1yHYwwQ9Rsjojk BEEbNrWoO7AnpBt275fzgXY+AAAAA== X-Change-ID: 20260224-fpf-imx8mp-frdm-402c4df06302 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabian Pfitzner X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: f.pfitzner@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Add support for the following new features: - SD Card - Ethernet (FEC + EQOS) - Wifi - USB - HDMI The imx8mp-evk dt and the NXP downstream imx8mp-frdm dts were taken as a reference. Signed-off-by: Fabian Pfitzner --- Changes in v3: - Rebased onto for-next branch: https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git/log/?h= =3Dfor-next - Link to v2: https://lore.kernel.org/r/20260316-fpf-imx8mp-frdm-v2-1-e2e8a= adecb2f@pengutronix.de Changes in v2: - Reorder nodes by name - Remove unused "realtek,clkout-disable" property - Link to v1: https://lore.kernel.org/r/20260224-fpf-imx8mp-frdm-v1-1-d7f3b= 57c18e0@pengutronix.de --- arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 407 ++++++++++++++++++++++= ++++ 1 file changed, 407 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boo= t/dts/freescale/imx8mp-frdm.dts index d69d78fed4e1b151be3948bb8ef0888eb016c667..b301cf3d425b1b748e2be8f223b= b703e7a4355f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -42,6 +42,67 @@ memory@40000000 { reg =3D <0x0 0x40000000 0 0xc0000000>, <0x1 0x00000000 0 0x40000000>; }; + + native-hdmi-connector { + compatible =3D "hdmi-connector"; + label =3D "HDMI OUT"; + type =3D "a"; + + port { + hdmi_in: endpoint { + remote-endpoint =3D <&hdmi_tx_out>; + }; + }; + }; + + reg_usdhc2_vmmc: regulator-sd { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB_VBUS"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pcal6416_1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc1_vmmc: regulator-wifi-vmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "WLAN_EN"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&pcal6416_1 10 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + enable-active-high; + startup-delay-us =3D <20000>; + }; + + reg_usdhc1_vqmmc: regulator-wifi-vqmmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "regulator-wifi-vqmmc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + enable-active-high; + }; + + sdio_pwrseq: usdhc1-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&gpio2 10 GPIO_ACTIVE_LOW>; + }; }; =20 &A53_0 { @@ -60,6 +121,147 @@ &A53_3 { cpu-supply =3D <®_arm>; }; =20 +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@2 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos_phy>; + reset-gpios =3D <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0xf0>; + snps,map-to-dma-channel =3D <4>; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy1>; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec_phy>; + eee-broken-1000t; + reset-gpios =3D <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + realtek,aldps-enable; + realtek,clkout-disable; + }; + }; +}; + + +&hdmi_pvi { + status =3D "okay"; +}; + +&hdmi_tx { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hdmi>; + status =3D "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint =3D <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status =3D "okay"; +}; + &i2c1 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; @@ -218,6 +420,32 @@ &i2c3 { status =3D "okay"; }; =20 +&lcdif3 { + status =3D "okay"; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb3_phy0 { + status =3D "okay"; +}; + +&usb3_phy1 { + vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; + +&usb_dwc3_1 { + dr_mode =3D "host"; + status =3D "okay"; +}; + &snvs_pwrkey { status =3D "okay"; }; @@ -237,6 +465,36 @@ &uart3 { status =3D "okay"; }; =20 +&usdhc1 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates =3D <200000000>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + mmc-pwrseq =3D <&sdio_pwrseq>; + vmmc-supply =3D <®_usdhc1_vmmc>; + vqmmc-supply =3D <®_usdhc1_vqmmc>; + bus-width =3D <4>; + non-removable; + no-sd; + no-mmc; + status =3D "okay"; +}; + +&usdhc2 { + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates =3D <400000000>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; +}; + &usdhc3 { assigned-clocks =3D <&clk IMX8MP_CLK_USDHC3>; assigned-clock-rates =3D <400000000>; @@ -250,6 +508,74 @@ &usdhc3 { }; =20 &iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hog>; + + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins =3D < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins =3D < + /* Pin might be required by multiple drivers + * (e. g. HDMI Audio and HDMI TX) + */ + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins =3D < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) @@ -293,6 +619,12 @@ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 >; }; =20 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins =3D < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) @@ -310,6 +642,81 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP= | MX8MP_PULL_ENABLE) >; }; =20 + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins =3D < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK --- base-commit: 6c4b48012d57f205c94f25da0c68a4027ea6daf6 change-id: 20260224-fpf-imx8mp-frdm-402c4df06302 Best regards, --=20 Fabian Pfitzner