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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0836556f6sm219985805ad.49.2026.03.24.22.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 22:44:11 -0700 (PDT) From: Yingchao Deng Date: Wed, 25 Mar 2026 13:43:47 +0800 Subject: [PATCH v7 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-extended_cti-v7-4-bb406005089f@oss.qualcomm.com> References: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> In-Reply-To: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jinlong Mao , Tingwei Zhang , Jie Gan , quic_yingdeng@quicinc.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774417433; l=4654; i=yingchao.deng@oss.qualcomm.com; s=20260324; h=from:subject:message-id; bh=8tA/1rrhluQQOhAaaei29rn2Ss2/RThN58fxl9hPMJs=; b=kPJ6va5jIdBC1luKdNocyudY3wzT2OYkTluHO1R/HtuMWrwpokb9DAG6Jv97cbz6jci6+Z6Ti 6OStKD1lfPDBsz4zmeoCXv8H7A1fqyT/sRvuwPlSrS8Bih4EWbKRC61 X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=5tp504LR96W2IVT3sAbRCqWtoG16CxJVUnXJSfU8NlQ= X-Authority-Analysis: v=2.4 cv=fOk0HJae c=1 sm=1 tr=0 ts=69c3762d cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=PrhcshflQRWEcWOJaRQA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: kL_I_1FHfWrBbuUQVsJFfiNruo7fOnoh X-Proofpoint-ORIG-GUID: kL_I_1FHfWrBbuUQVsJFfiNruo7fOnoh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDAzOCBTYWx0ZWRfX+RUajFeC1rVS rJ9meOZOsAvTITb4p7jeIbvJiE+QJC68ddSgw9ljYJ+G29XP9w2hJh6gOyRbJ792GuuxlQrW9Rt ZlJJHlFo4cB/hs7XrSOst/6lNkvVYNAe+SIjF2h6xixipebMw55puyBLjTtE32k8W9acEsvH4t4 dEb6gnZ3wJzLX9IM3cGhLRj9w8FJMFEVhWhn6hovpJ8UVkM5jJ+ZVAhOqUGoHRkDCC7CA/Ymbmo C1y6NYZoi4oSBQeI2s7kWxcylLSBgKnu3+529x2QMqbqkX64zLcG4Vo3IswuEJOEoaQje65dCSH 8cNgUi3302YJF6tMjeqnB+6ESZmPuu4BCuX45/3wlaf2G3dVI/OLxO9NxJ/G2AOKzgUhkwGn1rt FoSzg6OohnZueukohgB6qMMeXwfvBTMbBulu3wVP47mooALvgI9qNTKbDO5G8qAsi4pOzHWK4RR M/57Q2445ZeB2TZcdrg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_02,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250038 Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Numbered sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI. On Qualcomm CTIs, only banked registers backed by hardware are exposed, with the number of visible banks derived from nr_trig_max. This ensures that userspace only sees registers that are actually implemented, while maintaining compatibility with existing CTI tooling. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 075f633ea9e1..123ac862d8de 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -511,18 +511,36 @@ static struct attribute *coresight_cti_regs_attrs[] = =3D { &dev_attr_appclear.attr, &dev_attr_apppulse.attr, coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)= ), + coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)= ), + coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)= ), coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 1)), + coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 2)), + coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 3)), coresight_cti_reg(chinstatus, CTICHINSTATUS), coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)), + coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)), + coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)), coresight_cti_reg(itchin, ITCHIN), coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)), + coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)), + coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)), coresight_cti_reg_rw(itchout, ITCHOUT), coresight_cti_reg(itchoutack, ITCHOUTACK), coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)), + coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)), + coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)), coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)), + coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)), + coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)), coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, @@ -533,10 +551,50 @@ static umode_t coresight_cti_regs_is_visible(struct k= object *kobj, { struct device *dev =3D kobj_to_dev(kobj); struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const char * const qcom_suffix_registers[] =3D { + "triginstatus", + "trigoutstatus", +#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS + "ittrigin", + "ittrigout", + "ittriginack", + "ittrigoutack", +#endif + }; + int i, nr, max_bank; + size_t len; =20 if (attr =3D=3D &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) return 0; =20 + /* + * Banked regs are exposed as (nr =3D 1..3). + * - Hide them on standard CTIs. + * - On QCOM CTIs, hide suffixes beyond the number of banks implied + * by nr_trig_max (32 triggers per bank). + */ + for (i =3D 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) { + len =3D strlen(qcom_suffix_registers[i]); + + if (strncmp(attr->name, qcom_suffix_registers[i], len)) + continue; + + if (kstrtoint(attr->name + len, 10, &nr)) + continue; + + if (!drvdata->is_qcom_cti) + return 0; + + if (nr < 1 || nr > 3) + return 0; + + max_bank =3D DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1; + if (nr > max_bank) + return 0; + + break; + } + return attr->mode; } =20 --=20 2.43.0