From nobody Fri Apr 3 03:00:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CA463115BC for ; Wed, 25 Mar 2026 05:44:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417445; cv=none; b=JzRLnNH5pRSc3FCIYUOjbVms9B+ekFsLHwNtYM+8TZdxNBZT+I3TF5oQX7WdbbzhsrKQx4ddJB8jI95jUEejCPKNEO1hMrfTVORoQ1cOj8z5RETga1od0KAEIwxbg/7EcJ8S59HUgMUYMYcJXvD9prDmX8R7O2Y3PIIcYhynUco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417445; c=relaxed/simple; bh=qAzZ+u/woLYDbL6f/lfFrwEnDhUdQIVjsv7FGZH74vE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FYL40GhE6HkW685LZw0YWY6fg06RehyKi1WJ4GGUoElJZNNxGs7NaqIm/z29u7pDTDAuSH9h5XfJk1eunuwVEZOM2fUgFCsUklFoSvacHLq6LdFEJ5NTcDFmnGnmS1LrqgTq7IpXlRGBA8Q1feySdGnwSmEnteLyT05Zy8fP47o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Ig+5FkGC; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=EuDKMoB9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Ig+5FkGC"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="EuDKMoB9" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62P4MsVU3110426 for ; Wed, 25 Mar 2026 05:44:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 25fbS8mRuUBMqAXg6T/z6v9tHy/oYlGG8Pqk/K9vN7I=; b=Ig+5FkGCAbUc3AUE lCSSO7QnCBIRlHpyNQd7YaXWAB9WblZCVGQUtOG3F2TlXXmxLThGwS2vnessL1wX 2Qi426EWbhnTT382mRrGb0Bo0TytBN8Fo+/5D3m+BAhSM96A1sCnicmLkBmOwkO6 0rTz42x7R3JCk8GaVyTp8uh6vKlMcjpBozJl7zwht6Mik7c5jBdGYa4tuyWTAt8Q wRVyzsibalJpWMGwXPHMddMeLZC48llE4BryjJO+gGLG6Uf0KTS97D4OUD+K0giO wUhPgcZAy/55mrxZlhl+jKrJ7UHxjLxyq+rSc7LuLyaucBoXNv9KVoXT3A4yA3UO cuQiRg== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d3vhvtwqy-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Mar 2026 05:44:02 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2b059ab124dso64612645ad.1 for ; Tue, 24 Mar 2026 22:44:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774417442; x=1775022242; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=25fbS8mRuUBMqAXg6T/z6v9tHy/oYlGG8Pqk/K9vN7I=; b=EuDKMoB96TYHULAyWdgM4H5YItMQISawG/9OFAM2yLFAKKYD4CExmnz8NLR5lNTakD wX7zLXcLvNSyfBc84sQdi1GHAPcf2kjhkfUEsj3OY1GCyJO70WTzfCqWq+objYARR4m6 Mmt44Dj9/niGVRi9UlwvQ95LbJ8hiC9Mx0bGS9zGZMWCLrqLxQAcrqBay6AkPykZW+az yp78BG+821/fgXhHIZRtO/gtiRWkPbuykYdp6FbW76ichjy3wPiqI2warPODgVvZnve6 XuhaSO6fYYQnaXmdY6UCRSklVw2qvf6RmGRbVv5CkXJ3LPMg8k505ZmwBMIYoUoOjmLg /VYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774417442; x=1775022242; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=25fbS8mRuUBMqAXg6T/z6v9tHy/oYlGG8Pqk/K9vN7I=; b=lNR2qrF60Y21f7msgGnjbNw6k2wKPZv4e86Ix39M+rBBS/xI3EuE4oFN/7gjU6np+F fU/3Axw3p31zTpD/e4B03+tyCX1Hxu2SfqNmWHpBOty4qxDs3WtWAhGKuKvpirMj8Q/n ew1Van28FMd+m4St9URHrVwekGOtQOrn5G9x49DuLPA4/+IrUW11QlVTB0S0wxwcllrw 7Ss0HFs26g1bAILV0Ezn0gYACFT0coEdSU/gy0fgkhhBCHEKg3KO13Sj36X5AbP5Hu3n I45sgx5e3tyO2w+ZgRShdDaE1UGF8W7Q1dLPo/VIYob5n3395QV7sLhvc//06zBdpdx7 iY1Q== X-Forwarded-Encrypted: i=1; AJvYcCWeUW9wwzRmKH/tO9RI+LPgdJ19vIS0CIRVkmV7ca15V5HDBBUYt/I64dw3y00ajNE37tRJMHtw8VH9oVM=@vger.kernel.org X-Gm-Message-State: AOJu0Yzu38jICBiETkUruNnNtm8enqXp3qUaQXSFPLmLCnN7EYeyMGVT awGCmc0NyRyp9iMFtG6wLSh9KG9nCCpD6niGxWGK9nuBMJrJ/pZiBKkABdXuolCthQExnf5IbQU ZGPMyLum/oaeklDS2PXJAeLJZj7QUuGCYD210EAFrG6IqBGtG7YBOHi5OrmYL7/g9qGr954gS2R o= X-Gm-Gg: ATEYQzzWqKPLW8J7Dty73GUBJJHEBTlbN1W0fmnZbAANGYBDQ/N+0PGPaQ98nZ0Zpgl MdaZ/P055LL2zi1iUNmWKFvNWgYzSxqw+9L7JGzmW+kbybnl1+dE3aX3hCaqVyIuBCj6NQaGH+0 KU0UqeVXHJqtw57iRAzj5kc6C3bvCnTutk2MN8mVwcfoP7azPpO5ywRbkkTUjYSI9M2gxmg8hMx 2R9ITIz5Jmgu13hS5SYPjPBCMUSEMLyBCJLZ32QnMMP8l/j3YK6INUq7nppZVFJl/7z+BhsRVB0 iCWuX3PU9w4SnDlFhRDXpfYPE8fxnAhURG4QSj/HiHeCq5lNVmX2skU9AZ6rTKMLVk1NrF1wFj3 9Ki1kKBrctWC1/CLnQIJA8jSEzeYahe/+BN0i+CR6rRglVVprUDItCzIEFwT+YQFanoxm08pmtx JZ6a7+qyR/obrJrw== X-Received: by 2002:a17:903:234a:b0:2ae:4445:f39a with SMTP id d9443c01a7336-2b0b099d271mr24386435ad.7.1774417441582; Tue, 24 Mar 2026 22:44:01 -0700 (PDT) X-Received: by 2002:a17:903:234a:b0:2ae:4445:f39a with SMTP id d9443c01a7336-2b0b099d271mr24386175ad.7.1774417440961; Tue, 24 Mar 2026 22:44:00 -0700 (PDT) Received: from jinlmao-gv.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0836556f6sm219985805ad.49.2026.03.24.22.43.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 22:44:00 -0700 (PDT) From: Yingchao Deng Date: Wed, 25 Mar 2026 13:43:44 +0800 Subject: [PATCH v7 1/4] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-extended_cti-v7-1-bb406005089f@oss.qualcomm.com> References: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> In-Reply-To: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jinlong Mao , Tingwei Zhang , Jie Gan , quic_yingdeng@quicinc.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774417433; l=10928; i=yingchao.deng@oss.qualcomm.com; s=20260324; h=from:subject:message-id; bh=qAzZ+u/woLYDbL6f/lfFrwEnDhUdQIVjsv7FGZH74vE=; b=0Kh5Lc/nzRfpzwGgV7GyzeF6MuKhH7iWTmlVU6okSE1pU+fbUygtkD5sBgvzeufPgQgZggox0 XwhjY48/XQTCfZQzqSbUb8uHubuvZ8ewW83DFQpsqUCXURAkMztduz1 X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=5tp504LR96W2IVT3sAbRCqWtoG16CxJVUnXJSfU8NlQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDAzOCBTYWx0ZWRfXwNuqL4QSCm2k cWTeGIhYdmQeRqTV2v5a+wcNXAZTNK8UPEecGQqtCWwS+dc/sk+KU5D/UHpNsRyVx3xxYAirH63 OJbXFBJgVRgC9Z1HH0EaFMH1wrWd8r4ENAISGKU8aUbQT4dokB/sHeXflaJMt7P3s77pyDsSjx/ vvkwq+MNsORl0XKtc9ai6btT4HvPwzNCPp4eiZVV9jGYOUiQ2PIdogBbcOsDtrFXf7RZYcbWPOb q6LO3F+9z7saViDUG74Bob6nEPubarih1CX135sJZvFEgj4u/mfq78nMBY7aBmANQ88ZKzU+lXe A2WZmtBvVkKjvTtjzH1zBXZPuKcGSWP17pJi/juJEpeMK856XMPkSJ1e1h4EQSQtQiUhk2kvUyz PS2Sw1KmDz/9maPFC4rmqkRDT6rI2QbVd8LPEUIzWCpyHCd7YS6dAA+y8DTO6vvHNf/ARTylnrj jJlVh64t9LMhsM1XBxg== X-Authority-Analysis: v=2.4 cv=P5M3RyAu c=1 sm=1 tr=0 ts=69c37622 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=gAozoMUHzvVhJ8WkzYYA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: 0zwPGJdrAtp6OcHZMvrAFUKKlPARlx_w X-Proofpoint-GUID: 0zwPGJdrAtp6OcHZMvrAFUKKlPARlx_w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_02,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250038 Replace the fixed-size u32 fields in the cti_config and cti_trig_grp structure with dynamically allocated bitmaps and arrays. This allows memory to be allocated based on the actual number of triggers during probe time, reducing memory footprint and improving scalability for platforms with varying trigger counts. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 57 ++++++++++++++++--= ---- .../hwtracing/coresight/coresight-cti-platform.c | 16 +++--- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 13 ++--- drivers/hwtracing/coresight/coresight-cti.h | 12 ++--- 4 files changed, 62 insertions(+), 36 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 2f4c9362709a..d5cb94e33184 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 -static void cti_set_default_config(struct device *dev, - struct cti_drvdata *drvdata) +static int cti_set_default_config(struct device *dev, + struct cti_drvdata *drvdata) { struct cti_config *config =3D &drvdata->config; u32 devid; @@ -181,6 +181,26 @@ static void cti_set_default_config(struct device *dev, config->nr_trig_max =3D CTIINOUTEN_MAX; } =20 + config->trig_in_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_= KERNEL); + if (!config->trig_in_use) + return -ENOMEM; + + config->trig_out_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, GFP= _KERNEL); + if (!config->trig_out_use) + return -ENOMEM; + + config->trig_out_filter =3D devm_bitmap_zalloc(dev, config->nr_trig_max, = GFP_KERNEL); + if (!config->trig_out_filter) + return -ENOMEM; + + config->ctiinen =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), G= FP_KERNEL); + if (!config->ctiinen) + return -ENOMEM; + + config->ctiouten =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), = GFP_KERNEL); + if (!config->ctiouten) + return -ENOMEM; + config->nr_ctm_channels =3D CTI_DEVID_CTMCHANNELS(devid); =20 /* Most regs default to 0 as zalloc'ed except...*/ @@ -189,6 +209,7 @@ static void cti_set_default_config(struct device *dev, config->enable_req_count =3D 0; =20 config->asicctl_impl =3D !!FIELD_GET(GENMASK(4, 0), devid); + return 0; } =20 /* @@ -219,8 +240,10 @@ int cti_add_connection_entry(struct device *dev, struc= t cti_drvdata *drvdata, cti_dev->nr_trig_con++; =20 /* add connection usage bit info to overall info */ - drvdata->config.trig_in_use |=3D tc->con_in->used_mask; - drvdata->config.trig_out_use |=3D tc->con_out->used_mask; + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, + tc->con_in->used_mask, drvdata->config.nr_trig_max); + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, + tc->con_out->used_mask, drvdata->config.nr_trig_max); =20 return 0; } @@ -242,12 +265,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct dev= ice *dev, int in_sigs, if (!in) return NULL; =20 + in->used_mask =3D devm_bitmap_alloc(dev, in_sigs, GFP_KERNEL); + if (!in->used_mask) + return NULL; + out =3D devm_kzalloc(dev, offsetof(struct cti_trig_grp, sig_types[out_sigs]), GFP_KERNEL); if (!out) return NULL; =20 + out->used_mask =3D devm_bitmap_alloc(dev, out_sigs, GFP_KERNEL); + if (!out->used_mask) + return NULL; + tc->con_in =3D in; tc->con_out =3D out; tc->con_in->nr_sigs =3D in_sigs; @@ -263,7 +294,6 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) { int ret =3D 0; int n_trigs =3D drvdata->config.nr_trig_max; - u32 n_trig_mask =3D GENMASK(n_trigs - 1, 0); struct cti_trig_con *tc =3D NULL; =20 /* @@ -274,8 +304,8 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) if (!tc) return -ENOMEM; =20 - tc->con_in->used_mask =3D n_trig_mask; - tc->con_out->used_mask =3D n_trig_mask; + bitmap_fill(tc->con_in->used_mask, n_trigs); + bitmap_fill(tc->con_out->used_mask, n_trigs); ret =3D cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); return ret; } @@ -288,7 +318,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; - u32 trig_bitmask; u32 chan_bitmask; u32 reg_value; int reg_offset; @@ -298,18 +327,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_= chan_op op, (trigger_idx >=3D config->nr_trig_max)) return -EINVAL; =20 - trig_bitmask =3D BIT(trigger_idx); - /* ensure registered triggers and not out filtered */ if (direction =3D=3D CTI_TRIG_IN) { - if (!(trig_bitmask & config->trig_in_use)) + if (!(test_bit(trigger_idx, config->trig_in_use))) return -EINVAL; } else { - if (!(trig_bitmask & config->trig_out_use)) + if (!(test_bit(trigger_idx, config->trig_out_use))) return -EINVAL; =20 if ((config->trig_filter_enable) && - (config->trig_out_filter & trig_bitmask)) + test_bit(trigger_idx, config->trig_out_filter)) return -EINVAL; } =20 @@ -687,7 +714,9 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); =20 /* initialise CTI driver config values */ - cti_set_default_config(dev, drvdata); + ret =3D cti_set_default_config(dev, drvdata); + if (ret) + return ret; =20 pdata =3D coresight_cti_get_platform_data(dev); if (IS_ERR(pdata)) { diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers= /hwtracing/coresight/coresight-cti-platform.c index 4eff96f48594..af5f45c6fcf0 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct dev= ice *dev, goto create_v8_etm_out; =20 /* build connection data */ - tc->con_in->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ - tc->con_out->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ =20 /* * The EXTOUT type signals from the ETM are connected to a set of input @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct devi= ce *dev, goto of_create_v8_out; =20 /* Set the v8 PE CTI connection data */ - tc->con_in->used_mask =3D 0x3; /* sigs <0 1> */ + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ tc->con_in->sig_types[0] =3D PE_DBGTRIGGER; tc->con_in->sig_types[1] =3D PE_PMUIRQ; - tc->con_out->used_mask =3D 0x7; /* sigs <0 1 2 > */ + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ tc->con_out->sig_types[0] =3D PE_EDBGREQ; tc->con_out->sig_types[1] =3D PE_DBGRESTART; tc->con_out->sig_types[2] =3D PE_CTIIRQ; @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device= *dev, goto of_create_v8_out; =20 /* filter pe_edbgreq - PE trigout sig <0> */ - drvdata->config.trig_out_filter |=3D 0x1; + set_bit(0, drvdata->config.trig_out_filter); =20 of_create_v8_out: return ret; @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp= *tgrp, if (!err) { /* set the signal usage mask */ for (idx =3D 0; idx < tgrp->nr_sigs; idx++) - tgrp->used_mask |=3D BIT(values[idx]); + set_bit(values[idx], tgrp->used_mask); } =20 kfree(values); @@ -331,7 +331,9 @@ static int cti_plat_process_filter_sigs(struct cti_drvd= ata *drvdata, =20 err =3D cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); if (!err) - drvdata->config.trig_out_filter |=3D tg->used_mask; + bitmap_or(drvdata->config.trig_out_filter, + drvdata->config.trig_out_filter, + tg->used_mask, drvdata->config.nr_trig_max); =20 kfree(tg); return err; diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 4c0a60840efb..88f8a08ef778 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -720,12 +720,9 @@ static ssize_t trigout_filtered_show(struct device *de= v, { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - int size =3D 0, nr_trig_max =3D cfg->nr_trig_max; - unsigned long mask =3D cfg->trig_out_filter; + int nr_trig_max =3D cfg->nr_trig_max; =20 - if (mask) - size =3D bitmap_print_to_pagebuf(true, buf, &mask, nr_trig_max); - return size; + return bitmap_print_to_pagebuf(true, buf, cfg->trig_out_filter, nr_trig_m= ax); } static DEVICE_ATTR_RO(trigout_filtered); =20 @@ -934,9 +931,8 @@ static ssize_t trigin_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_in->used_mask; =20 - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); + return bitmap_print_to_pagebuf(true, buf, con->con_in->used_mask, cfg->nr= _trig_max); } =20 static ssize_t trigout_sig_show(struct device *dev, @@ -948,9 +944,8 @@ static ssize_t trigout_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_out->used_mask; =20 - return bitmap_print_to_pagebuf(true, buf, &mask, cfg->nr_trig_max); + return bitmap_print_to_pagebuf(true, buf, con->con_out->used_mask, cfg->n= r_trig_max); } =20 /* convert a sig type id to a name */ diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index c5f9e79fabc6..ef079fc18b72 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -68,7 +68,7 @@ struct fwnode_handle; */ struct cti_trig_grp { int nr_sigs; - u32 used_mask; + unsigned long *used_mask; int sig_types[]; }; =20 @@ -145,17 +145,17 @@ struct cti_config { int enable_req_count; =20 /* registered triggers and filtering */ - u32 trig_in_use; - u32 trig_out_use; - u32 trig_out_filter; + unsigned long *trig_in_use; + unsigned long *trig_out_use; + unsigned long *trig_out_filter; bool trig_filter_enable; u8 xtrig_rchan_sel; =20 /* cti cross trig programmable regs */ u32 ctiappset; u8 ctiinout_sel; - u32 ctiinen[CTIINOUTEN_MAX]; - u32 ctiouten[CTIINOUTEN_MAX]; + u32 *ctiinen; + u32 *ctiouten; u32 ctigate; u32 asicctl; }; --=20 2.43.0 From nobody Fri Apr 3 03:00:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A72030F535 for ; Wed, 25 Mar 2026 05:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417448; cv=none; b=VKOexQaiguVnFGFMPROL1gzRH4E7Xme//lg0jNLpt2fGpC21nAJKmjv8kVvOrkI8oVl6TWYMUtVIghqFLhYUpjQy+SeLwVkJxgf1Rct77UW8r0+Nat3Lpnv1rHWFON9xBlfPWqLJkHoNaDwIpMLYRMnsIVIP/ZGbketokCSmwK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417448; c=relaxed/simple; bh=7Av2HAUAr7KB5Ak4a2H20M+seSJyBiILEkz7dpvzJfA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CH3h+scH3pEF2Q5L6DYZQy74s6hEW+EsXl/+hOwVbBtDp5X9CBl/qzg5WPQXsDFOdmpKhWvf/IUJ61NaIUTwKg3MY0VZMf/2isRbvFpHKZ6fxuigcA1yhQfE+l2hYwL++MHWVamEeePwl0pEHT4uLKdnBpAVhJnOdhAdkkDZ3YA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Mr94mDjb; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=QbP8X+e0; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Mr94mDjb"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="QbP8X+e0" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62P2J84X3057321 for ; Wed, 25 Mar 2026 05:44:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 1uROBrYURmQMKmWYhSbrHteOFKQsLCjR237xB3AYYOI=; b=Mr94mDjb2yNvU7yw Gs+bsDbAGwj1bFgqGYMVnoh1yvJTR5CjDhG7N2CANnqEENGIzHGuC+RaiMyBPcuL p/ZQ//lO2lwaL0h94YAkgBxs7OXFtxwLkNvH9JDtgLpaAu7gkITvaYYlIWQ8XExp W77KQZp0CHR3674LrTjcYLAy9twGSiJBQ3xL6mUceZ+JoZXNhYjzvAMxPrPxLWyN +XYuQY1TIDnkVoh0Im5kISPCIjZ5ey9RHNgHIjrve+z9SwFaotDhxp3IgnLABUdA Z7KBXdW1yD6ujsbsia8qzFLC+RFJGPQ2vRfb7PAMboTtU4KB9KqGKQ1FCTNveK8/ HGRAdA== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d46tp0jjd-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Mar 2026 05:44:06 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2adc527eaf5so19473885ad.0 for ; Tue, 24 Mar 2026 22:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774417445; x=1775022245; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1uROBrYURmQMKmWYhSbrHteOFKQsLCjR237xB3AYYOI=; b=QbP8X+e0gE87tFN1NHAuX38HmFQQ9ngBxq7NUWJ1Czvof9Hh6cEhUQsmc9SgEgxNyP zc0Li0Ejj6bdI2YowxyI7ejeR5z+Xur9dmDF0lrk7QH4/CajIGvLVaxtN3A5syOLqCNp b/MCDfd+CQpY5kKk6H+RKjUVsCrwh3peTC102lINjltjJabJ4vzG83Dit6TlQiEZ7FBx QEsRtBsA34J1fMV8Rmiqo3EWERtfxa8xIBofqbJ0I9cbEOm+yVR0ljHbvm9VTlIgQjTP 7vmVLeu77vPWouCf54QaZmDACqMeIk1N3IeM9SEkQwo6j/pjZTJei/KIYjNFL+cwrD5W CDZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774417445; x=1775022245; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1uROBrYURmQMKmWYhSbrHteOFKQsLCjR237xB3AYYOI=; b=r+mopAXxaBrPtsoagnboavSuzFoqq8Ynw6A/PFtXb9NRb3F3LZo2lOs3UJ3QFolorN Xi88HQ6lro+8qmMF4Z8T9bJhupuqShRMbKbDaGQs1gmV7ghPREit5uE24N7Tm1LpWwxW UAMq4IISj17ScxDfqiTdTCW2SWa9fCutP2tSqo+Snf+OmBmgMS9XvVEp837LKvjrNrfU Ra0yrq2+oAtmg1KDYhrrJQEgUvX+19go4/5XXJLC5Zg6Dxy64x5L+L4OESrZJTMrGtYv /F+UTuC5UbfyoBHRqjPx7xp4QvTSLX4E84s1koaZDGA+CqpXZHYlmXoHZ7bf4Y2z7vKZ vuvg== X-Forwarded-Encrypted: i=1; AJvYcCWrEqRQukFUNgYVhSLjb1jALRToVRGrKfd/sL6ht84ihJf23HuLOXgsFNIhVW7NKBRcMNLwiE85lwntED4=@vger.kernel.org X-Gm-Message-State: AOJu0YyoHWqZ7GMarfgOSRKql5BUjHI5PsUOcRWoCdg6D+vuzaPOe+r8 BuDHINgtPiZ00k8Xz7eAjJx6s7ESSnqm2Lw0/alSr+V3Odm3dhbdICr8F8qs3ch72XWCVZKiSJm P6zHr4Tk26n4v8dQPZObjIJlP5JVPlNW8qda7kcDHhByatbCUe/tVWyF3azIojjZWZYdVApkATD s= X-Gm-Gg: ATEYQzximuvRgbK7R23NO9FPCOXWz3hANyKu8FAOqNVCLQUrH5vrPZBvqD749vGnqtj lK5e596uesADDrvs3/+faPvzc2RIGN6lK7Zx9HUL3N6WycM3nNl3Ro1yN8ErXLUwQagjG0Wp9fL Co4Y3EXMeIXk+oa9RPpUOIhXNneQxYQKtjbOUvmAmZo1QJiCKJw16lee/rx/rklpktfX5dNO9Ix eAmZAnvsch2iD4FFVpKx7SF9p4RYK94ZMUkX1VNsAme6nn6NO0jeu9j29f/stKO/qeUlXffAhvu u6SEwLmnPBEq6pZDnCxntMvpFtQPrxEaZJZYesC18Gz7bDI8ZXH/59iGEziUm2H3/zo5JFJD78k Y8tnBz1L+ECX1sF0dWiqHpUTR5hbiUC1/JApJ6rjk6pYjp9GvNBRaMSDyPH3n+k/UmjfCu89Xqg qSHWNKHdaJazhDLg== X-Received: by 2002:a17:902:e784:b0:2b0:4eeb:f80a with SMTP id d9443c01a7336-2b0b0ab3a21mr25199055ad.29.1774417445413; Tue, 24 Mar 2026 22:44:05 -0700 (PDT) X-Received: by 2002:a17:902:e784:b0:2b0:4eeb:f80a with SMTP id d9443c01a7336-2b0b0ab3a21mr25198645ad.29.1774417444850; Tue, 24 Mar 2026 22:44:04 -0700 (PDT) Received: from jinlmao-gv.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0836556f6sm219985805ad.49.2026.03.24.22.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 22:44:04 -0700 (PDT) From: Yingchao Deng Date: Wed, 25 Mar 2026 13:43:45 +0800 Subject: [PATCH v7 2/4] coresight: cti: encode trigger register index in register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-extended_cti-v7-2-bb406005089f@oss.qualcomm.com> References: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> In-Reply-To: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jinlong Mao , Tingwei Zhang , Jie Gan , quic_yingdeng@quicinc.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774417433; l=6063; i=yingchao.deng@oss.qualcomm.com; s=20260324; h=from:subject:message-id; bh=7Av2HAUAr7KB5Ak4a2H20M+seSJyBiILEkz7dpvzJfA=; b=0fa+nmYg96nSHuDJGRyhZxDSsgOWgfT19ZguSiSwp/vuHjyKHTiCh5Iv1Ms+1Yb0seEIvbBxL Iy4Sk6rijZ3CEYOla+zqiEFOdEYaibAZICIYxobNu9pxZ9OjWEDc7mn X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=5tp504LR96W2IVT3sAbRCqWtoG16CxJVUnXJSfU8NlQ= X-Proofpoint-ORIG-GUID: 88eges2RXSdD_NOKtXLzMYzwXb-DWUV4 X-Authority-Analysis: v=2.4 cv=F4lat6hN c=1 sm=1 tr=0 ts=69c37626 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=JIbpoTx20AKeDh2nFAsA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: 88eges2RXSdD_NOKtXLzMYzwXb-DWUV4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDAzOCBTYWx0ZWRfX31Wp6Rdv6EjP zf8aHlPH4zpvrOXoWRN5kXiPpNQ7uS9WC255DyVBNyiI0TQmytQLL7SbozRJ/vgxHAQV9l7SsCV pXuKOcwcxijpg5B1H0/4ZW/TTuC3cBbpybtXlBCOKkrLocU5KaD+sVhRIJoabk+fQnfmIEjEyfI vMPIr6bJWOzEUzgJmTP99SHNxcEW2TBukqcQUwzUNyb9r/Ua6tFF8Vj+BgprJHtGaOSlLAsQKGv 8B4iYgErcBc0VbYSHhE99hbHQV9fBPt29O7y9SReeGdvuiSPp5R5ys5BPBUAWiegSp22kPjIMA3 B7u6d8XaExKgqdyKyJEyDKCAL7ongbTuziMFvfbJTm6TRWqd25kEI7Nh55kaxNq03c2HtRYf1Mf jXDU55x9us1V8oZOQ3fjmkz0C8FYp6J4KoBWcgP3Ahgog0AuqDLF6S6OIpYExs+A4US/bu8D1x9 Qk9mjgHEEnI+u3XtH/Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_02,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250038 Introduce a small encoding to carry the register index together with the base offset in a single u32, and use a common helper to compute the final MMIO address. This refactors register access to be based on the encoded (reg, nr) pair, reducing duplicated arithmetic and making it easier to support variants that bank or relocate trigger-indexed registers. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 31 +++++++++++++++----= ---- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 4 +-- drivers/hwtracing/coresight/coresight-cti.h | 17 ++++++++++--- 3 files changed, 36 insertions(+), 16 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index d5cb94e33184..023993475a2e 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -42,6 +42,14 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) =20 +static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, u32 reg) +{ + u32 offset =3D CTI_REG_CLR_NR(reg); + u32 nr =3D CTI_REG_GET_NR(reg); + + return drvdata->base + offset + sizeof(u32) * nr; +} + /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { @@ -55,16 +63,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) =20 /* write the CTI trigger registers */ for (i =3D 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], + cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i))); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i))); } =20 /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); + writel_relaxed(config->ctigate, cti_reg_addr(drvdata, CTIGATE)); if (config->asicctl_impl) - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->asicctl, cti_reg_addr(drvdata, ASICCTL)); + writel_relaxed(config->ctiappset, cti_reg_addr(drvdata, CTIAPPSET)); =20 /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -127,7 +136,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, in= t offset) int val; =20 CS_UNLOCK(drvdata->base); - val =3D readl_relaxed(drvdata->base + offset); + val =3D readl_relaxed(cti_reg_addr(drvdata, offset)); CS_LOCK(drvdata->base); =20 return val; @@ -136,7 +145,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, in= t offset) void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue) { CS_UNLOCK(drvdata->base); - writel_relaxed(value, drvdata->base + offset); + writel_relaxed(value, cti_reg_addr(drvdata, offset)); CS_LOCK(drvdata->base); } =20 @@ -342,8 +351,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* update the local register values */ chan_bitmask =3D BIT(channel_idx); - reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN : CTIOUTEN); =20 guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 @@ -363,8 +371,9 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); - + cti_write_single_reg(drvdata, + CTI_REG_SET_NR(reg_offset, trigger_idx), + reg_value); return 0; } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 88f8a08ef778..075f633ea9e1 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -385,7 +385,7 @@ static ssize_t inen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIINEN, index), val); =20 return size; } @@ -426,7 +426,7 @@ static ssize_t outen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIOUTEN, index), val); =20 return size; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index ef079fc18b72..21bcdedcb95f 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -30,8 +30,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTIINEN 0x020 +#define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -57,7 +57,18 @@ struct fwnode_handle; * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ -#define CTIINOUTEN_MAX 32 +#define CTIINOUTEN_MAX 128 + +/* + * Encode CTI register offset and register index in one u32: + * - bits[0:11] : base register offset (0x000 to 0xFFF) + * - bits[24:31] : register index (nr) + */ +#define CTI_REG_NR_MASK GENMASK(31, 24) +#define CTI_REG_GET_NR(reg) FIELD_GET(CTI_REG_NR_MASK, (reg)) +#define CTI_REG_SET_NR_CONST(reg, nr) ((reg) | FIELD_PREP_CONST(CTI_REG_NR= _MASK, (nr))) +#define CTI_REG_SET_NR(reg, nr) ((reg) | FIELD_PREP(CTI_REG_NR_MASK, (nr)= )) +#define CTI_REG_CLR_NR(reg) ((reg) & (~CTI_REG_NR_MASK)) =20 /** * Group of related trigger signals --=20 2.43.0 From nobody Fri Apr 3 03:00:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97552314D07 for ; Wed, 25 Mar 2026 05:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417453; cv=none; b=B8sQmg+7QTU+LWV+8sdk4x88M6Ids/b8rS/2bcRTMRKV6d+34XdR1oHJ8hknU7mB+mJJIvz3eDEZCCbvCCfypEKgm6oonksu9/H9xxeibyqI0Vp2iDBDrwDThGWn3Ja8l5YXlu5y7Rd9EHzg+5rb6yPyacLdiIN/+oEHXzm6PMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417453; c=relaxed/simple; bh=tsL6V64wIF8Vfwl80JY3mqBfH+J4HRNO08L5h5sdEfE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pmZ4g1rohN4AGP8glQqFC0LWqzadzfZgyMcilbx6pdw1XWGX0ePmh5w2/Ecuxsxp0hKSSzFuTMC6cKBGZHd6g1uIfeqLyaG9e0QWu1aljPT0yiL0yblE4H95847iQvMnQwsZzyoeLPknihLxyvUjBklVuePFdJLXU15/D5sFEKs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NiZGZjY3; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=I4G2iMKJ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NiZGZjY3"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="I4G2iMKJ" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62P4qwBh989024 for ; Wed, 25 Mar 2026 05:44:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= JQzcZFRQRIe3UKXb4FlRrFEi/jWZoZmnUtf/AMN/Ogw=; b=NiZGZjY3SFMHnPFt X0WQNpSEZD9A6EaXQ+f5Snw3WZSTbTjt4qJQDM9us1cuNp83RTnmPrDiMJ2K5c0n 50Q/vNdr+jOo6JXeWGA6YswxpEFgCAK3dslJjzBVVE2NQgAa/9+DHTv1/9vsMMiE VQlNW/5sm9tq/szqsa68u7JE9jhQtSBrsaAYglrrVMVnemtTdzviRssY8RViFzyZ TFufeOBJNVVRK5aKBtLTjbt2BgxpQiIoHd2uD1IXvN9hOWBYU9KklyTKHvwbidnl 433DnG6XuC945cf1aErJXIdKjJUNOvyXYV8xw/AWD8Btw/Errc310h94wpedF0ji 7m1GZg== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d3u0m38tn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Mar 2026 05:44:09 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2b0565d77a6so30077095ad.2 for ; Tue, 24 Mar 2026 22:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774417449; x=1775022249; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JQzcZFRQRIe3UKXb4FlRrFEi/jWZoZmnUtf/AMN/Ogw=; b=I4G2iMKJPrTSUK3KQyto5rL3c3WHlS2qYNpywFfUaiBQh+pUWugar3nWQmWf7dVko6 6pgsfULtl+f9QmNf0B+sDoLeUnhUl7H7ClpUT11QDjgfr+dd6pGJFdBbMUfctwBugss7 Owk7W88BLajuyTiC8OqcN/BzTfseJwIREm/V8bqDcgRmW/Tmgy2rPP8EyWTGOf1Zs3Rb FLVtetDutS48t7gdKp36wTJ0WFO3j7fTo0TkjlKpwhzzWB8jent+wi7QsUswnR6cxIcD hy1GHrHs4bkHfDKvDk+hft4QPimgf7/zL0TVfmIpIOcybubv62rglHkTjEVm4sYPjlWT 9Oiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774417449; x=1775022249; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=JQzcZFRQRIe3UKXb4FlRrFEi/jWZoZmnUtf/AMN/Ogw=; b=r5n1TsjZN1loIXSLTOzDtEmfZ+d+6JwYdTawoXGTuv62PCAmIhfjVzHBv5scAKnllt jqYakN3LPsqXQtXO/bRYdegI8onqKl02et7UUGAXp+SB9GXfp7X+HFln5gePrC4SgWsL XjEQSJGaizVNhLtgxWKuthB+47ZlVPN7klaId4BR611FNgYqaI4S2JoK1AFsln8EIp7y 26+aqidkFVZJLRwmQgibIi33xlUJraHHvYy2AnSGAF43SPv3AEa2FBZsM5ALovlBXT+t TiOQ3v7uktOjQMTCZVA9GxbfBGqJdo4CykdCrFQzgRPUfggUZ0DT7nCeZwt9D9thNTqf j10Q== X-Forwarded-Encrypted: i=1; AJvYcCUQJt2pYDUhRyDjd33bKRN7VeJeDSCf+n8Rl4FvxEwvTGXwLplDvPq9GvQz4ioTHlmufUU5GP9EmQwEgks=@vger.kernel.org X-Gm-Message-State: AOJu0YxAtSfiVIHHgiCwcxPT0hHN9dSYg0IQfK7WDFLcWpulbiDqeZPu LhbepyQNGwLxrpodrUeSQHZ11/PBJtUHb/txxKrKtXnXuTGRT80/IrQthL9e3cAFkSMkSpbBZK1 XhlgVNcfUSPY+1mQS5EZM2BsniABBNHCSfAMTVlWpJJFSVQVkZJKo8d04aw6yJWJ/55wQvfNcli Q= X-Gm-Gg: ATEYQzyWk+QxjUaRUaRb4U4L57ZrvQcZhB9jmMX3FUnmIExYnuy6Ga5C6ochBRLfxCh X/x9mhQXVVN+//SdaevCCycq/ViXrzDsjnC6d7Zh4qNsod3MdMPmKaA+YD3+H4F4C59cBuFy+Ik /G8tjMuDPUcX6ZdHPEOr61YXVp51biExu3i4VWTn4OfV+MvnHovVTCqJAjueOBZ5vL7O+fsYWkT ma44IQMxIbTXgWxH0Y6nVRnoAjLSo6Lm2ltjcC/0/1Hljadwl0dhDOBz1rG/TR8oA7z4rA6aSID A6fX+JxLSmj8scfLjBPFUFE1ckK1zDyMh50gpC1blPryJASrXj4B7vTjyh6Z/c42TFI9u7VL/aX YiTw54bt3+eTnu11sLkpx4f7VSU+WU5miAsjBxrtcpqvdL//56J8f1YaEb7bX/FqTqrAhoiNfKA 22k2BB0ws8dNcSEg== X-Received: by 2002:a17:902:d591:b0:2b0:4b3a:9b4b with SMTP id d9443c01a7336-2b0b09e8568mr25983995ad.16.1774417449097; Tue, 24 Mar 2026 22:44:09 -0700 (PDT) X-Received: by 2002:a17:902:d591:b0:2b0:4b3a:9b4b with SMTP id d9443c01a7336-2b0b09e8568mr25983705ad.16.1774417448521; Tue, 24 Mar 2026 22:44:08 -0700 (PDT) Received: from jinlmao-gv.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0836556f6sm219985805ad.49.2026.03.24.22.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 22:44:08 -0700 (PDT) From: Yingchao Deng Date: Wed, 25 Mar 2026 13:43:46 +0800 Subject: [PATCH v7 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-extended_cti-v7-3-bb406005089f@oss.qualcomm.com> References: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> In-Reply-To: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jinlong Mao , Tingwei Zhang , Jie Gan , quic_yingdeng@quicinc.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774417433; l=6755; i=yingchao.deng@oss.qualcomm.com; s=20260324; h=from:subject:message-id; bh=tsL6V64wIF8Vfwl80JY3mqBfH+J4HRNO08L5h5sdEfE=; b=tx726oeyFvbCnTOQp3JfZzxjdXfeYZd1ALE7Mk5SBqWKrsk0fUv3xrS++jS3n/gLw8+YysSCU JbRLrJG20QuB580j1reWygEgD3vvB5fL+BsqdvMYSRq4aqPN0KgahME X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=5tp504LR96W2IVT3sAbRCqWtoG16CxJVUnXJSfU8NlQ= X-Authority-Analysis: v=2.4 cv=IY6KmGqa c=1 sm=1 tr=0 ts=69c37629 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=7a10iwBbuTRWBBlgjiMA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: 9D5IaK8oYtQcSe8y6nNOFkbv-QDTC_6Z X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDAzOCBTYWx0ZWRfX3RnYlIUzXCnM Zk6hevFbJvL3jOd+Uy4Mss1AdcA/Rdefuurfth9a706/QT2lwJLxjLmJbzTdpTxaJQxarZ76W73 R98FbTExlbDOPtSkhO7vvZ+lLjrECHvoADCPNfwH1ZdzdYMvqVEIoqaaXWFkqC5n8rv1vbb7sci 8eygVB0fwPkqSycVJrSeNtipUVzNucyv18EXvdgixb02SIRqmpuBF6k2uWQRgg4mvXynC48qdKa VMHoOHQ/J445NE5qNtR0nRk7KVOWlehEPxd397/4yiOwGbDpAJxQS2lWlYxLcxPUbzdt/PlDigE /kmN8D9YsBXiBs3RIeo+b/5WPzdCaAfevsEhg2TP+p090dffQMbD1jzPyvWvdeda48tv6sHVNGm D8QSyucJ/bTNxFWGP8DziVdtMPx/jD0zM8uvDQl6Gdxz/cZnLrztvItenF89iK7wuLbSkI4yNkt c5x1OWpVlSsKmEw9B+Q== X-Proofpoint-GUID: 9D5IaK8oYtQcSe8y6nNOFkbv-QDTC_6Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_02,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 suspectscore=0 adultscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250038 Qualcomm implements an extended variant of the ARM CoreSight CTI with a different register layout and vendor-specific behavior. While the programming model remains largely compatible, the register offsets differ from the standard ARM CTI and require explicit handling. Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI driver data. Introduce a small mapping layer to translate standard CTI register offsets to Qualcomm-specific offsets, allowing the rest of the driver to use a common register access path. Additionally, handle a Qualcomm-specific quirk where the CLAIMSET register is incorrectly initialized to a non-zero value, which can cause tools or drivers to assume the component is already claimed. Clear the register during probe to reflect the actual unclaimed state. No functional change is intended for standard ARM CTI devices. Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 26 +++++++++- drivers/hwtracing/coresight/coresight-cti.h | 1 + drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++++++++++= ++++ 3 files changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 023993475a2e..afa83d411a4a 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -21,6 +21,7 @@ =20 #include "coresight-priv.h" #include "coresight-cti.h" +#include "qcom-cti.h" =20 /* * CTI devices can be associated with a PE, or be connected to CoreSight @@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *dr= vdata, u32 reg) u32 offset =3D CTI_REG_CLR_NR(reg); u32 nr =3D CTI_REG_GET_NR(reg); =20 + /* convert to qcom specific offset */ + if (unlikely(drvdata->is_qcom_cti)) + offset =3D cti_qcom_reg_off(offset); + return drvdata->base + offset + sizeof(u32) * nr; } =20 @@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 +/* DEVARCH[31:21] - ARCHITECT */ +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31= )) + static int cti_set_default_config(struct device *dev, struct cti_drvdata *drvdata) { @@ -698,6 +706,7 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) struct coresight_desc cti_desc; struct coresight_platform_data *pdata =3D NULL; struct resource *res =3D &adev->res; + u32 devarch; =20 /* driver data*/ drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -722,6 +731,20 @@ static int cti_probe(struct amba_device *adev, const s= truct amba_id *id) =20 raw_spin_lock_init(&drvdata->spinlock); =20 + devarch =3D readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); + if (CTI_DEVARCH_ARCHITECT(devarch) =3D=3D ARCHITECT_QCOM) { + drvdata->is_qcom_cti =3D true; + /* + * QCOM CTI does not implement Claimtag functionality as + * per CoreSight specification, but its CLAIMSET register + * is incorrectly initialized to 0xF. This can mislead + * tools or drivers into thinking the component is claimed. + * + * Reset CLAIMSET to 0 to reflect that no claims are active. + */ + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); + } + /* initialise CTI driver config values */ ret =3D cti_set_default_config(dev, drvdata); if (ret) @@ -778,7 +801,8 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); + dev_info(&drvdata->csdev->dev, + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); return 0; } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 21bcdedcb95f..9c0896b17c24 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -187,6 +187,7 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; + bool is_qcom_cti; }; =20 /* diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/cor= esight/qcom-cti.h new file mode 100644 index 000000000000..21a33b759b36 --- /dev/null +++ b/drivers/hwtracing/coresight/qcom-cti.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _CORESIGHT_QCOM_CTI_H +#define _CORESIGHT_QCOM_CTI_H + +#include "coresight-cti.h" + +#define ARCHITECT_QCOM 0x477 + +/* CTI programming registers */ +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08c +/* Integration test registers */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 + +static noinline u32 cti_qcom_reg_off(u32 offset) +{ + switch (offset) { + case CTIINTACK: return QCOM_CTIINTACK; + case CTIAPPSET: return QCOM_CTIAPPSET; + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; + case CTIINEN: return QCOM_CTIINEN; + case CTIOUTEN: return QCOM_CTIOUTEN; + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; + case CTIGATE: return QCOM_CTIGATE; + case ASICCTL: return QCOM_ASICCTL; + case ITCHINACK: return QCOM_ITCHINACK; + case ITTRIGINACK: return QCOM_ITTRIGINACK; + case ITCHOUT: return QCOM_ITCHOUT; + case ITTRIGOUT: return QCOM_ITTRIGOUT; + case ITCHOUTACK: return QCOM_ITCHOUTACK; + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; + case ITCHIN: return QCOM_ITCHIN; + case ITTRIGIN: return QCOM_ITTRIGIN; + + default: + return offset; + } +} + +#endif /* _CORESIGHT_QCOM_CTI_H */ --=20 2.43.0 From nobody Fri Apr 3 03:00:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 641D0311C2F for ; Wed, 25 Mar 2026 05:44:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417455; cv=none; b=OxaZIhUvnMAjLU2VbbhJ1F7+TcKvfImJo0qVWfXWmO3hJ4y/JjXOzlrY3T4rS7oOAeJNvz9KXYci0NBhZhQDqVvak3o/enQcFC/PXpFkVgc9IGQPARGQY6XzoapIUy6TRn7DXq9Up8jL5Xnz0pMy5gKgYoPNdyhVXBhp6jH/m0A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774417455; c=relaxed/simple; bh=8tA/1rrhluQQOhAaaei29rn2Ss2/RThN58fxl9hPMJs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SghDHt9VhZVOjYYqO4i39B01tMKRumEiBOIbESvc70iUboMOCpyfzXtGrYO0xUiTNiPkItv4q8G60beBCMDhu6cbM6abeu84DRRGlEGmAg97+/BmNYvJ/vAjsfDDU+qNKRUE7B3OLDwj2CdXmAhT7eQCfydTzU7ZzxD7A9vykHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VJw8Mhh+; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=LU5va6c0; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VJw8Mhh+"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="LU5va6c0" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62P5NJlr2075638 for ; Wed, 25 Mar 2026 05:44:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= sAedjumssGP8HnleB4ucvI59aev90SYKLdAP8s7agLk=; b=VJw8Mhh+jSJxkCAh LyLamUjsD8eHWm6v3vFbKQU/sWUjwQXPpuf/99WJTdRfcC3oZaF2n4hS3C0UgGf3 ATiCZbAQcjFZV11hm7XjAHJ/lw21IoBoNk2+z1Gmfnq0LnrnyHKvn6Q17wUm8T1M PlNDOMgBuKTomM2iwEyqn39fAd8unaXfFDtIOAe63AHCl8YXyPDcFxZMpjGSO7q/ VYLYJgGoxO/HMNqna1mnZHvO9j5oGNiGlP8KiYQ8BI0xnKFrnYmwFDg9BifoejYM TVrEKBfw+YDsjdb5fT+ru+t7/HhwkVTtSWqNaHGaoeNZHJYyQrqpLceSN9kn1T6B v9wEdQ== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d41411mva-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 25 Mar 2026 05:44:13 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2b0560c1320so138022145ad.2 for ; Tue, 24 Mar 2026 22:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774417453; x=1775022253; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sAedjumssGP8HnleB4ucvI59aev90SYKLdAP8s7agLk=; b=LU5va6c0ikkjQbZnWgWBzl+GBLp20vCl4sBK80IKtkjidMk9yY62U8uUruGNeuXfhx xyiwobl7Xz9DvJixwPq4tX7cYQvSBc3wyIMELsz/2jVruipgouNVM1luGWHmrWZDcchf Zhy5qO9seH/zAjTBc6VpYoWgluAr9ZLlXjbPU3SDGFaWZFL4wnzsa5JGheT3A2FIEJHg h96JwRxFiGfH3aMrTZi/iZdPxaFZdFi3ikOqu+99tJZ4ZqhzuNHbxA0x9u9XeNy99Tr4 faRPdkZMz5IKxDDTb555NCQ4N6V/bJ8eny+8ZAuL7yU9Endc6uxB+C/SPdgkoKWbzTFt 6nPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774417453; x=1775022253; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=sAedjumssGP8HnleB4ucvI59aev90SYKLdAP8s7agLk=; b=OMMoumnJ6Jrhh2UxLH7Rr8mtnICaJnq9ZQNrNbFlG2uesSMTYMbQb6BWdtqTpg7QsY OQM4VwDSI8X10RKgrD8rPYPj3Artq5o0PvkXWvsCYtUUVtv/+L4ETMegVtR7vv1FWvaw ITm2KngU5G/yeErNsbrVhXfGs+Spp1JGaLoPNecTK+K6m416qTX9RNDnWM59cF8t99WU I2VbhQNvMkvSdjFgfdJt9TEcTgcGbur9TdtzHJFuHsNFUcWmEGdPzl3/j2lfjqzVsFk8 8t6Qr3jWTCXnsxjgky7y2EPFR/KQO4laC14x7qSwHXzalha524UUbeF4STpZsAn09fG3 ZL3Q== X-Forwarded-Encrypted: i=1; AJvYcCXqqceQ/bjEf7QGu/ep9hDE3WG9TYdLl2i2zY0Rfpj3VsR0UIXTEjgx/xRkoUqCjia9xmwbjNNr58Yp1zA=@vger.kernel.org X-Gm-Message-State: AOJu0YyOSlOld6VpyWIm6r/nB5acUCn1wNV217iyN0nU4s4arj6hMO6H PnhhH8VozmcKTVj6sjnKmLuw39fNPJfvAQQy4e22zC/bn/F2Ktm8U5F6hLtbDH6J8mtuJHtW5BL eSpwg3Cn7GMQMWC10zDjK2O/p4VJtD8vtdDtSD6UXgqn5+dPyEEQirl8ECryP3zr3jumBEHhArh A= X-Gm-Gg: ATEYQzwlVfiBdqdq8sfuYo/PcrVGsYNG3WWszWPNJCoj28fS8w4Dhhwr2mqF94tGkDz fUOHzPgt9gqCLdIS1pGPUJPdTBXvHjuj5piGKsUCyT5ofF5Pf/mnX9Kx/9z48cJCzLyhR4++//l 0nZrKaqlQBDLWbOqJxE5hKivyJNPOGnSoqPpDAyek7KtmDlxSiy0duzTMNrsCp3rB7fxTKvflOs UX5BeBXPM7kg2mDz7VKEy2mw5MGxhRKCsPLawK1E1OHF5Sd4MzF14rqdxeDPapRomUyTQJV+FYg RGeJuSuA+JlL6tfatTuTGOQg197/ObyyADYrcvLvbXq9EwyD/4RW1A8LlH2x4sCjlIjKrWMlzgf 9EZ0MMiEBoazN0e1LyBlrdQCGdaakWYHsGRBnrgwgXZQVEWvnoIm6kUcET9MLq/Ac0eDtRxCdO2 gCo885HNVy3HOg1w== X-Received: by 2002:a17:903:46cb:b0:2b0:4b37:e9a5 with SMTP id d9443c01a7336-2b0b0b2efd3mr24364835ad.53.1774417452674; Tue, 24 Mar 2026 22:44:12 -0700 (PDT) X-Received: by 2002:a17:903:46cb:b0:2b0:4b37:e9a5 with SMTP id d9443c01a7336-2b0b0b2efd3mr24364465ad.53.1774417452193; Tue, 24 Mar 2026 22:44:12 -0700 (PDT) Received: from jinlmao-gv.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0836556f6sm219985805ad.49.2026.03.24.22.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 22:44:11 -0700 (PDT) From: Yingchao Deng Date: Wed, 25 Mar 2026 13:43:47 +0800 Subject: [PATCH v7 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-extended_cti-v7-4-bb406005089f@oss.qualcomm.com> References: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> In-Reply-To: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jinlong Mao , Tingwei Zhang , Jie Gan , quic_yingdeng@quicinc.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774417433; l=4654; i=yingchao.deng@oss.qualcomm.com; s=20260324; h=from:subject:message-id; bh=8tA/1rrhluQQOhAaaei29rn2Ss2/RThN58fxl9hPMJs=; b=kPJ6va5jIdBC1luKdNocyudY3wzT2OYkTluHO1R/HtuMWrwpokb9DAG6Jv97cbz6jci6+Z6Ti 6OStKD1lfPDBsz4zmeoCXv8H7A1fqyT/sRvuwPlSrS8Bih4EWbKRC61 X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=5tp504LR96W2IVT3sAbRCqWtoG16CxJVUnXJSfU8NlQ= X-Authority-Analysis: v=2.4 cv=fOk0HJae c=1 sm=1 tr=0 ts=69c3762d cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=PrhcshflQRWEcWOJaRQA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: kL_I_1FHfWrBbuUQVsJFfiNruo7fOnoh X-Proofpoint-ORIG-GUID: kL_I_1FHfWrBbuUQVsJFfiNruo7fOnoh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDAzOCBTYWx0ZWRfX+RUajFeC1rVS rJ9meOZOsAvTITb4p7jeIbvJiE+QJC68ddSgw9ljYJ+G29XP9w2hJh6gOyRbJ792GuuxlQrW9Rt ZlJJHlFo4cB/hs7XrSOst/6lNkvVYNAe+SIjF2h6xixipebMw55puyBLjTtE32k8W9acEsvH4t4 dEb6gnZ3wJzLX9IM3cGhLRj9w8FJMFEVhWhn6hovpJ8UVkM5jJ+ZVAhOqUGoHRkDCC7CA/Ymbmo C1y6NYZoi4oSBQeI2s7kWxcylLSBgKnu3+529x2QMqbqkX64zLcG4Vo3IswuEJOEoaQje65dCSH 8cNgUi3302YJF6tMjeqnB+6ESZmPuu4BCuX45/3wlaf2G3dVI/OLxO9NxJ/G2AOKzgUhkwGn1rt FoSzg6OohnZueukohgB6qMMeXwfvBTMbBulu3wVP47mooALvgI9qNTKbDO5G8qAsi4pOzHWK4RR M/57Q2445ZeB2TZcdrg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_02,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250038 Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Numbered sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI. On Qualcomm CTIs, only banked registers backed by hardware are exposed, with the number of visible banks derived from nr_trig_max. This ensures that userspace only sees registers that are actually implemented, while maintaining compatibility with existing CTI tooling. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 075f633ea9e1..123ac862d8de 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -511,18 +511,36 @@ static struct attribute *coresight_cti_regs_attrs[] = =3D { &dev_attr_appclear.attr, &dev_attr_apppulse.attr, coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)= ), + coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)= ), + coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)= ), coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 1)), + coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 2)), + coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 3)), coresight_cti_reg(chinstatus, CTICHINSTATUS), coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)), + coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)), + coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)), coresight_cti_reg(itchin, ITCHIN), coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)), + coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)), + coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)), coresight_cti_reg_rw(itchout, ITCHOUT), coresight_cti_reg(itchoutack, ITCHOUTACK), coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)), + coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)), + coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)), coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)), + coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)), + coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)), coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, @@ -533,10 +551,50 @@ static umode_t coresight_cti_regs_is_visible(struct k= object *kobj, { struct device *dev =3D kobj_to_dev(kobj); struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const char * const qcom_suffix_registers[] =3D { + "triginstatus", + "trigoutstatus", +#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS + "ittrigin", + "ittrigout", + "ittriginack", + "ittrigoutack", +#endif + }; + int i, nr, max_bank; + size_t len; =20 if (attr =3D=3D &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) return 0; =20 + /* + * Banked regs are exposed as (nr =3D 1..3). + * - Hide them on standard CTIs. + * - On QCOM CTIs, hide suffixes beyond the number of banks implied + * by nr_trig_max (32 triggers per bank). + */ + for (i =3D 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) { + len =3D strlen(qcom_suffix_registers[i]); + + if (strncmp(attr->name, qcom_suffix_registers[i], len)) + continue; + + if (kstrtoint(attr->name + len, 10, &nr)) + continue; + + if (!drvdata->is_qcom_cti) + return 0; + + if (nr < 1 || nr > 3) + return 0; + + max_bank =3D DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1; + if (nr > max_bank) + return 0; + + break; + } + return attr->mode; } =20 --=20 2.43.0