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Now that nova-core's `register` macro doesn't exist anymore, we can import and use it directly without risk of name collision. Reviewed-by: Eliot Courtney Reviewed-by: Gary Guo Signed-off-by: Alexandre Courbot --- drivers/gpu/nova-core/regs.rs | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 87c2977ba6e4..2f171a4ff9ba 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -2,7 +2,7 @@ =20 use kernel::{ io::{ - self, + register, register::WithBase, Io, // }, @@ -35,7 +35,7 @@ =20 // PMC =20 -io::register! { +register! { /// Basic revision information about the GPU. pub(crate) NV_PMC_BOOT_0(u32) @ 0x00000000 { /// Lower bits of the architecture. @@ -106,7 +106,7 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> ke= rnel::fmt::Result { =20 // PBUS =20 -io::register! { +register! { pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} =20 /// Scratch register 0xe used as FRTS firmware error code. @@ -117,7 +117,7 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> ke= rnel::fmt::Result { =20 // PFB =20 -io::register! { +register! { /// Low bits of the physical system memory address used by the GPU to = perform sysmembar /// operations (see [`crate::fb::SysmemFlush`]). pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 { @@ -180,7 +180,7 @@ pub(crate) fn higher_bound(self) -> u64 { =20 // PGSP =20 -io::register! { +register! { pub(crate) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 { 31:0 address; } @@ -195,7 +195,7 @@ pub(crate) fn higher_bound(self) -> u64 { // These scratch registers remain powered on even in a low-power state and= have a designated group // number. =20 -io::register! { +register! { /// Boot Sequence Interface (BSI) register used to determine /// if GSP reload/resume has completed during the boot process. pub(crate) NV_PGC6_BSI_SECURE_SCRATCH_14(u32) @ 0x001180f8 { @@ -247,7 +247,7 @@ pub(crate) fn usable_fb_size(self) -> u64 { =20 // PDISP =20 -io::register! { +register! { pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { /// VGA workspace base address divided by 0x10000. 31:8 addr; @@ -271,7 +271,7 @@ pub(crate) fn vga_workspace_addr(self) -> Option { =20 pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize =3D 16; =20 -io::register! { +register! { pub(crate) NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_S= IZE] @ 0x00824100 { 15:0 data =3D> u16; } @@ -287,7 +287,7 @@ pub(crate) fn vga_workspace_addr(self) -> Option { =20 // PFALCON =20 -io::register! { +register! { pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 { 6:6 swgen0 =3D> bool; 4:4 halt =3D> bool; @@ -468,7 +468,7 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { =20 /* PFALCON2 */ =20 -io::register! { +register! { pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180= { 7:0 algo ?=3D> FalconModSelAlgo; } @@ -490,7 +490,7 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { =20 // PRISCV =20 -io::register! { +register! { /// RISC-V status register for debug (Turing and GA100 only). /// Reflects current RISC-V core status. pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Bas= e + 0x00000240 { @@ -516,11 +516,11 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { // only be used in HAL modules. =20 pub(crate) mod gm107 { - use kernel::io; + use kernel::io::register; =20 // FUSE =20 - io::register! { + register! { pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00021c04 { 0:0 display_disabled =3D> bool; } @@ -528,11 +528,11 @@ pub(crate) mod gm107 { } =20 pub(crate) mod ga100 { - use kernel::io; + use kernel::io::register; =20 // FUSE =20 - io::register! { + register! { pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00820c04 { 0:0 display_disabled =3D> bool; } --=20 2.53.0