From nobody Fri Apr 3 03:01:31 2026 Received: from courrier.aliel.fr (pouet.aliel.fr [65.21.61.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BAC2352C4E; Wed, 25 Mar 2026 09:18:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=65.21.61.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774430332; cv=none; b=fWJiDiPpjNVSp6pyIP9Qv5iorUiYRWCUy2A/WukqDtcKyZereBVIn3Efv374Qd5v/9Klu59fw5VhjAoKiUhdYGgKZj509RftJlmtxtw3uZsGfloZ7n8UVSnUlWqAJRp9mLEMEQa4i6h3r5znT9gKMclyGUgkm99wkZEFzdr8FZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774430332; c=relaxed/simple; bh=WZ2VWU8ZZjMvH1UNXGZZiw4ZemZ6mSet2kenghPyLf4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gT1RHWK+Sj4Z0Pp5FQf/EVyU2i561XfuL2Pp9+Lw8KFtgH5NIVaY2x+iO2GdT47gC2p4uU0TzURXV+oC9IPcR+DulIPfbGdammPz39WBgIKLGdzVu3SO1T1Z6OWYDLX900d++zE1oBFZ40rUkBc32x7oJN3vsQ7ccjrT7fsn0s4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=aliel.fr; spf=pass smtp.mailfrom=aliel.fr; dkim=pass (1024-bit key) header.d=aliel.fr header.i=@aliel.fr header.b=VGI/7v6S; arc=none smtp.client-ip=65.21.61.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=aliel.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aliel.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=aliel.fr header.i=@aliel.fr header.b="VGI/7v6S" From: Ronald Claveau DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aliel.fr; s=courrier-s1; t=1774430329; bh=WZ2VWU8ZZjMvH1UNXGZZiw4ZemZ6mSet2kenghPyLf4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=VGI/7v6S9Hp5hycjhI4RroFM6kUQRKcVK1DQks/Rqspe+jMfAqlRgvhBASsVFxq1M Z8kArI5/aIn3gzIKREvXyhuBR/EUuGtOk5A+sFXlH10OWc46jek4dFD0xrELqfaiDt hopK1ejgidDx2QVW1vVTI6JMGI9tf4DLnhw6jJ/4= Date: Wed, 25 Mar 2026 10:15:22 +0100 Subject: [PATCH v4 4/9] arm64: dts: amlogic: t7: Add PWM pinctrl nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260325-add-emmc-t7-vim4-v4-4-44c7b4a5e459@aliel.fr> References: <20260325-add-emmc-t7-vim4-v4-0-44c7b4a5e459@aliel.fr> In-Reply-To: <20260325-add-emmc-t7-vim4-v4-0-44c7b4a5e459@aliel.fr> To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Johannes Berg , van Spriel Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-wireless@vger.kernel.org, Ronald Claveau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openssh-sha256; t=1774430324; l=3146; i=linux-kernel-dev@aliel.fr; s=id_ed25519; h=from:subject:message-id; bh=WZ2VWU8ZZjMvH1UNXGZZiw4ZemZ6mSet2kenghPyLf4=; b=U1NIU0lHAAAAAQAAADMAAAALc3NoLWVkMjU1MTkAAAAgMGec55oxeeisqykQiUedekMYyOnR9 BG9E/7rDWyqdNoAAAAGcGF0YXR0AAAAAAAAAAZzaGE1MTIAAABTAAAAC3NzaC1lZDI1NTE5AAAA QAwFbBr3FjIvDay8rQ3kHJMHy2yIGRImTzSlbpZvuzYhFmM7E5MXFCZesofPIA331o6ZTxY/61W CXWUMnFQd5gA= X-Developer-Key: i=linux-kernel-dev@aliel.fr; a=openssh; fpr=SHA256:kch4osYZ6A1BrPps5AUs6KnfdE2wm4ocMtyTc8TmZMs These pinctrl nodes are required by the PWM drivers to configure pin muxing at runtime. Signed-off-by: Ronald Claveau Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 136 ++++++++++++++++++++++++= ++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index 62c87d0ef7065..eb09a26bcd0e0 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -307,6 +307,142 @@ mux { }; }; =20 + pwm_a_pins: pwm-a { + mux { + groups =3D "pwm_a"; + function =3D "pwm_a"; + bias-disable; + }; + }; + + pwm_ao_a_pins: pwm-ao-a { + mux { + groups =3D "pwm_ao_a"; + function =3D "pwm_ao_a"; + bias-disable; + }; + }; + + pwm_ao_b_pins: pwm-ao-b { + mux { + groups =3D "pwm_ao_b"; + function =3D "pwm_ao_b"; + bias-disable; + }; + }; + + pwm_ao_c_pins: pwm-ao-c { + mux { + groups =3D "pwm_ao_c"; + function =3D "pwm_ao_c"; + bias-disable; + }; + }; + + pwm_ao_c_hiz_pins: pwm-ao-c-hiz { + mux { + groups =3D "pwm_ao_c_hiz"; + function =3D "pwm_ao_c_hiz"; + bias-disable; + }; + }; + + pwm_ao_d_pins: pwm-ao-d { + mux { + groups =3D "pwm_ao_d"; + function =3D "pwm_ao_d"; + bias-disable; + }; + }; + + pwm_ao_e_pins: pwm-ao-e { + mux { + groups =3D "pwm_ao_e"; + function =3D "pwm_ao_e"; + bias-disable; + }; + }; + + pwm_ao_f_pins: pwm-ao-f { + mux { + groups =3D "pwm_ao_f"; + function =3D "pwm_ao_f"; + bias-disable; + }; + }; + + pwm_ao_g_pins: pwm-ao-g { + mux { + groups =3D "pwm_ao_g"; + function =3D "pwm_ao_g"; + bias-disable; + }; + }; + + pwm_ao_g_hiz_pins: pwm-ao-g-hiz { + mux { + groups =3D "pwm_ao_g_hiz"; + function =3D "pwm_ao_g_hiz"; + bias-disable; + }; + }; + + pwm_ao_h_pins: pwm-ao-h { + mux { + groups =3D "pwm_ao_h"; + function =3D "pwm_ao_h"; + bias-disable; + }; + }; + + pwm_b_pins: pwm-b { + mux { + groups =3D "pwm_b"; + function =3D "pwm_b"; + bias-disable; + }; + }; + + pwm_c_pins: pwm-c { + mux { + groups =3D "pwm_c"; + function =3D "pwm_c"; + bias-disable; + }; + }; + + pwm_d_pins: pwm-d { + mux { + groups =3D "pwm_d"; + function =3D "pwm_d"; + bias-disable; + }; + }; + + pwm_e_pins: pwm-e { + mux { + groups =3D "pwm_e"; + function =3D "pwm_e"; + bias-disable; + }; + }; + + pwm_f_pins: pwm-f { + mux { + groups =3D "pwm_f"; + function =3D "pwm_f"; + bias-disable; + }; + }; + + pwm_vs_pins: pwm-vs { + mux { + groups =3D "pwm_vs"; + function =3D "pwm_vs"; + bias-disable; + }; + }; + sdcard_pins: sdcard { mux { groups =3D "sdcard_d0", --=20 2.49.0