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charset="utf-8" From: Vidya Sagar The Root Port's CLKREQ# signal is shared with a downstream PCIe switch and the endpoints behind it. By default, APPL_PINMUX_CLKREQ_OVERRIDE only overrides the CLKREQ# input to the controller (so REFCLK is enabled internally); it does not drive the CLKREQ# output pin low. Some PCIe switches (e.g. Broadcom PCIe Gen4) forward the Root Port's CLKREQ# to their downstream side and expect it to be driven low for REFCLK, even when the switch does not support CLK-PM or ASPM-L1SS. Without driving the output pin low, link-up can fail between the switch and endpoints. Clear APPL_PINMUX_CLKREQ_DEFAULT_VALUE so the CLKREQ# output pad is explicitly driven low. That makes the shared CLKREQ# line low on the wire and avoids link-up issues with such switches. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V6 -> V8: Fix commit message Changes V1 -> V6: None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index b497b178bb7e..c823285368f5 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -44,6 +44,7 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE BIT(13) =20 #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1428,6 +1429,7 @@ static int tegra_pcie_config_controller(struct tegra_= pcie_dw *pcie, val =3D appl_readl(pcie, APPL_PINMUX); val |=3D APPL_PINMUX_CLKREQ_OVERRIDE_EN; val &=3D ~APPL_PINMUX_CLKREQ_OVERRIDE; + val &=3D ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE; 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charset="utf-8" From: Vidya Sagar Calibrate 'pipe to universal PHY(UPHY)' (P2U) for the Endpoint controller to request UPHY PLL rate change to Gen1 during initialization. This helps to reset stale PLL state from the previous bad link state. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes v8: Fix commit message Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index c823285368f5..37fcac55838f 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1071,6 +1071,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw= *pcie) ret =3D phy_power_on(pcie->phys[i]); if (ret < 0) goto phy_exit; + + if (pcie->of_data->mode =3D=3D DW_PCIE_EP_TYPE) + phy_calibrate(pcie->phys[i]); } =20 return 0; --=20 2.34.1 From nobody Thu Apr 2 13:15:31 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011000.outbound.protection.outlook.com [52.101.62.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8459B3B6BF9; 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charset="utf-8" From: Vidya Sagar The Tegra PCIe Endpoint controller has a single interrupt line that is shared between multiple interrupt sources: 1. PCIe link state events (link up, hot reset done) 2. Configuration space events (Bus Master Enable changes) 3. DMA completion events The interrupt is currently registered with IRQF_ONESHOT, which keeps the interrupt line masked until the threaded handler completes. That blocks processing of DMA completion events (and other sources) while the threaded handler runs. Removing IRQF_ONESHOT is safe for the following reasons: 1. The hard IRQ handler (tegra_pcie_ep_hard_irq) properly acknowledges and clears all interrupt status bits in hardware before returning. This prevents interrupt storms and ensures the interrupt controller can re-enable the interrupt line immediately. 2. A follow-up patch adds handling in the hard IRQ for DMA completion events. Dropping IRQF_ONESHOT is required so the line is unmasked after the hard IRQ returns and those events can be serviced without being blocked by the threaded handler. 3. The threaded handler (tegra_pcie_ep_irq_thread) only processes link-up notifications and LTR message sending. These operations don't conflict with DMA interrupt processing and don't require the interrupt line to remain masked. This change enables both DMA driver and Endpoint controller driver to share the interrupt line without blocking each other. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Fix commit message Changes V6 -> V7: None Changes V1 -> V6: Updated commit message drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 37fcac55838f..63173f7af62b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2243,7 +2243,7 @@ static int tegra_pcie_dw_probe(struct platform_device= *pdev) ret =3D devm_request_threaded_irq(dev, pp->irq, tegra_pcie_ep_hard_irq, tegra_pcie_ep_irq_thread, - IRQF_SHARED | IRQF_ONESHOT, + IRQF_SHARED, "tegra-pcie-ep-intr", pcie); if (ret) { dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, --=20 2.34.1 From nobody Thu Apr 2 13:15:31 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013040.outbound.protection.outlook.com [40.107.201.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45AED3CA483; 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charset="utf-8" From: Vidya Sagar Enable DMA interrupt to support Tegra PCIe DMA in both Root Port and Endpoint modes. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V8: None drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 63173f7af62b..b312d02f8dab 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -91,6 +91,7 @@ #define APPL_INTR_EN_L1_8_0 0x44 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) +#define APPL_INTR_EN_L1_8_EDMA_INT_EN BIT(6) #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) =20 @@ -544,6 +545,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, voi= d *arg) spurious =3D 0; } =20 + if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) { + status_l1 =3D appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); + /* Interrupt is handled by dma driver, don't treat it as spurious */ + if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) + spurious =3D 0; + } + if (spurious) { dev_warn(pcie->dev, "Random interrupt (STATUS =3D 0x%08X)\n", status_l0); @@ -779,6 +787,7 @@ static void tegra_pcie_enable_intx_interrupts(struct dw= _pcie_rp *pp) val |=3D APPL_INTR_EN_L1_8_INTX_EN; val |=3D APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; val |=3D APPL_INTR_EN_L1_8_BW_MGT_INT_EN; + val |=3D APPL_INTR_EN_L1_8_EDMA_INT_EN; if (IS_ENABLED(CONFIG_PCIEAER)) val |=3D APPL_INTR_EN_L1_8_AER_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); @@ -1805,6 +1814,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegr= a_pcie_dw *pcie) val |=3D APPL_INTR_EN_L0_0_SYS_INTR_EN; val |=3D APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; val |=3D APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; + val |=3D APPL_INTR_EN_L0_0_INT_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L0_0); =20 val =3D appl_readl(pcie, APPL_INTR_EN_L1_0_0); @@ -1812,6 +1822,10 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) val |=3D APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); 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charset="utf-8" From: Vidya Sagar When PCIe link goes down, hardware can retrain the link and try to link up. To enable this feature, program the APPL_CTRL register with hardware hot reset with immediate LTSSM enable mode. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V8: None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index b312d02f8dab..4527d4759e42 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1791,6 +1791,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegr= a_pcie_dw *pcie) val =3D appl_readl(pcie, APPL_CTRL); val |=3D APPL_CTRL_SYS_PRE_DET_STATE; val |=3D APPL_CTRL_HW_HOT_RST_EN; + val &=3D ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SH= IFT); + val |=3D (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT= _RST_MODE_SHIFT); appl_writel(pcie, val, APPL_CTRL); =20 val =3D appl_readl(pcie, APPL_CFG_MISC); --=20 2.34.1 From nobody Thu Apr 2 13:15:31 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011025.outbound.protection.outlook.com [40.107.208.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 357D13CEBB5; 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charset="utf-8" From: Vidya Sagar Tegra supports PCIe core clock monitoring for any rate changes that may be happening because of the link speed changes. This is useful in tracking any changes in the core clock that are not initiated by the software. Reviewed-by: Rob Herring (Arm) Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V5 -> V8: None Changes V4 -> V5: Fixed clock description per review comment Changes V1 -> V4: None .../devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml | 6 +++++- .../devicetree/bindings/pci/nvidia,tegra194-pcie.yaml | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.= yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml index 6d6052a2748f..7805757f2e2d 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml @@ -55,12 +55,16 @@ properties: - const: intr =20 clocks: + minItems: 1 items: - - description: module clock + - description: core clock + - description: monitor clock =20 clock-names: + minItems: 1 items: - const: core + - const: core_m =20 resets: items: diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yam= l b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml index fe81d52c7277..41041ae7e0a4 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml @@ -58,12 +58,16 @@ properties: - const: msi =20 clocks: + minItems: 1 items: - - description: module clock + - description: core clock + - description: monitor clock =20 clock-names: + minItems: 1 items: - const: core + - const: core_m =20 resets: items: --=20 2.34.1 From nobody Thu Apr 2 13:15:31 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012000.outbound.protection.outlook.com [40.93.195.0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA28D3CF691; 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charset="utf-8" From: Vidya Sagar Add support for Tegra PCIe core clock monitoring. Monitoring tracks rate changes that may occur due to link speed changes and is useful for detecting core clock changes not initiated by software. Parse the monitor clock from device tree and enable it when present. Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Fix commit message Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-tegra194.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 4527d4759e42..3278353b2c29 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -249,6 +249,7 @@ struct tegra_pcie_dw { struct resource *atu_dma_res; void __iomem *appl_base; struct clk *core_clk; + struct clk *core_clk_m; struct reset_control *core_apb_rst; struct reset_control *core_rst; struct dw_pcie pci; @@ -945,6 +946,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) } =20 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); + if (clk_prepare_enable(pcie->core_clk_m)) + dev_err(pci->dev, "Failed to enable core monitor clock\n"); =20 return 0; } @@ -1017,6 +1020,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *= pci) val &=3D ~PCI_DLF_EXCHANGE_ENABLE; dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val); =20 + /* + * core_clk_m is enabled as part of host_init callback in + * dw_pcie_host_init(). Disable the clock since below + * tegra_pcie_dw_host_init() will enable it again. + */ + clk_disable_unprepare(pcie->core_clk_m); tegra_pcie_dw_host_init(pp); dw_pcie_setup_rc(pp); =20 @@ -1610,6 +1619,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pc= ie_dw *pcie) =20 static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { + clk_disable_unprepare(pcie->core_clk_m); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2160,6 +2170,11 @@ static int tegra_pcie_dw_probe(struct platform_devic= e *pdev) return PTR_ERR(pcie->core_clk); } =20 + pcie->core_clk_m =3D devm_clk_get_optional(dev, "core_m"); + if (IS_ERR(pcie->core_clk_m)) + return dev_err_probe(dev, PTR_ERR(pcie->core_clk_m), + "Failed to get monitor clock\n"); + pcie->appl_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "appl"); if (!pcie->appl_res) { @@ -2356,6 +2371,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device = *dev) if (!pcie->link_state) return 0; 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charset="utf-8" Add the aspm-l1-entry-delay-ns device tree property to all PCIe Root Port and PCIe Endpoint nodes in tegra194.dtsi and tegra234.dtsi so that ASPM L1 entrance latency is configured from device tree. - Tegra194: 4000 ns (4 us) for both Root Port and Endpoint. - Tegra234: 8000 ns (8 us) for Root Port, 16000 ns (16 us) for Endpoint. Signed-off-by: Manikanta Maddireddy --- V8: New patch arch/arm64/boot/dts/nvidia/tegra194.dtsi | 9 +++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index 849694f751d9..1d659454a6f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2382,6 +2382,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -2434,6 +2435,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -2486,6 +2488,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -2538,6 +2541,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -2583,6 +2587,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 interconnects =3D <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; @@ -2629,6 +2634,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -2674,6 +2680,7 @@ pcie-ep@14180000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 interconnects =3D <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; @@ -2723,6 +2730,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -2771,6 +2779,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <4000>; =20 interconnects =3D <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 850c473235e3..850c1a645d71 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4532,6 +4532,7 @@ pcie@140a0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -4586,6 +4587,7 @@ pcie@140c0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -4640,6 +4642,7 @@ pcie@140e0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -4686,6 +4689,7 @@ pcie-ep@140e0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <16000>; =20 interconnects =3D <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; @@ -4734,6 +4738,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -4788,6 +4793,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -4842,6 +4848,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -4896,6 +4903,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -4937,6 +4945,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <16000>; =20 interconnects =3D <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; @@ -4983,6 +4992,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -5037,6 +5047,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -5083,6 +5094,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <16000>; =20 interconnects =3D <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; @@ -5131,6 +5143,7 @@ pcie@141c0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <8000>; =20 bus-range =3D <0x0 0xff>; =20 @@ -5177,6 +5190,7 @@ pcie-ep@141c0000 { nvidia,aspm-cmrt-us =3D <60>; nvidia,aspm-pwr-on-t-us =3D <20>; nvidia,aspm-l0s-entrance-latency-us =3D <3>; + aspm-l1-entry-delay-ns =3D <16000>; =20 interconnects =3D <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 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charset="utf-8" Program ASPM L1 entrance latency from the optional aspm-l1-entry-delay-ns device tree property instead of of_data. Convert the value from nanoseconds to the hardware encoding (log2(us) + 1, 3-bit field). If the property is absent, default to 7 (maximum latency). Signed-off-by: Manikanta Maddireddy --- Changes V8: Use aspm-l1-entry-delay-ns instead of of_data Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 3278353b2c29..a856a48362df 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -272,6 +273,7 @@ struct tegra_pcie_dw { u32 aspm_cmrt; u32 aspm_pwr_on_t; u32 aspm_l0s_enter_lat; + u32 aspm_l1_enter_lat; =20 struct regulator *pex_ctl_supply; struct regulator *slot_ctl_3v3; @@ -710,6 +712,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); val &=3D ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; val |=3D (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); + val &=3D ~PORT_AFR_L1_ENTRANCE_LAT_MASK; + val |=3D (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT); val |=3D PORT_AFR_ENTER_ASPM; dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); } @@ -1110,6 +1114,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_d= w *pcie) { struct platform_device *pdev =3D to_platform_device(pcie->dev); struct device_node *np =3D pcie->dev->of_node; + u32 val; int ret; =20 pcie->dbi_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi= "); @@ -1136,6 +1141,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_= dw *pcie) dev_info(pcie->dev, "Failed to read ASPM L0s Entrance latency: %d\n", ret); =20 + /* Default to max latency of 7. */ + pcie->aspm_l1_enter_lat =3D 7; + ret =3D of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val); + if (!ret) { + u32 us =3D max(val / 1000, 1U); + + pcie->aspm_l1_enter_lat =3D min(ilog2(us) + 1, 7U); + } + ret =3D of_property_read_u32(np, "num-lanes", &pcie->num_lanes); if (ret < 0) { dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); --=20 2.34.1