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charset="utf-8" From: Vidya Sagar As per PCIe spec r7.0, sec 5.3.3.2.1, after sending PME_Turn_Off message, Root Port should wait for 1~10 msec for PME_TO_Ack message. Currently, driver is polling for 10 msec with 1 usec delay which is aggressive. Use existing macro PCIE_PME_TO_L2_TIMEOUT_US to poll for 10 msec with 1 msec delay. Since this function is used in non-atomic context only, use non-atomic poll function. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: None Changes V6 -> V7: Use PCIE_PME_TO_L2_TIMEOUT_US instead PME_ACK_TIMEOUT Changes V1 -> V6: None drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 0ddeef70726d..d6c6bd512b51 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -198,8 +198,6 @@ #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 =20 -#define PME_ACK_TIMEOUT 10000 - #define LTSSM_TIMEOUT 50000 /* 50ms */ =20 #define GEN3_GEN4_EQ_PRESET_INIT 5 @@ -1553,9 +1551,10 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_= dw *pcie) val |=3D APPL_PM_XMT_TURNOFF_STATE; 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charset="utf-8" On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock -> Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock and Recovery.RcvrSpeed transit times are 24 ms and 48 ms respectively, so the total time from L0 to detect is ~96 ms. Increase the poll timeout to 120 ms to account for this. Add LTSSM state defines for detect-related states and use them in the poll condition. Use readl_poll_timeout() instead of readl_poll_timeout_atom= ic() in tegra_pcie_dw_pme_turnoff() since that path runs in non-atomic context. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Split into two patches Changes V6 -> V7: Append _US to LTSSM macros Changes V5 -> V6: Retain only one fixes tag Changes V1 -> V5: None drivers/pci/controller/dwc/pcie-tegra194.c | 36 +++++++++++++--------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index d6c6bd512b51..5b243c006562 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -137,7 +137,11 @@ #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 -#define LTSSM_STATE_PRE_DETECT 5 +#define LTSSM_STATE_DETECT_QUIET 0x00 +#define LTSSM_STATE_DETECT_ACT 0x08 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x28 +#define LTSSM_STATE_DETECT_WAIT 0x30 +#define LTSSM_STATE_L2_IDLE 0xa8 =20 #define APPL_RADM_STATUS 0xE4 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) @@ -198,7 +202,8 @@ #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 =20 -#define LTSSM_TIMEOUT 50000 /* 50ms */ +#define LTSSM_DELAY_US 10000 /* 10 ms */ +#define LTSSM_TIMEOUT_US 120000 /* 120 ms */ =20 #define GEN3_GEN4_EQ_PRESET_INIT 5 =20 @@ -1597,15 +1602,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_= pcie_dw *pcie) data &=3D ~APPL_CTRL_LTSSM_EN; writel(data, pcie->appl_base + APPL_CTRL); =20 - err =3D readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, - data, - ((data & - APPL_DEBUG_LTSSM_STATE_MASK) >> - APPL_DEBUG_LTSSM_STATE_SHIFT) =3D=3D - LTSSM_STATE_PRE_DETECT, - 1, LTSSM_TIMEOUT); + err =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data, + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_QUIET) = || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_ACT) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_PRE_DETECT_QUI= ET) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_WAIT), + LTSSM_DELAY_US, LTSSM_TIMEOUT_US); if (err) - dev_info(pcie->dev, "Link didn't go to detect state\n"); + dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", data, err= ); } /* * DBI registers may not be accessible after this as PLL-E would be @@ -1685,12 +1689,14 @@ static void pex_ep_event_pex_rst_assert(struct tegr= a_pcie_dw *pcie) appl_writel(pcie, val, APPL_CTRL); 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charset="utf-8" After the link reaches a detect-related LTSSM state, disable LTSSM so it do= es not keep toggling between polling and detect. Do this by polling for the detect state first, then clearing APPL_CTRL_LTSSM_EN in both tegra_pcie_dw_pme_turnoff() and pex_ep_event_pex_rst_assert(). Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Split into two patches drivers/pci/controller/dwc/pcie-tegra194.c | 29 ++++++++++++---------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 5b243c006562..baee73438638 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1594,14 +1594,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_p= cie_dw *pcie) data &=3D ~APPL_PINMUX_PEX_RST; appl_writel(pcie, data, APPL_PINMUX); =20 - /* - * Some cards do not go to detect state even after de-asserting - * PERST#. So, de-assert LTSSM to bring link to detect state. - */ - data =3D readl(pcie->appl_base + APPL_CTRL); - data &=3D ~APPL_CTRL_LTSSM_EN; - writel(data, pcie->appl_base + APPL_CTRL); - err =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data, ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_QUIET) = || ((data & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_ACT) || @@ -1610,6 +1602,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_p= cie_dw *pcie) LTSSM_DELAY_US, LTSSM_TIMEOUT_US); if (err) dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", data, err= ); + + /* + * Deassert LTSSM state to stop the state toggling between + * polling and detect. + */ + data =3D readl(pcie->appl_base + APPL_CTRL); + data &=3D ~APPL_CTRL_LTSSM_EN; + writel(data, pcie->appl_base + APPL_CTRL); } /* * DBI registers may not be accessible after this as PLL-E would be @@ -1683,11 +1683,6 @@ static void pex_ep_event_pex_rst_assert(struct tegra= _pcie_dw *pcie) if (pcie->ep_state =3D=3D EP_STATE_DISABLED) return; =20 - /* Disable LTSSM */ - val =3D appl_readl(pcie, APPL_CTRL); - val &=3D ~APPL_CTRL_LTSSM_EN; - appl_writel(pcie, val, APPL_CTRL); - ret =3D readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_QUIET) || ((val & APPL_DEBUG_LTSSM_STATE_MASK) =3D=3D LTSSM_STATE_DETECT_ACT) || @@ -1698,6 +1693,14 @@ static void pex_ep_event_pex_rst_assert(struct tegra= _pcie_dw *pcie) if (ret) dev_info(pcie->dev, "LTSSM state: 0x%x detect timeout: %d\n", val, ret); =20 + /* + * Deassert LTSSM state to stop the state toggling between + * polling and detect. + */ + val =3D appl_readl(pcie, APPL_CTRL); + val &=3D ~APPL_CTRL_LTSSM_EN; + appl_writel(pcie, val, APPL_CTRL); + reset_control_assert(pcie->core_rst); =20 tegra_pcie_disable_phy(pcie); --=20 2.34.1 From nobody Sun Apr 5 16:29:47 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011030.outbound.protection.outlook.com [52.101.52.30]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96D80396D30; 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charset="utf-8" From: Vidya Sagar As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe Endpoint device should be in D3 state to assert WAKE# pin. The previous workaround that forced downstream devices to D0 before taking the link to L2 cited PCI Express Base r4.0 v1.0 sec 5.2 Link State Power Management; however, that spec does not explicitly require putting the device into D0 and only indicates that power removal may be initiated without transitioning to D3Hot. Remove the D0 workaround so that Endpoint devices can use wake functionality (WAKE# from D3). With some Endpoints the link may not enter L2 when they remain in D3, but the Root Port continues with the usual flow after PME timeout, so there is no functional issue. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V6 -> V8: Fix commit message Changes V1 -> V6: None drivers/pci/controller/dwc/pcie-tegra194.c | 41 ---------------------- 1 file changed, 41 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index baee73438638..7e15597df6c1 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1258,44 +1258,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegr= a_pcie_dw *pcie, return 0; } =20 -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) -{ - struct dw_pcie_rp *pp =3D &pcie->pci.pp; - struct pci_bus *child, *root_port_bus =3D NULL; - struct pci_dev *pdev; - - /* - * link doesn't go into L2 state with some of the endpoints with Tegra - * if they are not in D0 state. So, need to make sure that immediate - * downstream devices are in D0 state before sending PME_TurnOff to put - * link into L2 state. - * This is as per PCI Express Base r4.0 v1.0 September 27-2017, - * 5.2 Link State Power Management (Page #428). - */ - - list_for_each_entry(child, &pp->bridge->bus->children, node) { - if (child->parent =3D=3D pp->bridge->bus) { - root_port_bus =3D child; - break; - } - } - - if (!root_port_bus) { - dev_err(pcie->dev, "Failed to find downstream bus of Root Port\n"); - return; - } - - /* Bring downstream devices to D0 if they are not already in */ - list_for_each_entry(pdev, &root_port_bus->devices, bus_list) { - if (PCI_SLOT(pdev->devfn) =3D=3D 0) { - if (pci_set_power_state(pdev, PCI_D0)) - dev_err(pcie->dev, - "Failed to transition %s to D0 state\n", - dev_name(&pdev->dev)); - } - } -} - static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) { pcie->slot_ctl_3v3 =3D devm_regulator_get_optional(pcie->dev, "vpcie3v3"); @@ -1625,7 +1587,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pc= ie_dw *pcie) =20 static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { - tegra_pcie_downstream_dev_to_D0(pcie); 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charset="utf-8" The PERST (PERST#) GPIO interrupt is only registered when the controller is operating in Endpoint mode. In Root Port mode, the PERST GPIO is configured as an output to control downstream devices, and no interrupt is registered for it. Currently, tegra_pcie_dw_stop_link() unconditionally calls disable_irq() on pex_rst_irq, which causes issues in Root Port mode where this IRQ is not registered. Fix this by only disabling the PERST IRQ when operating in Endpoint mode, where the interrupt is actually registered and used to detect PERST assertion/deassertion from the host. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe Endpoint mode in Teg= ra194") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Reviewed-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V8: None drivers/pci/controller/dwc/pcie-tegra194.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 7e15597df6c1..f3428fd3345c 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1025,7 +1025,8 @@ static void tegra_pcie_dw_stop_link(struct dw_pcie *p= ci) { struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); =20 - disable_irq(pcie->pex_rst_irq); + if (pcie->of_data->mode =3D=3D DW_PCIE_EP_TYPE) + disable_irq(pcie->pex_rst_irq); } =20 static const struct dw_pcie_ops tegra_dw_pcie_ops =3D { --=20 2.34.1 From nobody Sun Apr 5 16:29:47 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012039.outbound.protection.outlook.com [40.93.195.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FDA23B2FD2; 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charset="utf-8" From: Vidya Sagar The GPIO DT property "nvidia,refclk-select" to select the PCIe reference clock is optional. Use devm_gpiod_get_optional() to get it. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Teg= ra194") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V5 -> V8: None Changes V4 -> V5: Added Fixes tag Changes V1 -> V4: None drivers/pci/controller/dwc/pcie-tegra194.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index f3428fd3345c..e0b17ad3052d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1167,9 +1167,9 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_d= w *pcie) return err; } =20 - pcie->pex_refclk_sel_gpiod =3D devm_gpiod_get(pcie->dev, - "nvidia,refclk-select", - GPIOD_OUT_HIGH); + pcie->pex_refclk_sel_gpiod =3D devm_gpiod_get_optional(pcie->dev, + "nvidia,refclk-select", + GPIOD_OUT_HIGH); if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { int err =3D PTR_ERR(pcie->pex_refclk_sel_gpiod); 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charset="utf-8" From: Vidya Sagar Pre-silicon simulation showed the Endpoint initiating speed change after secondary bus reset; the HW team recommended disabling this feature in the Endpoint. Disable direct speed change for the Endpoint so it does not initiate speed change after physical layer link up at gen1, leaving speed change ownership with the host. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Teg= ra194") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Fix commit mesaage Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index e0b17ad3052d..0be701e58238 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1805,6 +1805,10 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) =20 reset_control_deassert(pcie->core_rst); =20 + val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &=3D ~PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + if (pcie->update_fc_fixup) { val =3D dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); val |=3D 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; 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charset="utf-8" From: Vidya Sagar LTR message should be sent as soon as the Root Port enables LTR in the Endpoint. Set snoop and no-snoop LTR timing and LTR message request before the PCIe link comes up so that the LTR message is sent upstream as soon as LTR is enabled. This addresses the case where the host has not yet programmed Max Snoop/ No-Snoop latencies in config space. Without programming these values, the Endpoint would send 0 latencies to the host. The hardware later compares these requested values with the Max latencies configured by the host and sends the appropriate values upstream once the host sets them. Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Teg= ra194") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Fix commit message Changes V6 -> V7: Retain FIELD_PREP() usage Changes V1 -> V6: None drivers/pci/controller/dwc/pcie-tegra194.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 0be701e58238..602ff8131887 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -485,15 +485,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, v= oid *arg) if (val & PCI_COMMAND_MASTER) { ktime_t timeout; =20 - /* 110us for both snoop and no-snoop */ - val =3D FIELD_PREP(PCI_LTR_VALUE_MASK, 110) | - FIELD_PREP(PCI_LTR_SCALE_MASK, 2) | - LTR_MSG_REQ | - FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) | - FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) | - LTR_NOSNOOP_MSG_REQ; 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charset="utf-8" From: Vidya Sagar Host software initiates the L2 sequence. PCIe link is kept in L2 state during suspend. If Endpoint mode is enabled and the link is up, the software cannot proceed with suspend. However, when the PCIe Endpoint driver is probed, but the PCIe link is not up, Tegra can go into suspend state. So, allow system to suspend in this case. Fixes: de2bbf2b71bb ("PCI: tegra194: Don't allow suspend when Tegra PCIe is= in EP mode") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Fix commit message Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-tegra194.c | 31 +++++++++++++++++----- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 602ff8131887..375eafabcf88 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2269,16 +2269,28 @@ static void tegra_pcie_dw_remove(struct platform_de= vice *pdev) gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); } =20 -static int tegra_pcie_dw_suspend_late(struct device *dev) +static int tegra_pcie_dw_suspend(struct device *dev) { struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); - u32 val; =20 if (pcie->of_data->mode =3D=3D DW_PCIE_EP_TYPE) { - dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n"); - return -EPERM; + if (pcie->ep_state =3D=3D EP_STATE_ENABLED) { + dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed\n"); + return -EPERM; + } + + disable_irq(pcie->pex_rst_irq); + return 0; } =20 + return 0; +} + +static int tegra_pcie_dw_suspend_late(struct device *dev) +{ + struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); + u32 val; + if (!pcie->link_state) return 0; =20 @@ -2298,6 +2310,9 @@ static int tegra_pcie_dw_suspend_noirq(struct device = *dev) { struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); =20 + if (pcie->of_data->mode =3D=3D DW_PCIE_EP_TYPE) + return 0; + if (!pcie->link_state) return 0; =20 @@ -2312,6 +2327,9 @@ static int tegra_pcie_dw_resume_noirq(struct device *= dev) struct tegra_pcie_dw *pcie =3D dev_get_drvdata(dev); int ret; =20 + if (pcie->of_data->mode =3D=3D DW_PCIE_EP_TYPE) + return 0; + if (!pcie->link_state) return 0; =20 @@ -2344,8 +2362,8 @@ static int tegra_pcie_dw_resume_early(struct device *= dev) u32 val; =20 if (pcie->of_data->mode =3D=3D DW_PCIE_EP_TYPE) { - dev_err(dev, "Suspend is not supported in EP mode"); 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charset="utf-8" From: Vidya Sagar Free up the resources during remove() that were acquired by the DesignWare driver for the Endpoint mode during probe(). Fixes: bb617cbd8151 ("PCI: tegra194: Clean up the exit path for Endpoint mo= de") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V8: None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 375eafabcf88..1cc80f3065d5 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2250,6 +2250,7 @@ static int tegra_pcie_dw_probe(struct platform_device= *pdev) static void tegra_pcie_dw_remove(struct platform_device *pdev) { struct tegra_pcie_dw *pcie =3D platform_get_drvdata(pdev); + struct dw_pcie_ep *ep =3D &pcie->pci.ep; =20 if (pcie->of_data->mode =3D=3D DW_PCIE_RC_TYPE) { if (!pcie->link_state) @@ -2261,6 +2262,7 @@ static void tegra_pcie_dw_remove(struct platform_devi= ce *pdev) } else { disable_irq(pcie->pex_rst_irq); pex_ep_event_pex_rst_assert(pcie); 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charset="utf-8" Tegra194 PCIe driver uses custom version number to detect Tegra194 and Tegra234 IPs. With version detect logic added, version check results in mismatch warnings. tegra194-pcie 14100000.pcie: Versions don't match (0000562a !=3D 3536322a) Use HW version numbers which matches to PORT_LOGIC.PCIE_VERSION_OFF in Tegra194 driver to avoid this kernel warnings. Fixes: a54e19073718 ("PCI: tegra194: Add Tegra234 PCIe support") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Reviewed-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Split into two patches Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-designware.h | 2 ++ drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index f4cf1602cc99..5bceadbd2c9f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -34,8 +34,10 @@ #define DW_PCIE_VER_470A 0x3437302a #define DW_PCIE_VER_480A 0x3438302a #define DW_PCIE_VER_490A 0x3439302a +#define DW_PCIE_VER_500A 0x3530302a #define DW_PCIE_VER_520A 0x3532302a #define DW_PCIE_VER_540A 0x3534302a +#define DW_PCIE_VER_562A 0x3536322a =20 #define __dw_pcie_ver_cmp(_pci, _ver, _op) \ ((_pci)->version _op DW_PCIE_VER_ ## _ver) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 1cc80f3065d5..4cc0bdb0b9da 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -35,8 +35,8 @@ #include #include "../../pci.h" =20 -#define TEGRA194_DWC_IP_VER 0x490A -#define TEGRA234_DWC_IP_VER 0x562A +#define TEGRA194_DWC_IP_VER DW_PCIE_VER_500A +#define TEGRA234_DWC_IP_VER DW_PCIE_VER_562A =20 #define APPL_PINMUX 0x0 #define APPL_PINMUX_PEX_RST BIT(0) --=20 2.34.1 From nobody Sun Apr 5 16:29:47 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011043.outbound.protection.outlook.com [52.101.62.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6D343BF69C; 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charset="utf-8" The ECRC (TLP digest) workaround was originally added for DesignWare version 4.90a. Tegra234 SoC has 5.00a DWC HW version, which has the same ATU TD override behaviour, so apply the workaround for 5.00a too. Fixes: a54e19073718 ("PCI: tegra194: Add Tegra234 PCIe support") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Reviewed-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Split into two patches Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 345365ea97c7..c4dc2d88649e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -486,7 +486,7 @@ static inline void dw_pcie_writel_atu_ob(struct dw_pcie= *pci, u32 index, u32 reg static inline u32 dw_pcie_enable_ecrc(u32 val) { /* - * DesignWare core version 4.90A has a design issue where the 'TD' + * DWC versions 0x3530302a and 0x3536322a has a design issue where the 'T= D' * bit in the Control register-1 of the ATU outbound region acts * like an override for the ECRC setting, i.e., the presence of TLP * Digest (ECRC) in the outgoing TLPs is solely determined by this @@ -559,7 +559,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, if (upper_32_bits(limit_addr) > upper_32_bits(parent_bus_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |=3D PCIE_ATU_INCREASE_REGION_SIZE; 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charset="utf-8" From: Vidya Sagar When Tegra234 is operating in the Endpoint mode with L1.2 enabled, PCIe link goes down during L1.2 exit. This is because Tegra234 is powering up UPHY PLL immediately without making sure that the REFCLK is stable. This is causing UPHY PLL to not lock to the correct frequency and leading to link going down. There is no hardware fix for this, hence do not advertise the L1.2 capability in the Endpoint mode. Fixes: a54e19073718 ("PCI: tegra194: Add Tegra234 PCIe support") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V8: Add fixes tag and move to fixes series Changes V1 -> V7: None drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 4cc0bdb0b9da..c7cae3a004ec 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -234,6 +234,7 @@ struct tegra_pcie_dw_of_data { bool has_sbr_reset_fix; bool has_l1ss_exit_fix; bool has_ltr_req_fix; + bool disable_l1_2; u32 cdm_chk_int_en_bit; u32 gen4_preset_vec; u8 n_fts[2]; @@ -679,6 +680,22 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) if (pcie->supports_clkreq) pci->l1ss_support =3D true; =20 + /* + * Disable L1.2 capability advertisement for Tegra234 Endpoint mode. + * Tegra234 has a hardware bug where during L1.2 exit, the UPHY PLL is + * powered up immediately without waiting for REFCLK to stabilize. This + * causes the PLL to fail to lock to the correct frequency, resulting in + * PCIe link loss. Since there is no hardware fix available, we prevent + * the Endpoint from advertising L1.2 support by clearing the L1.2 bits + * in the L1 PM Substates Capabilities register. This ensures the host + * will not attempt to enter L1.2 state with this Endpoint. + */ + if (pcie->of_data->disable_l1_2 && pcie->of_data->mode =3D=3D DW_PCIE_EP_= TYPE) { + val =3D dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); + val &=3D ~(PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2); + dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val); + } + /* Program L0s and L1 entrance latencies */ val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); val &=3D ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; @@ -2443,6 +2460,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pc= ie_dw_ep_of_data =3D { .mode =3D DW_PCIE_EP_TYPE, .has_l1ss_exit_fix =3D true, .has_ltr_req_fix =3D true, + .disable_l1_2 =3D true, .cdm_chk_int_en_bit =3D BIT(18), /* Gen4 - 6, 8 and 9 presets enabled */ .gen4_preset_vec =3D 0x340, --=20 2.34.1 From nobody Sun Apr 5 16:29:47 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013011.outbound.protection.outlook.com [40.93.196.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB3293B6BF9; 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charset="utf-8" When PERST# is deasserted twice (assert -> deassert -> assert -> deassert), a CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc (PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify() and dw_pcie_ep_cleanup() are called before reset_control_deassert() powers on the controller core. The call chain that causes the timeout: pex_ep_event_pex_rst_deassert() pci_epc_deinit_notify() pci_epf_test_epc_deinit() pci_epf_test_clear_bar() pci_epc_clear_bar() dw_pcie_ep_clear_bar() __dw_pcie_ep_reset_bar() dw_pcie_dbi_ro_wr_en() <- Accesses 0x8bc DBI register reset_control_deassert(pcie->core_rst) <- Core powered on HERE The DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only accessible after the controller core is powered on via reset_control_deassert(pcie->core_rst). Accessing them before this point results in a CBB timeout because the hardware is not yet operational. Fix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to after reset_control_deassert(pcie->core_rst), ensuring the controller is fully powered on before any DBI register accesses occur. Fixes: 40e2125381dc ("PCI: tegra194: Move controller cleanups to pex_ep_eve= nt_pex_rst_deassert()") Reviewed-by: Jon Hunter Tested-by: Jon Hunter Reviewed-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V8: None drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index c7cae3a004ec..b497b178bb7e 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1749,10 +1749,6 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) goto fail_phy; } =20 - /* Perform cleanup that requires refclk */ - pci_epc_deinit_notify(pcie->pci.ep.epc); - dw_pcie_ep_cleanup(&pcie->pci.ep); - /* Clear any stale interrupt statuses */ appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0); appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0); @@ -1822,6 +1818,10 @@ static void pex_ep_event_pex_rst_deassert(struct teg= ra_pcie_dw *pcie) =20 reset_control_deassert(pcie->core_rst); =20 + /* Perform cleanup that requires refclk and core reset deasserted */ + pci_epc_deinit_notify(pcie->pci.ep.epc); + dw_pcie_ep_cleanup(&pcie->pci.ep); + val =3D dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val &=3D ~PORT_LOGIC_SPEED_CHANGE; dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); --=20 2.34.1