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charset="utf-8" Tegra Endpoint exposes three 64-bit BARs at indices 0, 2, and 4: - BAR0+BAR1: EPF test/data (programmable 64-bit BAR) - BAR2+BAR3: MSI-X table (hardware-backed) - BAR4+BAR5: DMA registers (hardware-backed) Update tegra_pcie_epc_features so that BAR2 is BAR_RESERVED with PCI_EPC_BAR_RSVD_MSIX_TBL_RAM (64 KB) & PCI_EPC_BAR_RSVD_MSIX_PBA_RAM (64 K= B) and BAR4 is BAR_RESERVED with PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO (4KB). This keeps CONSECUTIVE_BAR_TEST working while allowing the host to use 64-bit BAR2 (MSI-X) and BAR4 (DMA). Signed-off-by: Manikanta Maddireddy Reviewed-by: Niklas Cassel --- v3: Rebased on pci/endpoint v2: Split MSI-X table and PBA reserved region drivers/pci/controller/dwc/pcie-tegra194.c | 42 +++++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index c5381ffdf1eb..ea7a6256450c 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1978,16 +1978,48 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_e= p *ep, u8 func_no, return 0; } =20 -/* Tegra EP: BAR0 =3D 64-bit programmable BAR */ +static const struct pci_epc_bar_rsvd_region tegra194_bar2_rsvd[] =3D { + { + /* MSI-X table structure */ + .type =3D PCI_EPC_BAR_RSVD_MSIX_TBL_RAM, + .offset =3D 0x0, + .size =3D SZ_64K, + }, + { + /* MSI-X PBA structure */ + .type =3D PCI_EPC_BAR_RSVD_MSIX_PBA_RAM, + .offset =3D 0x10000, + .size =3D SZ_64K, + }, +}; + +static const struct pci_epc_bar_rsvd_region tegra194_bar4_rsvd[] =3D { + { + /* DMA_CAP (BAR4: DMA Port Logic Structure) */ + .type =3D PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO, + .offset =3D 0x0, + .size =3D SZ_4K, + }, +}; + +/* Tegra EP: BAR0 =3D 64-bit programmable BAR, BAR2 =3D 64-bit MSI-X tabl= e, BAR4 =3D 64-bit DMA regs. */ static const struct pci_epc_features tegra_pcie_epc_features =3D { DWC_EPC_COMMON_FEATURES, .linkup_notifier =3D true, .msi_capable =3D true, .bar[BAR_0] =3D { .only_64bit =3D true, }, - .bar[BAR_2] =3D { .type =3D BAR_DISABLED, }, - .bar[BAR_3] =3D { .type =3D BAR_DISABLED, }, - .bar[BAR_4] =3D { .type =3D BAR_DISABLED, }, - .bar[BAR_5] =3D { .type =3D BAR_DISABLED, }, + .bar[BAR_2] =3D { + .type =3D BAR_RESERVED, + .only_64bit =3D true, + .nr_rsvd_regions =3D ARRAY_SIZE(tegra194_bar2_rsvd), + .rsvd_regions =3D tegra194_bar2_rsvd, + }, + .bar[BAR_4] =3D { + .type =3D BAR_RESERVED, + .only_64bit =3D true, + .nr_rsvd_regions =3D ARRAY_SIZE(tegra194_bar4_rsvd), + .rsvd_regions =3D tegra194_bar4_rsvd, + }, .align =3D SZ_64K, }; =20 --=20 2.34.1