From nobody Sun Apr 5 13:04:14 2026 Received: from zg8tmtyylji0my4xnjeumjiw.icoremail.net (zg8tmtyylji0my4xnjeumjiw.icoremail.net [162.243.161.220]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0F7851A6807; Tue, 24 Mar 2026 07:32:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.161.220 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337550; cv=none; b=mbVRgOGCyBLnJuR0ZkpX8OdaJDxT09QkbZGzQ4WpexnVsTIPdLVmEHEHgypZIr0NXtPb2QPID4G57rt0HRAAbbpOyErTzdqySpdsHwW+KEvOQ8gBweJj/cD78axvZVJCGIXdNHE6shZvenrqr3kYUhbV5GX3zFs8F53gQxVc2ZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337550; c=relaxed/simple; bh=1gUWxuLGVhKAP4NDxrLqkR0pAoFWnUAm/zmpMxSlBeA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YH2ttK+u0xfGm52oa6jys6FG1nZFDbu2f7/vmtwr+GclB2q7JaPUyM8hSdPLoTPeJhVoizc4TOdAmUshXpkqWMlR3rzOfYPklRIreYsUJVXklYJ0R5sEUbvdO0e3WZuV1DsjiUMg239VvFcSmBcd3RINAjACghL8yC/laKtn4GA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=162.243.161.220 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app1 (Coremail) with SMTP id TAJkCgCXLHHjPcJplDsLAA--.42174S2; Tue, 24 Mar 2026 15:31:48 +0800 (CST) From: lizhi2@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.chevallier@bootlin.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, horms@kernel.org, Zhi Li , Conor Dooley Subject: [PATCH net-next v5 1/3] dt-bindings: ethernet: eswin: add clock sampling control Date: Tue, 24 Mar 2026 15:31:36 +0800 Message-ID: <20260324073137.396-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260324073017.376-1-lizhi2@eswincomputing.com> References: <20260324073017.376-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TAJkCgCXLHHjPcJplDsLAA--.42174S2 X-Coremail-Antispam: 1UD129KBjvJXoWxKr1rtr45ur43Xr1UXr17trb_yoWxtF15pF W5CrW5GFn5Xr1fCa17tF10kFyfJws7uF9xCr18t3Z7Xws0vFWYqr12yFy5Ga4UCr4xZFy5 WFWYgay8ua4jk3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRimiiDUUUU X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ Content-Type: text/plain; charset="utf-8" From: Zhi Li Due to chip backend reasons, there is already an approximately 4-5 ns skew between the RX clock and data of the eth1 MAC controller inside the silicon. For 1000M, the RX clock must be inverted since it is not possible to meet the RGMII timing requirements using only rx-internal-delay-ps on the MAC together with the standard 2 ns delay on the PHY. Therefore, even on a properly designed board, eth1 still requires RX clock inversion. This behaviour effectively breaks the RGMII timing assumptions at the SoC level. For the TX path of eth1, there is also a skew between the TX clock and data on the MAC controller inside the silicon. This skew happens to be approximately 2 ns. Therefore, it can be considered that the 2 ns delay of TX is provided by the MAC, so the TX is compliant with the RGMII standard. For 10/100 operation, the approximately 4-5 ns skew in the chip does not break the standard. The RGMII timing table (Section 3.3) specifies that for 10/100 operation the maximum value is unspecified: https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-processors/= 20655/1/RGMIIv2_0_final_hp.pdf Due to the eth1 silicon behavior described above, a new compatible string "eswin,eic7700-qos-eth-clk-inversion" is added to the device tree. This allows the driver to handle the differences between eth1 and eth0 through dedicated logic. The rx-internal-delay-ps and tx-internal-delay-ps properties now use minimum and maximum constraints to reflect the actual hardware delay range (0-2540 ps) applied in 20 ps steps. This relaxes the binding validation compared to the previous enum-based definition and avoids regressions for existing DTBs while keeping the same hardware limits. Treat the RX/TX internal delay properties as optional, board-specific tuning knobs and remove them from the example to avoid encouraging their use. In addition, the binding now includes additional background information about the HSP CSR registers accessed by the MAC. The TXD and RXD delay control registers are included so the driver can explicitly clear any residual configuration left by the bootloader. Background reference for the High-Speed Subsystem and HSP CSR block is available in Chapter 10 ("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual, Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf): https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/r= eleases There are currently no in-tree users of the EIC7700 Ethernet driver, so these changes are safe. Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 So= C") Signed-off-by: Zhi Li Acked-by: Conor Dooley --- .../bindings/net/eswin,eic7700-eth.yaml | 69 +++++++++++++++---- 1 file changed, 55 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b= /Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index 91e8cd1db67b..0b27719feb7d 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -20,6 +20,7 @@ select: contains: enum: - eswin,eic7700-qos-eth + - eswin,eic7700-qos-eth-clk-inversion required: - compatible =20 @@ -29,7 +30,9 @@ allOf: properties: compatible: items: - - const: eswin,eic7700-qos-eth + - enum: + - eswin,eic7700-qos-eth + - eswin,eic7700-qos-eth-clk-inversion - const: snps,dwmac-5.20 =20 reg: @@ -63,16 +66,29 @@ properties: - const: stmmaceth =20 rx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 2540 + multipleOf: 20 =20 tx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 2540 + multipleOf: 20 =20 eswin,hsp-sp-csr: description: HSP CSR is to control and get status of different high-speed periphe= rals (such as Ethernet, USB, SATA, etc.) via register, which can tune board-level's parameters of PHY, etc. + + Additional background information about the High-Speed Subsystem + and the HSP CSR block is available in Chapter 10 ("High-Speed Interf= ace") + of the EIC7700X SoC Technical Reference Manual, Part 4 + (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is + publicly available at + https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-M= anual/releases + + This reference is provided for background information only. $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: @@ -82,6 +98,8 @@ properties: - description: Offset of AXI clock controller Low-Power request register - description: Offset of register controlling TX/RX clock delay + - description: Offset of register controlling TXD delay + - description: Offset of register controlling RXD delay =20 required: - compatible @@ -93,8 +111,6 @@ required: - phy-mode - resets - reset-names - - rx-internal-delay-ps - - tx-internal-delay-ps - eswin,hsp-sp-csr =20 unevaluatedProperties: false @@ -104,24 +120,49 @@ examples: ethernet@50400000 { compatible =3D "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; reg =3D <0x50400000 0x10000>; + interrupt-parent =3D <&plic>; + interrupts =3D <61>; + interrupt-names =3D "macirq"; clocks =3D <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, <&d0_clock 193>; clock-names =3D "axi", "cfg", "stmmaceth", "tx"; + resets =3D <&reset 95>; + reset-names =3D "stmmaceth"; + eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>; + phy-handle =3D <&gmac0_phy0>; + phy-mode =3D "rgmii-id"; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config =3D <&stmmac_axi_setup_gmac0>; + + stmmac_axi_setup_gmac0: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,rd_osr_lmt =3D <2>; + snps,wr_osr_lmt =3D <2>; + }; + }; + + ethernet@50410000 { + compatible =3D "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-= 5.20"; + reg =3D <0x50410000 0x10000>; interrupt-parent =3D <&plic>; - interrupts =3D <61>; + interrupts =3D <70>; interrupt-names =3D "macirq"; - phy-mode =3D "rgmii-id"; - phy-handle =3D <&phy0>; - resets =3D <&reset 95>; + clocks =3D <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 194>; + clock-names =3D "axi", "cfg", "stmmaceth", "tx"; + resets =3D <&reset 94>; reset-names =3D "stmmaceth"; - rx-internal-delay-ps =3D <200>; - tx-internal-delay-ps =3D <200>; - eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x100 0x108 0x118>; - snps,axi-config =3D <&stmmac_axi_setup>; + eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>; + phy-handle =3D <&gmac1_phy0>; + phy-mode =3D "rgmii-id"; snps,aal; snps,fixed-burst; snps,tso; - stmmac_axi_setup: stmmac-axi-config { + snps,axi-config =3D <&stmmac_axi_setup_gmac1>; + + stmmac_axi_setup_gmac1: stmmac-axi-config { snps,blen =3D <0 0 0 0 16 8 4>; snps,rd_osr_lmt =3D <2>; snps,wr_osr_lmt =3D <2>; --=20 2.25.1 From nobody Sun Apr 5 13:04:14 2026 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.237.72.81]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 16F292E7631; Tue, 24 Mar 2026 07:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.237.72.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337666; cv=none; b=ZSXwyRL3sZ/yoZH0+bBstSJ3DzL2JnEsXUR5Ac5fvAusQQiz5G0vj4im0pZzQz2/qS3/hZtbHDHdOADZu4qnrMqmUc19l7ZxNmNrghjS68qB+tgOmqv10nmmmtA6AXA5bVLUzvoI2B46iCqQPBKAslALf2/yHF99Qpcx3kfBPbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337666; c=relaxed/simple; bh=z4n3PCrtTDdq36Yvi4h1mo7cmkQTPxqEfzbacDx+P6Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cL246dJrkKcExkGFy8FokWtUadH0Bgjs6fQegTLUd6fx5XhvNSuYiq3ANpaJ2PXTkllTh3k0i1ntX+Jo2Y48zU/SDkKi1T8K+i4EDEJXfisyMDaaV35YIuhbyW0SLFJs4DlFbXKmq0YxyuOgxG+C4RRAxwpdM8EvXFLe7AZ+XgA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=52.237.72.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app1 (Coremail) with SMTP id TAJkCgAXrHBgPsJpwDsLAA--.21779S2; Tue, 24 Mar 2026 15:33:53 +0800 (CST) From: lizhi2@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.chevallier@bootlin.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, horms@kernel.org, Zhi Li Subject: [PATCH net-next v5 2/3] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing Date: Tue, 24 Mar 2026 15:32:05 +0800 Message-ID: <20260324073350.419-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260324073017.376-1-lizhi2@eswincomputing.com> References: <20260324073017.376-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TAJkCgAXrHBgPsJpwDsLAA--.21779S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Zw4ktF15AF1xAFyUtrWDArb_yoWDWFy5pF WkAFy5tr1jqr1fG3yvyF4kta4Fkw47WF1rArWfKFnFyF98trn8XayjyasIkF98Wry7Zr13 J3yUAFyxuF129rJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRMrWrDUUUU X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ From: Zhi Li The second Ethernet controller (eth1) on the Eswin EIC7700 SoC may fail to sample RX data correctly at Gigabit speed due to EIC7700-specific receive clock to data skew at the MAC input in the silicon. The existing internal delay configuration does not provide sufficient adjustment range to compensate for this condition at 1000Mbps. Update the EIC7700 DWMAC glue driver to apply EIC7700-specific clock sampling inversion only during Gigabit operation on MAC instances that require it. TXD and RXD delay registers are explicitly cleared during initialization to override any residual configuration left by the bootloader. All HSP CSR register accesses are performed only after the required clocks are enabled. Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver") Signed-off-by: Zhi Li --- .../ethernet/stmicro/stmmac/dwmac-eic7700.c | 183 ++++++++++++++---- 1 file changed, 140 insertions(+), 43 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-eic7700.c index bcb8e000e720..33144611da8d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c @@ -28,20 +28,40 @@ =20 /* * TX/RX Clock Delay Bit Masks: - * - TX Delay: bits [14:8] =E2=80=94 TX_CLK delay (unit: 0.1ns per bit) - * - RX Delay: bits [30:24] =E2=80=94 RX_CLK delay (unit: 0.1ns per bit) + * - TX Delay: bits [14:8] =E2=80=94 TX_CLK delay (unit: 0.02ns per bit) + * - TX Invert : bit [15] + * - RX Delay: bits [30:24] =E2=80=94 RX_CLK delay (unit: 0.02ns per bit) + * - RX Invert : bit [31] */ #define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8) #define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24) +#define EIC7700_ETH_TX_INV_DELAY BIT(15) +#define EIC7700_ETH_RX_INV_DELAY BIT(31) =20 -#define EIC7700_MAX_DELAY_UNIT 0x7F +#define EIC7700_MAX_DELAY_STEPS 0x7F +#define EIC7700_DELAY_STEP_PS 20 +#define EIC7700_MAX_DELAY_PS \ + (EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS) =20 static const char * const eic7700_clk_names[] =3D { "tx", "axi", "cfg", }; =20 +struct eic7700_dwmac_data { + bool rgmii_rx_clk_invert; +}; + struct eic7700_qos_priv { + struct device *dev; struct plat_stmmacenet_data *plat_dat; + struct regmap *eic7700_hsp_regmap; + u32 eth_axi_lp_ctrl_offset; + u32 eth_phy_ctrl_offset; + u32 eth_txd_offset; + u32 eth_clk_offset; + u32 eth_rxd_offset; + u32 eth_clk_dly_param; + bool eth_rx_clk_inv; }; =20 static int eic7700_clks_config(void *priv, bool enabled) @@ -61,8 +81,28 @@ static int eic7700_clks_config(void *priv, bool enabled) static int eic7700_dwmac_init(struct device *dev, void *priv) { struct eic7700_qos_priv *dwc =3D priv; + int ret; + + ret =3D eic7700_clks_config(dwc, true); + if (ret) + return ret; + + ret =3D regmap_set_bits(dwc->eic7700_hsp_regmap, + dwc->eth_phy_ctrl_offset, + EIC7700_ETH_TX_CLK_SEL | + EIC7700_ETH_PHY_INTF_SELI); + if (ret) { + eic7700_clks_config(dwc, false); + return ret; + } + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset, + EIC7700_ETH_CSYSREQ_VAL); + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0); + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0); =20 - return eic7700_clks_config(dwc, true); + return 0; } =20 static void eic7700_dwmac_exit(struct device *dev, void *priv) @@ -88,18 +128,35 @@ static int eic7700_dwmac_resume(struct device *dev, vo= id *priv) return ret; } =20 +static void eic7700_dwmac_fix_speed(void *priv, phy_interface_t interface, + int speed, unsigned int mode) +{ + struct eic7700_qos_priv *dwc =3D (struct eic7700_qos_priv *)priv; + u32 dly_param =3D dwc->eth_clk_dly_param; + + switch (speed) { + case SPEED_1000: + if (dwc->eth_rx_clk_inv) + dly_param |=3D EIC7700_ETH_RX_INV_DELAY; + break; + case SPEED_100: + case SPEED_10: + break; + default: + dev_err(dwc->dev, "invalid speed %u\n", speed); + break; + } + + regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, dly_param); +} + static int eic7700_dwmac_probe(struct platform_device *pdev) { + const struct eic7700_dwmac_data *data; struct plat_stmmacenet_data *plat_dat; struct stmmac_resources stmmac_res; struct eic7700_qos_priv *dwc_priv; - struct regmap *eic7700_hsp_regmap; - u32 eth_axi_lp_ctrl_offset; - u32 eth_phy_ctrl_offset; - u32 eth_phy_ctrl_regset; - u32 eth_rxd_dly_offset; - u32 eth_dly_param =3D 0; - u32 delay_ps; + u32 delay_ps, val; int i, ret; =20 ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); @@ -116,70 +173,95 @@ static int eic7700_dwmac_probe(struct platform_device= *pdev) if (!dwc_priv) return -ENOMEM; =20 + dwc_priv->dev =3D &pdev->dev; + + data =3D device_get_match_data(&pdev->dev); + if (!data) + return dev_err_probe(&pdev->dev, + -EINVAL, "no match data found\n"); + + dwc_priv->eth_rx_clk_inv =3D data->rgmii_rx_clk_invert; + /* Read rx-internal-delay-ps and update rx_clk delay */ if (!of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", &delay_ps)) { - u32 val =3D min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + if (delay_ps % EIC7700_DELAY_STEP_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "rx delay must be multiple of %dps\n", + EIC7700_DELAY_STEP_PS); + + if (delay_ps > EIC7700_MAX_DELAY_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "rx delay out of range\n"); =20 - eth_dly_param &=3D ~EIC7700_ETH_RX_ADJ_DELAY; - eth_dly_param |=3D FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val); - } else { - return dev_err_probe(&pdev->dev, -EINVAL, - "missing required property rx-internal-delay-ps\n"); + val =3D delay_ps / EIC7700_DELAY_STEP_PS; + + dwc_priv->eth_clk_dly_param &=3D ~EIC7700_ETH_RX_ADJ_DELAY; + dwc_priv->eth_clk_dly_param |=3D + FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val); } =20 /* Read tx-internal-delay-ps and update tx_clk delay */ if (!of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", &delay_ps)) { - u32 val =3D min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT); + if (delay_ps % EIC7700_DELAY_STEP_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "tx delay must be multiple of %dps\n", + EIC7700_DELAY_STEP_PS); + + if (delay_ps > EIC7700_MAX_DELAY_PS) + return dev_err_probe(&pdev->dev, -EINVAL, + "tx delay out of range\n"); + + val =3D delay_ps / EIC7700_DELAY_STEP_PS; =20 - eth_dly_param &=3D ~EIC7700_ETH_TX_ADJ_DELAY; - eth_dly_param |=3D FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val); - } else { - return dev_err_probe(&pdev->dev, -EINVAL, - "missing required property tx-internal-delay-ps\n"); + dwc_priv->eth_clk_dly_param &=3D ~EIC7700_ETH_TX_ADJ_DELAY; + dwc_priv->eth_clk_dly_param |=3D + FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val); } =20 - eic7700_hsp_regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "eswin,hsp-sp-csr"); - if (IS_ERR(eic7700_hsp_regmap)) + dwc_priv->eic7700_hsp_regmap =3D + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "eswin,hsp-sp-csr"); + if (IS_ERR(dwc_priv->eic7700_hsp_regmap)) return dev_err_probe(&pdev->dev, - PTR_ERR(eic7700_hsp_regmap), + PTR_ERR(dwc_priv->eic7700_hsp_regmap), "Failed to get hsp-sp-csr regmap\n"); =20 ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 1, ð_phy_ctrl_offset); + 1, &dwc_priv->eth_phy_ctrl_offset); if (ret) return dev_err_probe(&pdev->dev, ret, "can't get eth_phy_ctrl_offset\n"); =20 - regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset, - ð_phy_ctrl_regset); - eth_phy_ctrl_regset |=3D - (EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI); - regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset, - eth_phy_ctrl_regset); - ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 2, ð_axi_lp_ctrl_offset); + 2, &dwc_priv->eth_axi_lp_ctrl_offset); if (ret) return dev_err_probe(&pdev->dev, ret, "can't get eth_axi_lp_ctrl_offset\n"); =20 - regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset, - EIC7700_ETH_CSYSREQ_VAL); + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 3, &dwc_priv->eth_clk_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "can't get eth_clk_offset\n"); =20 ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp-sp-csr", - 3, ð_rxd_dly_offset); + 4, &dwc_priv->eth_txd_offset); if (ret) return dev_err_probe(&pdev->dev, ret, - "can't get eth_rxd_dly_offset\n"); + "can't get eth_txd_offset\n"); =20 - regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset, - eth_dly_param); + ret =3D of_property_read_u32_index(pdev->dev.of_node, + "eswin,hsp-sp-csr", + 5, &dwc_priv->eth_rxd_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "can't get eth_rxd_offset\n"); =20 plat_dat->num_clks =3D ARRAY_SIZE(eic7700_clk_names); plat_dat->clks =3D devm_kcalloc(&pdev->dev, @@ -208,12 +290,27 @@ static int eic7700_dwmac_probe(struct platform_device= *pdev) plat_dat->exit =3D eic7700_dwmac_exit; plat_dat->suspend =3D eic7700_dwmac_suspend; plat_dat->resume =3D eic7700_dwmac_resume; + plat_dat->fix_mac_speed =3D eic7700_dwmac_fix_speed; =20 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } =20 +static const struct eic7700_dwmac_data eic7700_dwmac_data =3D { + .rgmii_rx_clk_invert =3D false, +}; + +static const struct eic7700_dwmac_data eic7700_dwmac_data_clk_inversion = =3D { + .rgmii_rx_clk_invert =3D true, +}; + static const struct of_device_id eic7700_dwmac_match[] =3D { - { .compatible =3D "eswin,eic7700-qos-eth" }, + { .compatible =3D "eswin,eic7700-qos-eth", + .data =3D &eic7700_dwmac_data, + }, + { + .compatible =3D "eswin,eic7700-qos-eth-clk-inversion", + .data =3D &eic7700_dwmac_data_clk_inversion, + }, { } }; MODULE_DEVICE_TABLE(of, eic7700_dwmac_match); --=20 2.25.1 From nobody Sun Apr 5 13:04:14 2026 Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D55973358C2; Tue, 24 Mar 2026 07:34:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=206.189.21.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337689; cv=none; b=nHphsrVAx1ZrWDgEhe6Jb67hy2XnZVeyf6qYSy/icYo3rc5o0un9eQH7sL5Y2c06LybrWifK3fSrBuWmRULVgGT3SrtF+lEPuzeWlKyDWL4CdMikDFqwKBnxzvJLHsXsnQAxtk/+HTo4N63bBIjG/x5I58IJ7rtwsTCTYtP6Frw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774337689; c=relaxed/simple; bh=9NqFRadax7AtkssXZXghsvWQ2TMnz7wfVN+4Myf13hk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TJh9Q0hc5aHcxJXSDIjzHyLvDdju4rF6XBJcmHJhIpC7Eg6a8ecx3HyjQt24QbBsF2T8vVeSFMKlTWN7vzcDgvxIcKkOj2W0jDVrJ/sAD7XcTqf0pdJtl/w6qda9FdmfkrIqvPY2agY0H4OElfRhOx6q3H+o6EUPo/o7AXGdK68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=206.189.21.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004057DT.eswin.cn (unknown [10.11.96.26]) by app2 (Coremail) with SMTP id TQJkCgDX7J91PsJp6jYLAA--.23271S2; Tue, 24 Mar 2026 15:34:14 +0800 (CST) From: lizhi2@eswincomputing.com To: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.chevallier@bootlin.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, horms@kernel.org, Zhi Li Subject: [PATCH net-next v5 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller Date: Tue, 24 Mar 2026 15:34:08 +0800 Message-ID: <20260324073408.439-1-lizhi2@eswincomputing.com> X-Mailer: git-send-email 2.52.0.windows.1 In-Reply-To: <20260324073017.376-1-lizhi2@eswincomputing.com> References: <20260324073017.376-1-lizhi2@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgDX7J91PsJp6jYLAA--.23271S2 X-Coremail-Antispam: 1UD129KBjvJXoWxurWxtw1DWr1xtFy8WFWDCFg_yoWrGw45pF 47urZ5XrWrWr1xA34YvFy09FZxJws7GF95Krn7tFyDGF4q9FWYvr4jy3WfJF17ArWUX3y5 WFs3t34FkF4vy3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRdWrXUUUUU= X-CM-SenderInfo: xol2xx2s6h245lqf0zpsxwx03jof0z/ Content-Type: text/plain; charset="utf-8" From: Zhi Li Enable the on-board Gigabit Ethernet controller on the HiFive Premier P550 development board. Signed-off-by: Zhi Li --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 42 ++++++++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 66 +++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/ar= ch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 131ed1fc6b2e..5a40be1d2a25 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -13,6 +13,8 @@ / { =20 aliases { serial0 =3D &uart0; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; }; =20 chosen { @@ -20,6 +22,46 @@ chosen { }; }; =20 +&gmac0 { + phy-handle =3D <&gmac0_phy0>; + phy-mode =3D "rgmii-id"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio106_pins>; + rx-internal-delay-ps =3D <20>; + tx-internal-delay-ps =3D <100>; + status =3D "okay"; + + mdio { + gmac0_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0>; + reset-gpios =3D <&gpioD 10 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + }; + }; +}; + +&gmac1 { + phy-handle =3D <&gmac1_phy0>; + phy-mode =3D "rgmii-rxid"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio111_pins>; + rx-internal-delay-ps =3D <200>; + tx-internal-delay-ps =3D <200>; + status =3D "okay"; + + mdio { + gmac1_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0>; + reset-gpios =3D <&gpioD 15 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + }; + }; +}; + &uart0 { status =3D "okay"; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/e= swin/eic7700.dtsi index c3ed93008bca..f1a01d5736a1 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -5,6 +5,8 @@ =20 /dts-v1/; =20 +#include + / { #address-cells =3D <2>; #size-cells =3D <2>; @@ -295,6 +297,70 @@ uart4: serial@50940000 { status =3D "disabled"; }; =20 + gmac0: ethernet@50400000 { + compatible =3D "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; + reg =3D <0x0 0x50400000 0x0 0x10000>; + interrupts =3D <61>; + interrupt-names =3D "macirq"; + clocks =3D <&clk 186>, + <&clk 171>, + <&clk 40>, + <&clk 193>; + clock-names =3D "axi", "cfg", "stmmaceth", "tx"; + resets =3D <&reset 95>; + reset-names =3D "stmmaceth"; + eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config =3D <&stmmac_axi_setup_gmac0>; + status =3D "disabled"; + + stmmac_axi_setup_gmac0: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,rd_osr_lmt =3D <2>; + snps,wr_osr_lmt =3D <2>; + }; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + gmac1: ethernet@50410000 { + compatible =3D "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20"; + reg =3D <0x0 0x50410000 0x0 0x10000>; + interrupts =3D <70>; + interrupt-names =3D "macirq"; + clocks =3D <&clk 186>, + <&clk 171>, + <&clk 40>, + <&clk 194>; + clock-names =3D "axi", "cfg", "stmmaceth", "tx"; + resets =3D <&reset 94>; + reset-names =3D "stmmaceth"; + eswin,hsp-sp-csr =3D <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config =3D <&stmmac_axi_setup_gmac1>; + status =3D "disabled"; + + stmmac_axi_setup_gmac1: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,rd_osr_lmt =3D <2>; + snps,wr_osr_lmt =3D <2>; + }; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + gpio@51600000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0x0 0x51600000 0x0 0x80>; --=20 2.25.1