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Mon, 23 Mar 2026 22:58:59 -0700 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v10 RESEND 3/3] i2c: tegra: Add support for Tegra410 Date: Tue, 24 Mar 2026 11:28:43 +0530 Message-ID: <20260324055843.549808-4-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260324055843.549808-1-kkartik@nvidia.com> References: <20260324055843.549808-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE32:EE_|PH0PR12MB5629:EE_ X-MS-Office365-Filtering-Correlation-Id: bb0cfdc6-16b9-4bc8-6528-08de896a7977 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|921020|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: nBNoON4RMdg2jmn5lzzZfUgI33AFfJIwrt6RAWRTYYl2NH8jOhY9x9cjvQhbxP5P7urQctMz1jOSOpt7gr1dzfA+Va9rAYtP/JaHUdnIv8hcwJtMPh1TNYdRy2Xz2hKpJHZHGoc476IN7Cvttb1m/I7HQlkugpnZ09oM5Jt+N1MywdcM24jYbibUj73QHnrLJIibjtFxl9a209ARfuHOAZMuk8nO11DXaCfk220TRbmAleHU7b3d4O49Mdn1UiT0/Ttn9p1paZaOcCZFtuaByohOGYEEiZTz+bXWm3/vVbEabRucjI5eO5yVq8EOeGHN+KzCh4K427ihmNB0RCqeZ0ked1lCS3vWW6bBQiQA4vWjqQqtOL7TrPXKy8FYYzCW3rjIFtxcuNVSUWLUjXLN13RqhuluaooPuSoBg8yiuHUWqQQZ6+8deTGVCIF4N8Q8f0uOhad48IYbHkPcSGWaeRrPiwUgyZ1gcKwzyA/U3p0xuQVf/Xa7iDGv8KedKh6PNdJQP+hCMp/EpGvBo46+Ad6gHEV1fUXE1n2IurQT50fpA4k0rQW6Rec8nzZc6fGRBtz8FrhiBpaFOKsZMLaCbGl+SJolUljF9i0qKUrMUdVKhAO9Uy/I33+n3jffX956yqnk9rk282GIHha6Gn/qJM4CTS3t00oCt5opPhGeryUEAfnFUdVxIIa8tFHf+Lsu+ydJfMfw5IlKFBUaB/Ijpf5rEjzVIdUmmn8p98e1HkWDpxLvEljcZ22+/N8HFKhQuZma/0im4D2BGQfEc3awHu2XOhBInrCeurTyqiQuIH/LYPHMXFIgFyHgkrhvzdFY X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(1800799024)(921020)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; 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charset="utf-8" Add support for the Tegra410 SoC, which has 4 I2C controllers. The controllers are feature-equivalent to Tegra264; only the register offsets differ. Signed-off-by: Kartik Rajput Reviewed-by: Jon Hunter Tested-by: Jon Hunter Acked-by: Thierry Reding --- Changes in v3: * Updated timing parameters for Tegra410. --- drivers/i2c/busses/i2c-tegra.c | 63 ++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2950930b5501..9fd5ade774a0 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -275,6 +275,34 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = =3D { .sw_mutex =3D 0x0ec, }; =20 +static const struct tegra_i2c_regs tegra410_i2c_regs =3D { + .cnfg =3D 0x000, + .status =3D 0x01c, + .sl_cnfg =3D 0x020, + .sl_addr1 =3D 0x02c, + .sl_addr2 =3D 0x030, + .tx_fifo =3D 0x054, + .rx_fifo =3D 0x058, + .packet_transfer_status =3D 0x05c, + .fifo_control =3D 0x060, + .fifo_status =3D 0x064, + .int_mask =3D 0x068, + .int_status =3D 0x06c, + .clk_divisor =3D 0x070, + .bus_clear_cnfg =3D 0x088, + .bus_clear_status =3D 0x08c, + .config_load =3D 0x090, + .clken_override =3D 0x094, + .interface_timing_0 =3D 0x098, + .interface_timing_1 =3D 0x09c, + .hs_interface_timing_0 =3D 0x0a0, + .hs_interface_timing_1 =3D 0x0a4, + .master_reset_cntrl =3D 0x0ac, + .mst_fifo_control =3D 0x0b8, + .mst_fifo_status =3D 0x0bc, + .sw_mutex =3D 0x0f0, +}; + /* * msg_end_type: The bus control which needs to be sent at end of transfer. * @MSG_END_STOP: Send stop pulse. @@ -2085,6 +2113,40 @@ static const struct tegra_i2c_hw_feature tegra264_i2= c_hw =3D { .regs =3D &tegra264_i2c_regs, }; =20 +static const struct tegra_i2c_hw_feature tegra410_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x3f, + .clk_divisor_fast_mode =3D 0x2c, + .clk_divisor_fast_plus_mode =3D 0x11, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D true, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D true, + .has_mst_reset =3D true, + .quirks =3D &tegra194_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D false, + .tlow_std_mode =3D 0x8, + .thigh_std_mode =3D 0x7, + .tlow_fast_mode =3D 0x2, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x2, + .thigh_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x8, + .thigh_hs_mode =3D 0x6, + .setup_hold_time_std_mode =3D 0x08080808, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, + .setup_hold_time_hs_mode =3D 0x0b0b0b, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D true, + .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra410_i2c_regs, +}; + static const struct of_device_id tegra_i2c_of_match[] =3D { { .compatible =3D "nvidia,tegra264-i2c", .data =3D &tegra264_i2c_hw, }, { .compatible =3D "nvidia,tegra256-i2c", .data =3D &tegra256_i2c_hw, }, @@ -2398,6 +2460,7 @@ static const struct acpi_device_id tegra_i2c_acpi_mat= ch[] =3D { {.id =3D "NVDA0101", .driver_data =3D (kernel_ulong_t)&tegra210_i2c_hw}, {.id =3D "NVDA0201", .driver_data =3D (kernel_ulong_t)&tegra186_i2c_hw}, {.id =3D "NVDA0301", .driver_data =3D (kernel_ulong_t)&tegra194_i2c_hw}, + {.id =3D "NVDA2017", .driver_data =3D (kernel_ulong_t)&tegra410_i2c_hw}, { } }; MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); --=20 2.43.0