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Mon, 23 Mar 2026 22:20:35 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:35 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 7/7] PCI: mediatek-gen3: Integrate new pwrctrl API Date: Tue, 24 Mar 2026 13:19:59 +0800 Message-ID: <20260324052002.4072430-8-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the new PCI pwrctrl API and PCI slot binding and power drivers, we now have a way to describe and power up WiFi/BT adapters connected through a PCIe or M.2 slot, or populated onto the mainboard itself. The latter case has the adapter layout or design copied verbatim, replacing the slot with direct connections. Integrate the PCI pwrctrl API into the PCIe driver, so that power is properly enabled before PCIe link training is done, allowing the card to successfully be detected. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- Changes since v5: - Adapt to PCI_PWRCTRL_SLOT -> PCI_PWRCTRL_GENERIC Kconfig symbol namechange --- drivers/pci/controller/Kconfig | 1 + drivers/pci/controller/pcie-mediatek-gen3.c | 38 ++++++++++++++++----- 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 5aaed8ac6e44..686349e09cd3 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -222,6 +222,7 @@ config PCIE_MEDIATEK_GEN3 depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on PCI_MSI select IRQ_MSI_LIB + select PCI_PWRCTRL_GENERIC help Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed, diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 208866d33c77..a94fdbaf47fe 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -421,15 +422,23 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_= pcie *pcie) val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } + + err =3D pci_pwrctrl_power_on_devices(pcie->dev); + if (err) { + dev_err(pcie->dev, "Failed to power on devices: %pe\n", ERR_PTR(err)); + return err; + } =20 - /* - * Described in PCIe CEM specification revision 6.0. - * - * The deassertion of PERST# should be delayed 100ms (TPVPERL) - * for the power and clock to become stable. - */ - msleep(PCIE_T_PVPERL_MS); + /* + * Described in PCIe CEM specification revision 6.0. + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); =20 + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { /* De-assert reset signals */ val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); @@ -449,6 +458,8 @@ static void mtk_pcie_devices_power_down(struct mtk_gen3= _pcie *pcie) val |=3D PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); } + + pci_pwrctrl_power_off_devices(pcie->dev); } =20 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) @@ -1209,9 +1220,15 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) return dev_err_probe(dev, err, "Failed to setup IRQ domains\n"); =20 + err =3D pci_pwrctrl_create_devices(pcie->dev); + if (err) { + goto err_tear_down_irq; + dev_err_probe(dev, err, "failed to create pwrctrl devices\n"); + } + err =3D mtk_pcie_setup(pcie); if (err) - goto err_tear_down_irq; + goto err_destroy_pwrctrl; =20 host->ops =3D &mtk_pcie_ops; host->sysdata =3D pcie; @@ -1225,6 +1242,9 @@ static int mtk_pcie_probe(struct platform_device *pde= v) err_power_down_pcie: mtk_pcie_devices_power_down(pcie); mtk_pcie_power_down(pcie); +err_destroy_pwrctrl: + if (err !=3D -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(pcie->dev); err_tear_down_irq: mtk_pcie_irq_teardown(pcie); return err; @@ -1240,7 +1260,9 @@ static void mtk_pcie_remove(struct platform_device *p= dev) pci_remove_root_bus(host->bus); pci_unlock_rescan_remove(); =20 + pci_pwrctrl_power_off_devices(pcie->dev); mtk_pcie_power_down(pcie); + pci_pwrctrl_destroy_devices(pcie->dev); mtk_pcie_irq_teardown(pcie); } =20 --=20 2.53.0.983.g0bb29b3bc5-goog