From nobody Sun Apr 5 16:35:10 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CD052E6116 for ; Tue, 24 Mar 2026 05:20:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329616; cv=none; b=F1ixwm9C9vELFz5sEpnMVQvbLnQBonbVBCJWu/gM2m++dqHsczG35s/BtciUPjKZfUT0Qao/CzuUhNzRCBGnDWF8oJiEL3DE7pS30VkDcvzuCsdKIFGYoDhCeHkZxZ01TK+3zqj9etpvmkNtm3Q/APDCXGplVtt/BMQWIXV5B/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329616; c=relaxed/simple; bh=phvAnSpR1eSl5qsE+squuz1VYQdzp5vQhwkgbm0GIbc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l7coZbdjGfFfUA+BGIaqdETkygydc06AxoWITihxiMKnY04YCEdXr+B916Wrs/HLHU7FKndyCwVk+DsJPLKNTS+3QsILsWmZM4n0e6qg4jr5PDJhCquUQEZYECCjSSEQu8PiMgiRTqAfVGrU956FNlOVwMcGt6bsYoPCdlKHpkc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=UJXHZy9J; arc=none smtp.client-ip=209.85.216.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="UJXHZy9J" Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-35a1230c60eso1703672a91.3 for ; Mon, 23 Mar 2026 22:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1774329615; x=1774934415; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d+G5opAB+jyNCsDIm/30vZQM14H1ghGVf70HXUwqlUM=; b=UJXHZy9JTxJA+Il27Gb79gv59RmBGE0etnVy74DUtL53mUaSvnIPyRb1Cj+Ee4byks kPt4D4IHgwzI64Ai5UB5KceeYglPMSyJz7YneS4gnuVrJvkCk6w6yv+Z5BNw6OtpAm7W 4JCLQX+w9pMcIkrWyMcwG0oddvZmgSLtY27iI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774329615; x=1774934415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=d+G5opAB+jyNCsDIm/30vZQM14H1ghGVf70HXUwqlUM=; b=qsnlsJt2djjfrU/0Kr19bJj8EP5BzqvhAhOho0wzaiKjRrJig3dyHTZ5skS5Fa+KOO ZCYF9tRUzPns+Mbst6P7P0G6KbLcLy98jRvwsqrNdNyh0jTO19rc99bXjyAJ6zGPbRs2 sH11vHMbDBBYdZVCpVJXwHdrAkzRSPZJZ/spulDh3iVEEkvEUtyaWDYjH2LkWLmAtwbp LTiQ5fLhL4BTpc6Eq7R2801q9GklNKxFctHrqXArX32fRFDTQhpttIM9LZrDbcbxfgdj 8fSM6XO9ahuPmb+GEco5WXWs1MDVZPlMGVMOLzp/2/+IW+Y/NJEqGyuEUkJJPovBzHum JaMQ== X-Forwarded-Encrypted: i=1; AJvYcCXjb8cqO57LPvlaCykKFAM5nL7EujrDhebZFYU5tWQ70L7tHeZpOPwpC7anhnB2lSvscL434mmkxlJigk0=@vger.kernel.org X-Gm-Message-State: AOJu0YzwOnKf50NY1dDT2fja+i5H0nmlySJkRnTdgQBYHJMTJ3NuNLfq giVCRBnRz1e0CQZ4BHhPJ6D/0/NOUhMO1IgCau6bznjLQRNYflsSgKWaM/bfFnDSmw== X-Gm-Gg: ATEYQzwJot+APmT4wHWvmVor9ZOK1ni3m5iTsV1GnDdE2u5lwyXEgPa3AH2DZzYHzX4 1ZyK/krYECEcARcKe/2wf0pSvLTO0QDweR9W+DV/Dp3mb5OJA4W+GdClq9cEHpkmYfzweTKL1OG 5oXuKrs1J4ZBAuEoSJTahfFdOL33g/YcvVXULDmbwCdcwk8LD2ORQyMKqGk7klMtqvkLQIcYOW5 OkmNNSDxQUEW1WBbMwpncm/AVS4BEKMk+Ke6kyJsryfunY0NipcDN0NuS90m6460h9V25ECNTsT tOFDT70jcfM+ukwx3TkOBPQrKH50TqAht3rO3jbtEYJTgpGh1KraaRAxWCXoAiJhW9rrtj6J6TJ +P0MTQjTs9oDu6+W535qY3FpDdeSwStDL/iMkpGv6b5sa/4ubgrEQMCls81U2kdeb5IYLQegF46 Taqn2hoCyCL38CGpXsSlWVpfaRtVx/ZH4HRAoCajrbJKycLN28MR36q7C1x+dQXNwtItHDSutuL kTyMBTK X-Received: by 2002:a17:90a:ec84:b0:35b:e56e:b5a6 with SMTP id 98e67ed59e1d1-35be56eb622mr6319388a91.1.1774329614922; Mon, 23 Mar 2026 22:20:14 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:14 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 1/7] PCI: mediatek-gen3: Clean up mtk_pcie_parse_port() with dev_err_probe() Date: Tue, 24 Mar 2026 13:19:53 +0800 Message-ID: <20260324052002.4072430-2-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mtk_pcie_parse_port() in the pcie-mediatek-gen driver has a bunch of if (err) { dev_err(dev, "error message\n"); return err; # or goto } patterns. Simplify these with dev_err_probe(). The system also gains proper deferred probe messages that can be seen in /sys/kernel/debug/devices_deferred Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- drivers/pci/controller/pcie-mediatek-gen3.c | 36 ++++++--------------- 1 file changed, 10 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 75ddb8bee168..1939cac995b5 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -876,10 +876,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *p= cie) if (!regs) return -EINVAL; pcie->base =3D devm_ioremap_resource(dev, regs); - if (IS_ERR(pcie->base)) { - dev_err(dev, "failed to map register base\n"); - return PTR_ERR(pcie->base); - } + if (IS_ERR(pcie->base)) + return dev_err_probe(dev, PTR_ERR(pcie->base), "failed to map register b= ase\n"); =20 pcie->reg_base =3D regs->start; =20 @@ -888,34 +886,20 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *= pcie) =20 ret =3D devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets); - if (ret) { - dev_err(dev, "failed to get PHY bulk reset\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to get PHY bulk reset\n"); =20 pcie->mac_reset =3D devm_reset_control_get_optional_exclusive(dev, "mac"); - if (IS_ERR(pcie->mac_reset)) { - ret =3D PTR_ERR(pcie->mac_reset); - if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "failed to get MAC reset\n"); - - return ret; - } + if (IS_ERR(pcie->mac_reset)) + return dev_err_probe(dev, PTR_ERR(pcie->mac_reset), "failed to get MAC r= eset\n"); =20 pcie->phy =3D devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(pcie->phy)) { - ret =3D PTR_ERR(pcie->phy); - if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "failed to get PHY\n"); - - return ret; - } + if (IS_ERR(pcie->phy)) + return dev_err_probe(dev, PTR_ERR(pcie->phy), "failed to get PHY\n"); =20 pcie->num_clks =3D devm_clk_bulk_get_all(dev, &pcie->clks); - if (pcie->num_clks < 0) { - dev_err(dev, "failed to get clocks\n"); - return pcie->num_clks; - } + if (pcie->num_clks < 0) + return dev_err_probe(dev, pcie->num_clks, "failed to get clocks\n"); =20 ret =3D of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); if (ret =3D=3D 0) { --=20 2.53.0.983.g0bb29b3bc5-goog From nobody Sun Apr 5 16:35:10 2026 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22BE1299A8F for ; Tue, 24 Mar 2026 05:20:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329620; cv=none; b=jUfYp8BWq/cV5/9V5GbhW9M7ui8jO7/nBf2iNB1FjLuSiP8nLLgqtz5GpP00SanKgwHRFh+NZejZFlf6dJurZwP+gQIPUdPkB1/x7XhcPebydF3WwypOMIkY90LVm0DSy8tW/RzHQYh1MjwkXKIw093mYtRtuiiP0fj9LIGjwyc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329620; c=relaxed/simple; bh=+ezN/B2ZMUl15YakQPOJzFUOlgdtwdAcENxCtoQ+AHM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BO5Mm3OLKK7Gwzf6p9deKIWOGLItp4WSQTmO46i0DKzrhDwlu9l5ncb567vMWCr8gEYdG+jA6osBgPAxQjotapC1tBLKGKamzarAHIfebVBDhCrIiVrmIZ/Fdn/ToPm3S4E5sqfcSvJHQcdDTNfSsGijqBIC+0rlZnNKZZyEASk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=nMzSZzL6; arc=none smtp.client-ip=209.85.216.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="nMzSZzL6" Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-35a211df8e3so585189a91.2 for ; Mon, 23 Mar 2026 22:20:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1774329618; x=1774934418; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O74W4ZMgDpT3MGQ+8wcjX/PqoiKfeKCvLKILcQ8L8Jc=; b=nMzSZzL6KctTDmOxd0axnyBeVoFdgAekcU7DOLQjCEZ3T1gkygbymQaW0SackruzZe A2nP4zCia/o9NvV7REW7deyysbSCKX2KTEtHZxigJDPa8ICgEBbRXB5B5/uFpfHil7wI zgC3a2N2lcnNkGrW9fMAsxbem3H0vmRUcFOmI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774329618; x=1774934418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=O74W4ZMgDpT3MGQ+8wcjX/PqoiKfeKCvLKILcQ8L8Jc=; b=bwGc12mQnLmMeYrfg7UqusilwpcwOIGa6F1Z5cx6E8YciNH935p1iyn+SRJg1Dn0Vu 9B5R+pQpw75TbB0Hqb4AD1vfawvCN5hKxI8cnaBvZZ0XOJwV105CRWtslh+jDrWKCZ9X XNlIieoYr7lp2xNJvB9/k9MhGDX/ZtvWT0Lt+/Nm/5w4pqhX+2qo/ppreCT7/GyNkn76 qiHuNDGXeonmJKGDCr+7SdJdQsH/Lm5JDtYnBRLbtj00FibGlVvl8u9N5gN+W3qPrkbB wDZvCM3nx+DD+et2N+9+kUWKAYSOxvwGEcUybKVbKdCNxMsC/HoKBpg3CozutomwROyG /6Zw== X-Forwarded-Encrypted: i=1; AJvYcCVd7/JFggTHd9324se63SvQs+lCW6/JkGJ5xP6N4cdFcZeG9oNBFGtuGDPaLeOjhij0yNxvnCJ4dAAGksA=@vger.kernel.org X-Gm-Message-State: AOJu0YwohVf6kPWtxeHr5+2zFN6/qQ8Ev00q31jDTjW5BUwhYV4eLyKi L28plDG2nra28ChCfZCPaMtpyI2ZvgzdGBHvYFjWX897XKHGdtgveRZHnJT5EmLJPg== X-Gm-Gg: ATEYQzzhuTbqdB+Ze2NsZYv5A+cTnaWx764lnb21pfOQh2QoLCUbuHIOnY/xAPpvE2p 9ivGY02AIRMG/C0kfEWciDc6u5lXcHnAN8HhXhlYfCn56g+Fyw9YsKjJ4IZNvmx5s75K8Rz6yxe xRo1Y7IC4nmt9Tmt1RuC5LSHqy5GGcNgj7ERmCK13QC1kQoDEsOOet3Dte8ugYwTwQLma1xg7tZ /NLQJ9x22YC5A1sXsp38raq/3l5Y/RgYYnMCDgSc8mxd7AjMf9Enbu+iyJM1dzWFAHyA9YYQMF0 b+VTdQlacVCLTvW8m1jVJmu1JSF1eO3hu/jXAeyQhYJpQP1AvmDDDWrtAWvu2SrTsvBmhGSznZa FvysvODb5ByorDR9g01g7lhbHuyLUbRWhenv0pNerla++4tqfHz41+q+s5E9JA+Mx6Vm67+HkEE fTCT6htRwllB2kWZbzy7jonyy6tyzITQYK1r65aPdDSPkh24Y0mYbN0qTfp2VNMiXx+KDKjzSMq wJdDkbw X-Received: by 2002:a17:90b:4c8e:b0:34c:fe57:2793 with SMTP id 98e67ed59e1d1-35bd2cec778mr11788613a91.20.1774329618496; Mon, 23 Mar 2026 22:20:18 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:18 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Helgaas , Bartosz Golaszewski Subject: [PATCH v6 2/7] PCI: mediatek-gen3: Move mtk_pcie_setup_irq() out of mtk_pcie_setup() Date: Tue, 24 Mar 2026 13:19:54 +0800 Message-ID: <20260324052002.4072430-3-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mtk_pcie_setup_irq() just sets up the IRQ domains for PCI INTx and MSI, and chains them to the controller's interrupt. It's not really related to the setup of the actual PCIe controller. Move the mtk_pcie_setup_irq() call out of and before mtk_pcie_setup(), and add a proper error message for when it fails. Reorder mtk_pcie_irq_teardown() in the remove callback to follow. Also create an error path in the probe function. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260309215056.GA603013@bhelgaas/ Reviewed-by: Bartosz Golaszewski Signed-off-by: Chen-Yu Tsai --- drivers/pci/controller/pcie-mediatek-gen3.c | 25 ++++++++++++--------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 1939cac995b5..04ae195d36c2 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1152,10 +1152,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) if (err) goto err_setup; =20 - err =3D mtk_pcie_setup_irq(pcie); - if (err) - goto err_setup; - return 0; =20 err_setup: @@ -1181,21 +1177,28 @@ static int mtk_pcie_probe(struct platform_device *p= dev) pcie->soc =3D device_get_match_data(dev); platform_set_drvdata(pdev, pcie); =20 + err =3D mtk_pcie_setup_irq(pcie); + if (err) + return dev_err_probe(dev, err, "Failed to setup IRQ domains\n"); + err =3D mtk_pcie_setup(pcie); if (err) - return err; + goto err_tear_down_irq; =20 host->ops =3D &mtk_pcie_ops; host->sysdata =3D pcie; =20 err =3D pci_host_probe(host); - if (err) { - mtk_pcie_irq_teardown(pcie); - mtk_pcie_power_down(pcie); - return err; - } + if (err) + goto err_power_down_pcie; =20 return 0; + +err_power_down_pcie: + mtk_pcie_power_down(pcie); +err_tear_down_irq: + mtk_pcie_irq_teardown(pcie); + return err; } =20 static void mtk_pcie_remove(struct platform_device *pdev) @@ -1208,8 +1211,8 @@ static void mtk_pcie_remove(struct platform_device *p= dev) pci_remove_root_bus(host->bus); pci_unlock_rescan_remove(); =20 - mtk_pcie_irq_teardown(pcie); mtk_pcie_power_down(pcie); + mtk_pcie_irq_teardown(pcie); } =20 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie) --=20 2.53.0.983.g0bb29b3bc5-goog From nobody Sun Apr 5 16:35:10 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93868285068 for ; Tue, 24 Mar 2026 05:20:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329623; cv=none; b=Bk8bASqhrO/L/l/bSD+WiOSvNH33sqYGHixVGJiQRBob0imtrSEF6MDundishG0oZSi0uTOfj3SGmWoacIneygqmScGxkBme0/capOTeNXEfWBffmXNUhug0FMi9/4waI4H0iixrNly/doRSta8M96rvqp+oseR3STYXcl34RjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329623; c=relaxed/simple; bh=Ivul44x/LugXYctG9ddeOlslTKGgpYAlCCLDtP7iazE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s/0iYQUXpZnophrcXJItoeEWiCH3IcAobxuWmVjLYy98RfM0o8rkciAPUD/Xc3Rvtq78UqkeAFGZnhCk1OO0MKTJlaoBtU1cVvdVqSUqZyxtB2YRlozrcoxXsUVnQL7gD6AUiB6XLs1cmB0i2MzCEGe7xsKSOoL95E1IBW1359M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=LdmNfC2Z; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="LdmNfC2Z" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-356337f058aso2803455a91.2 for ; Mon, 23 Mar 2026 22:20:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1774329622; x=1774934422; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uaGuEIl74d/AtM9ivAKLmt9Xm6tlq86gWmFME9IpiWQ=; b=LdmNfC2ZbzmTRGMHmsOTdZEC+0podQ3JEYDU386uQKaB9w9oZvuoY8g1/tqR56cQBj +36Ld0kWaJTcLHFpXKO2ETeyAkVoYat6UlegzG4qq72bE2ex7+lwyHh5LNt+QcmIlhc1 CLsWgjuQw/PR3EnsAXFX1shrW//1OLqZlgcK8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774329622; x=1774934422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=uaGuEIl74d/AtM9ivAKLmt9Xm6tlq86gWmFME9IpiWQ=; b=VKNB3LI2u+xIA/mAOtJ2aqYnSgtYasKHpq6jpUD4lQlDYQe1Lu3+Xvpfn8Lgahd6hU Yzfv6NiQt/yONj287tnnuRvnvgXjgBpPblhporlGnqWSbkfVR+P+c/b6GZzp+8m/wBrw lKL2lmllpemvevzyZHP5jRMvPZeOxAnmlIx0t7FTXH3muktyc5WEAhixnPllgFYAyiFo eYSGTPt+JDnqfhkkFIcdcIu3iwiLsYJxW4/726MtHpndbFeToFeoNJ7QCAfkEK7XA/8G G49E/8BRoS/ugbaokyJZq0MTuYKP1W1qO6nPdYcTkPypLkk3mmJ6XhREnlTzX0Im5Y15 1Jyw== X-Forwarded-Encrypted: i=1; AJvYcCXQdUTBoecxgmp9pQZCLv5rtrQBpf4JTtx5ETuoneL+9Dw49u7hFHLoykpvckYD9MB2xK9V2+NIYYMbiy0=@vger.kernel.org X-Gm-Message-State: AOJu0Yzm2FdUh4oV2s7zC/UCENPfbnnsc67strC5DybKRO55iofHvULV wRsK0hMd/AA6usjSky8BJrjotaB8zvQYeJppF0aXJzFfFgrtLujsnxacloahDkA1dQ== X-Gm-Gg: ATEYQzzKU5nLYD9L4r1wWHmTRoozPlJcPvpXBYo5EcByGJ+SLynyNwUtDvq+VmHT3rv wAEP46SauQTVmetP05MCdGFvMa3Nh8kZE8B/nGUDh85zhy/TQdkNGpSS6zM2jV3sNBT6pEX240N PUKr/c0aUksLAqcX+YnlNWBD9pxENy1OqFBnrA9hoqWRm9SjaglK1Tj5xg4QWb7j5s4HvkuV1ZO gz0Q+k5WdVQIUZXM1F+0+HBzxQGlVkDDP9NRbYdJNCI+5xb7C/5ZKtyufQ5SR9dtplk9/y/rLC6 ueY4ZnwM1lZOmRRX2EWGV4MMmrsp1z/V+BxFOw0tOvtuEyAuRXLsJe1pCTN+kCo0qmTJaUdEZd3 U0FFa9BIZz65u6JGGEQC7VMHKckXFfwUzdCp2Lp3GKsYQX7hBIhHqyLQd/ECIS1Ku2ZSyHXRMSA Z8DaoKNsLXafl/gVsGU0na5+f6pESYf6nq6M5klNP07hsAsUdgnzT4MZBy0clWAKNlRgZkWRdCN bef78DY X-Received: by 2002:a17:90b:390c:b0:35b:e844:3b4 with SMTP id 98e67ed59e1d1-35be8440e51mr6095494a91.32.1774329621952; Mon, 23 Mar 2026 22:20:21 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:21 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bjorn Helgaas , Bartosz Golaszewski Subject: [PATCH v6 3/7] PCI: mediatek-gen3: Move controller setup steps before PERST# control Date: Tue, 24 Mar 2026 13:19:55 +0800 Message-ID: <20260324052002.4072430-4-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting up the translation windows and enabling MSI involve only configuring the controller, not the device. These can be done before the device is enabled. Move these steps before the existing PERST# control. This provides a cleaner separation of controller vs device setup. This also allows the later patches that split out PERST# control and add device power control to have cleaner teardown. This change only moves code. No functional change is expected. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260309215056.GA603013@bhelgaas/ Reviewed-by: Bartosz Golaszewski Signed-off-by: Chen-Yu Tsai --- drivers/pci/controller/pcie-mediatek-gen3.c | 50 ++++++++++----------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 04ae195d36c2..1b6290f2c360 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -464,6 +464,31 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) val |=3D PCIE_DISABLE_DVFSRC_VLT_REQ; writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG); =20 + mtk_pcie_enable_msi(pcie); + + /* Set PCIe translation windows */ + resource_list_for_each_entry(entry, &host->windows) { + struct resource *res =3D entry->res; + unsigned long type =3D resource_type(res); + resource_size_t cpu_addr; + resource_size_t pci_addr; + resource_size_t size; + + if (type =3D=3D IORESOURCE_IO) + cpu_addr =3D pci_pio_to_address(res->start); + else if (type =3D=3D IORESOURCE_MEM) + cpu_addr =3D res->start; + else + continue; + + pci_addr =3D res->start - entry->offset; + size =3D resource_size(res); + err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, + type, &table_index); + if (err) + return err; + } + /* * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal * causing occasional PCIe link down. In order to overcome the issue, @@ -510,31 +535,6 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) return err; } =20 - mtk_pcie_enable_msi(pcie); - - /* Set PCIe translation windows */ - resource_list_for_each_entry(entry, &host->windows) { - struct resource *res =3D entry->res; - unsigned long type =3D resource_type(res); - resource_size_t cpu_addr; - resource_size_t pci_addr; - resource_size_t size; - - if (type =3D=3D IORESOURCE_IO) - cpu_addr =3D pci_pio_to_address(res->start); - else if (type =3D=3D IORESOURCE_MEM) - cpu_addr =3D res->start; - else - continue; - - pci_addr =3D res->start - entry->offset; - size =3D resource_size(res); - err =3D mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size, - type, &table_index); - if (err) - return err; - } - return 0; } =20 --=20 2.53.0.983.g0bb29b3bc5-goog From nobody Sun Apr 5 16:35:10 2026 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9C25283FEA for ; Tue, 24 Mar 2026 05:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329627; cv=none; b=Dvpm2czniT6J0tbJi3nib33Tsw46+2REm/6BElqObV1x/VeY/m7KYq+hzhpq8PvMMxXOoM5EI8Ui8dCmpgvej+rcQcwVP+O/AN8Y+KKgGhsJMBT2oEYcm+RiykYKK5ChTMUsqeSCsGG13JJmV4zHogi05dbBFbS59nJXyOSHmyY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329627; c=relaxed/simple; bh=/AlhRTbtRWo7GbL2ds2v9wvogDNH5q6EjWRr3V3z/rc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IfVu2Tt5vsER3vrwokZroxEZRx0r0h+6Al85e4Y42aZY3QeTiTv/h/UO1iQXY4bEqJCj0OsGkTZH+j3j/bWvhe0wvL637OhYhxBQk8oDXPJKy09gNakRUukVeFmjTr/jeGJebIZXqFRp1Xyf7kCYkMP25webB78yojM1Mvy0dPU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=mpgiqkMk; arc=none smtp.client-ip=209.85.216.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="mpgiqkMk" Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-3590042fa8eso3213189a91.1 for ; Mon, 23 Mar 2026 22:20:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1774329625; x=1774934425; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zcsyifPwpw7PalUEgFntf8CIjQvjzcA0RCRU1Yc2FT4=; b=mpgiqkMk6AkzHkdJJfHxkQKgDj5RYp3+lqt0r/S+AlO0YvbfND26d2rMr+OA35XZUk ADosFyLE0L71XTMKbmJrwEzLDMpYCHIkY3XAO96u4uoHpNqFXk1651NN3dvDN/WgS2Yv AtV0FTc4znOZLSYFvLJ2GYaxz/gnlHillHQ68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774329625; x=1774934425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zcsyifPwpw7PalUEgFntf8CIjQvjzcA0RCRU1Yc2FT4=; b=Qq4NuN887J4/VVYaOBnsaTuSg+RB+Z5GY3Nem9jdambtEfif0s8AuA78r3hAWPzVWf Dy71MerArVw/Xu7ctDoZvi4zULKFrypEe5kQ3XXWJOky1fX1IZ6LNY68HO0qDm6Yglc8 FbBJOAFngwF68FLfVnYt2KYoB19RVMUFqz4LGWjd93pKtV4msC8nZc+fctASW3cJlL0V YAI/dmTd41D435k1Vh4FcvZbZwnRuUwSqlnlzHq8n1RpZWrAU6jT7/fWk25nOp6lpnRV IFud51w6O16PdkRmrFNw7G4VlLRnRe1I3O4F6jHt+0aYcv9bNmQIdwudNNf5vzPgpevk 8nGw== X-Forwarded-Encrypted: i=1; AJvYcCVL1qaIBRzg2hCBDAx2qrh22UhvWZGF2POL0Mv6TACsPnYPsmaE+mYCwli8AKCt7JA3CwlcUWK2aX9OtCU=@vger.kernel.org X-Gm-Message-State: AOJu0YzDnM6/JMhKD3v+aW2ermuQztTpHEgQh5T4A3oGuA7gaJT7Uxco vofoA3OsNiNxHlP2fpWFevnx5R28/0hsoiamu2j8bviAZHF3D2AzNsKe15nE7irBDA== X-Gm-Gg: ATEYQzxTMrvzzwfK3v08572VCBottGxcZKAAxL26NfuJ1vnvpuJGDu6MLw4os7k8xya lGDWwe03sNTh2VHQB7xGXtwzABITjktApDkHcpfJ4Fiy7tYV0D77YXvM93Gqk41uyt4GLFZhfBl vzBaqc0KGsN54+IiE0bMzUGi0lTTQtYRd5EdIvk20hszSmfUHOqU4iZ9dVq19A+H6Sv9IPCdBHr DHjtlyHEycautDMnQW1pWMhV7qGAAEasoPaFL1vVtikIfswGj4zVF5HD1OSfy8I4X26/ALU0afZ kCbHl7qxOR6pKmElP4PJifuYFC4aejeReEbwSXm6h4J2VgKeqaiD9tR/N2Z1AO+ZScjiPrqSv9D jqBoafxHtY4XYn/JJAyIaCqK8/cScz92NinzsTaIqVf1UHvRhDAJJzOvX01hSWAyApaVjwHTqeQ r4Pjfdzt0jE3NN2yMeAT7mfc/CLoiMNtA2MU4b6HWSPdKPSq2V+joKUBwGRHoJP5SvxTjPC0rCC xqLBk+1sXuNA+WkpZg= X-Received: by 2002:a17:90b:510b:b0:35a:1b43:dff1 with SMTP id 98e67ed59e1d1-35bd2bf7926mr12662239a91.12.1774329625440; Mon, 23 Mar 2026 22:20:25 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:24 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 4/7] PCI: mediatek-gen3: Add error path for resume driver callbacks Date: Tue, 24 Mar 2026 13:19:56 +0800 Message-ID: <20260324052002.4072430-5-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resume callback currently does teardown in the conditional block directly. This is going to get ugly when the pwrctrl calls are added. Move the teardown to a proper error cleanup path. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- drivers/pci/controller/pcie-mediatek-gen3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 1b6290f2c360..22a16e4ebc76 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -1304,14 +1304,16 @@ static int mtk_pcie_resume_noirq(struct device *dev) return err; =20 err =3D mtk_pcie_startup_port(pcie); - if (err) { - mtk_pcie_power_down(pcie); - return err; - } + if (err) + goto err_power_down; =20 mtk_pcie_irq_restore(pcie); =20 return 0; + +err_power_down: + mtk_pcie_power_down(pcie); + return err; } =20 static const struct dev_pm_ops mtk_pcie_pm_ops =3D { --=20 2.53.0.983.g0bb29b3bc5-goog From nobody Sun Apr 5 16:35:10 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F8E29B228 for ; Tue, 24 Mar 2026 05:20:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329630; cv=none; b=WY81qv90zfDfT/2TSJogH99dHe//3VrGvQsuzSZaHXGNEEuQxmgm37ecqrxU6W4l2h0lnEBfDk4Ira4C8r9FvU/IcJFSOavyu7cRNb32LgkVhtUV/GHg7rXYDqlDmrdEzGGxSW30PU+D1ApNFiCkL33LUEmbCaXvbvMtMYHp/DU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329630; c=relaxed/simple; bh=KExZ1uFY5D1jLsHcrlxWGkAsKI6SDYhHbGW/69FV8ac=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tDSpbmnvUEeHjFK9j0hCH9BPuU8NkJYTbYseLAadIA5J8+eudW6SScdS4monkVYHyi+3musPLua2u59R2xSRRrnXM0Bh2dyDrOZ/tj59Px2TCC2/nnALCBj1Eb4koaOe7iVnsm9NaA3DBWx3vsqNwWVPHhR2SqBF7zW/iJEXvQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=SUtEOmRy; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="SUtEOmRy" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-35b905e9dc0so541442a91.3 for ; Mon, 23 Mar 2026 22:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1774329629; x=1774934429; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tBBocE8wHIzrURZ8u70flcyVVr5FTdBTVpVQUI9JEgQ=; b=SUtEOmRy6FpQY1Iny3LnWt1oAMv2TrjbztBzF5zT54FeRURVUyN4ho2FqGKpIg1ZWG 88ZFanW6lNm4uf9PbrlcFnKXsQWDSVFFSKa2yPsg3/QAYGtUvv4wyrAdw+lfNUp5abpn rBgXYaNQ5zvcrysO+zOq8L7FzB4u89ljAoydw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774329629; x=1774934429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=tBBocE8wHIzrURZ8u70flcyVVr5FTdBTVpVQUI9JEgQ=; b=SaSi7L5facQeszLNnqku/iwO6iGpGbPWTNN7qNYilne3NSZaipNKA2Yd5DUvFHqnMm ZfbKSCb3jnm/o4PJrkG2vUyaVFgzZmbm2hdVLVbRq4Ls+10nrZuU3FnNbKVu4Ld/jsjT HsjtLPKyLuZYScnAtr/dA5IJDd2/hx73dU/YxlXX0oXGIPCGIJChWKaRXmIWjSInWRVN wqVnaO8aBSJsrAb5SBvO7V0piAIp4PL2sEQSH8HRlzHf+d+D4q+J7EatTdSUUsfbecJC c2BXwOhKj3Rx4rMSToIYo1AJYJ3usviVGLIP8DTAhN7NleJHd3RttNzvOuZFNr4yjfXZ c/1g== X-Forwarded-Encrypted: i=1; AJvYcCUmEjrBB25fHPdil0N7bp47I26cCPALagElmCc030lZplsGBBZIna86ZAYt6ZxYKq0uh3q8ONZlGxcWUGc=@vger.kernel.org X-Gm-Message-State: AOJu0YxfSf6NGHqlXC16UJ/0YT65A0f+BQQBEh4U+fO7m11mymb1oYgQ kWhJwBY99eCv/+PSirgEgu0lDgxM0VA9VQOla1u6Vk/RrxxewC6nkgjaAEab+hnOnw== X-Gm-Gg: ATEYQzzeg93GHrx/3s/Q1Fu3BVgT1ejJQZiDU/GeJv00RuhrJ+cw1pgkvyYmjf81Ddm ckrLXLiRDHjLazlO6eBhCt77nIlV1/moeoBepEllldFI8qcG2B1GdMVRil4niOduct2nKGKn76G 57Vo7QvAHTumsCUxj4sP/o4vD/WuMr0i2HYlpaWesqq5XRQYXEqc4y+ODKZZ/0uAkMZmzYcW1D7 nyxCBInjqzhwb9IZbtjII0/757W0bd4aEOMuPJZzZPU4m38Kk3FLbt1lvHOFeBx8b6HKHo+6vGE sEIwA8VPLmBk7toLPalmZibgoUqen6jqGqsWLoHTBVNvkJxFJ3tzyvfZbwQmIThjnXjPZRc1f8O rn2S1gNrhztloVMD/DRrJ0paclztj9GYljjBRXCM0RpkN9hs805XvZnYZiv9U/UGBUScdVAn2ZN me9NBXXJ0vK80vpZAT0A0fiwKxoI6z5HRg1Y1Agu1SMLTnUp7GgZCb532krh/TlgmHSZc5xhmz3 7GZ8QSqMnLeT4GwmaI= X-Received: by 2002:a17:90b:510a:b0:359:3426:c60a with SMTP id 98e67ed59e1d1-35bd2bd6af9mr13589107a91.4.1774329628786; Mon, 23 Mar 2026 22:20:28 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:28 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 5/7] PCI: mediatek-gen3: Split out device power helpers Date: Tue, 24 Mar 2026 13:19:57 +0800 Message-ID: <20260324052002.4072430-6-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding full power on/off control with the pwrctrl API, split out the existing code that only partially deals with device power sequencing into separate helper functions. The existing code only handles PERST#. This is purely moving code around, and brings no functional changes. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- drivers/pci/controller/pcie-mediatek-gen3.c | 87 ++++++++++++--------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 22a16e4ebc76..526db8815401 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -403,6 +403,54 @@ static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *= pcie) writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG); } =20 +static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie) +{ + int err; + u32 val; + + /* + * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal + * causing occasional PCIe link down. In order to overcome the issue, + * PCIE_RSTB signals are not asserted/released at this stage and the + * PCIe block is reset using en7523_reset_assert() and + * en7581_pci_enable(). + */ + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { + /* Assert all reset signals */ + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); + val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB; + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + + /* + * Described in PCIe CEM specification revision 6.0. + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); + + /* De-assert reset signals */ + val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | + PCIE_PE_RSTB); + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } + + return 0; +} + +static void mtk_pcie_devices_power_down(struct mtk_gen3_pcie *pcie) +{ + u32 val; + + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { + /* Assert the PERST# pin */ + val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); + val |=3D PCIE_PE_RSTB; + writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } +} + static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) { struct resource_entry *entry; @@ -489,33 +537,9 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie = *pcie) return err; } =20 - /* - * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal - * causing occasional PCIe link down. In order to overcome the issue, - * PCIE_RSTB signals are not asserted/released at this stage and the - * PCIe block is reset using en7523_reset_assert() and - * en7581_pci_enable(). - */ - if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { - /* Assert all reset signals */ - val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); - val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB; - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - - /* - * Described in PCIe CEM specification revision 6.0. - * - * The deassertion of PERST# should be delayed 100ms (TPVPERL) - * for the power and clock to become stable. - */ - msleep(PCIE_T_PVPERL_MS); - - /* De-assert reset signals */ - val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB); - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - } + err =3D mtk_pcie_devices_power_up(pcie); + if (err) + return err; =20 /* Check if the link is up or not */ err =3D readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val, @@ -1270,7 +1294,6 @@ static int mtk_pcie_suspend_noirq(struct device *dev) { struct mtk_gen3_pcie *pcie =3D dev_get_drvdata(dev); int err; - u32 val; =20 /* Trigger link to L2 state */ err =3D mtk_pcie_turn_off_link(pcie); @@ -1279,13 +1302,7 @@ static int mtk_pcie_suspend_noirq(struct device *dev) return err; } =20 - if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { - /* Assert the PERST# pin */ - val =3D readl_relaxed(pcie->base + PCIE_RST_CTRL_REG); - val |=3D PCIE_PE_RSTB; - writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); - } - + mtk_pcie_devices_power_down(pcie); dev_dbg(pcie->dev, "entered L2 states successfully"); =20 mtk_pcie_irq_save(pcie); --=20 2.53.0.983.g0bb29b3bc5-goog From nobody Sun Apr 5 16:35:10 2026 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C14CC2E6116 for ; Tue, 24 Mar 2026 05:20:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329634; cv=none; b=pvSVoEZttqhGa5C7YCJK+Ox2MCjkIvllMrMVXSxI/gR6BTtaxngP+BmzK+vr8GdUQTVzasOHeVwWmfbQWWrcRsUfha54mT+osBVMHQIqfHRLenefl5MTU+jP0wVe5chxLlv6Qr/TTcMsBAw1F6rmKnGaTOK60ax+npa3N9+jUU0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329634; c=relaxed/simple; bh=B9OvoSLl+ADp923M20OOIo0J0s8S2OqvmiGPQXQYOfE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q88hP38CFXQeQrNkUZkAiUkKz+ufqlmyADcecEZA2+W6NeKVl2MJq7gvyli2uRlLs6AdxhaX0O6yVhKfgJ3M7jNkO64CHrrDKcQTXbPYvBTfwbuJtqygQoLCrc1QPc/XtscnhRZdwh8MFitqRtW7e2zolW2GlyIJKQ+B4L7MMjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=Pn0cj5b2; arc=none smtp.client-ip=209.85.216.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Pn0cj5b2" Received: by mail-pj1-f50.google.com with SMTP id 98e67ed59e1d1-35ba2ae4df3so2427036a91.2 for ; Mon, 23 Mar 2026 22:20:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1774329632; x=1774934432; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GfQ3i6n0srgdKQ5C4/oS1IhFvqnwaDhA6rAMXlkp0g8=; b=Pn0cj5b2jmi3da3lkZpwRVuvtX7lzDPKfmOg0Th5Bwx+kjTfZ5iFAM2mX99jN63TpI E0Lwujyf9oIGr4kXZeau/ID9vgHxCoGeWYnYWT15/lYS5j8+H3DT1c4hS2Gc64RYytdQ +qL8Xe5SnRWJVX1oCTTBdkjT3TO84d4dlMiLg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774329632; x=1774934432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=GfQ3i6n0srgdKQ5C4/oS1IhFvqnwaDhA6rAMXlkp0g8=; b=AcmI39hwqGx4lYVJxOE55K1CUKxjcEPsuh17N6gYmSq1DZA5b55YODjrY1O0H86DuC AYgPeIXH78l8/sj9Sl4PNJQZ92YeUunFmbs2nAv26v4+xgSjpEJyal2k/bSU29hSrFW0 soE1JNPVxU2PuTqlJgDntiovxHSj3NM62+mGeIWwN9OV1wXormKxTkQjs0MQ4pd2WkRE u/V24GtAxbYl+AuJMJ3EgqQvZO65p/gBL3wQ1sQVSyTs2gIS8KMKHIl+ycUGWutB3AE5 D8xG6ZH6SN/XvVrw17kM389THZJHWerlHQ2Ks71Tex01KpsJq/ukc5kFb+27yEGYBciS m1Dw== X-Forwarded-Encrypted: i=1; AJvYcCUUYSS6ZtypbX9CBCBAXNJNy4ci/pY0zxGmVuXELQyWLH56nCaDtkagTj2th4zma8bfHCdrmVKkAIVVUqo=@vger.kernel.org X-Gm-Message-State: AOJu0Yw8+XRp8QiqpFEj/4WZg0cgI++QKoX6A/G/q7IBJ8kVrSLfX0re fXyuUUSHryEv8iTkx2YQlDFXtoOupXvYxlpjI4Wy3TYci/1CETVkwRtef24QOZlcpA== X-Gm-Gg: ATEYQzzvkclTdMg/xzvLMJfnIhT2G71sTQM9oU2x/LB12qxgDsa78NXnejeiSBhloa+ GysK6G3+EJiEpUdy3GrzwV9Jnwe3qJjzqlSGUOqVcWleciJxRvomQgMiUbzBlFWlY7XTNMxv8F+ U1GOmYGllgWhW5blsIuggsjtvxvF36tr0z2EHRGLqjKO1d3KuAcQcDm1DQW6mZCExqV9sw7838M XmqaP3gwfsW7JGdKa2npSQfB8th38fBeDaPPvjbs9ze6hzaOz/tIpEAENG9Dd5h/IpclIigZryO uoTa+S0Ag7BBxpWn/kSwFixJ6xrfdtiIEVE6INxfItIQbVAneG5Cgu2onf1W50kAEVZZ+Hf0+EP sYoQfEnKL5kjmWP9kJyUMEcAaBYmbB4BHH+sLQiXPkvvbmcJ/9iGGH863SdIH8IrrAKo41xWOzx lgGtd73PtiUGajzYtICVvYFynfA9hafRf95+aF4Y5zkMLUA/39RT89oxkYZIna7HUrPIsRPpKx7 vIU2u0r X-Received: by 2002:a17:90a:1c08:b0:35b:e519:213b with SMTP id 98e67ed59e1d1-35be5192186mr4759182a91.30.1774329632112; Mon, 23 Mar 2026 22:20:32 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:31 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 6/7] PCI: mediatek-gen3: Disable device if further setup fails Date: Tue, 24 Mar 2026 13:19:58 +0800 Message-ID: <20260324052002.4072430-7-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If further setup fails after the device is powered on and link training succeeds, we want to place the device back in a quiescence state to avoid unintended activity and save power. This also helps with power state tracking and balancing once pwrctrl API is integrated. Power down the device in the error paths of mtk_pcie_startup_port() and mtk_pcie_probe(). Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- drivers/pci/controller/pcie-mediatek-gen3.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 526db8815401..208866d33c77 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -556,10 +556,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie= *pcie) dev_err(pcie->dev, "PCIe link down, current LTSSM state: %s (%#x)\n", ltssm_state, val); - return err; + goto err_power_down_device; } =20 return 0; + +err_power_down_device: + mtk_pcie_devices_power_down(pcie); + return err; } =20 #define MTK_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ @@ -1219,6 +1223,7 @@ static int mtk_pcie_probe(struct platform_device *pde= v) return 0; =20 err_power_down_pcie: + mtk_pcie_devices_power_down(pcie); mtk_pcie_power_down(pcie); err_tear_down_irq: mtk_pcie_irq_teardown(pcie); --=20 2.53.0.983.g0bb29b3bc5-goog From nobody Sun Apr 5 16:35:10 2026 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C771283FEA for ; Tue, 24 Mar 2026 05:20:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329637; cv=none; b=OGZ8/dlgSLxyF1SZZ9u8eShWvOCX0dWQoGjenlAtRkjYpbj/si9x+6t8AKpR/7Bus0wwSlktz1ptv44GkRcLSET7zwuoy1rm5srVgt30igjalLKQLtk6xTn4ueLrqT0jHLgX+1Fb9GZcgh8qfWX+UrpP2vE1cht8Go/JVme0mtU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774329637; c=relaxed/simple; bh=fKIbwOS2b08Lxy/ZlhmZIR630mrDoOxAL/X82ZVIgaY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YRSCIyIIyaMO8he7sVzPbjdEw1sGfChCyGKDEsDtASWNN22X1O2zibKvtKaGai/rfhhpdrbXPVSYYiXQ8nhhSCdZcEPlg13F2G3qOXkodi7DJ55n6eUZ+FxDfKetKDqDEdf2nW05Lj8Bec+YhXjBBs3kx3Jua/iYWGUWy6yApgE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=BxfjWfjj; arc=none smtp.client-ip=209.85.216.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="BxfjWfjj" Received: by mail-pj1-f47.google.com with SMTP id 98e67ed59e1d1-35a1d4a095bso2932728a91.0 for ; Mon, 23 Mar 2026 22:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1774329635; x=1774934435; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dTFvdYaRAXH5T4w3zStr4Kcf5DL2tAxoUUkF1NtmwTQ=; b=BxfjWfjjNNUsg39QTCR2AHcOsD/f3ZCr6tyXMu5wwLsxyoZo8WA9dl16uMy8XUXKF2 FfxEmx+zlxgxPeBsdmtC3s9SHLQhLOumWcx0NyNu5exrn5n1bl7BhDYV4V2iKm7IGaNB SJOlRUsSCSFHcawKIRWu1yqQQwKRRnATc+IHc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774329635; x=1774934435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dTFvdYaRAXH5T4w3zStr4Kcf5DL2tAxoUUkF1NtmwTQ=; b=nCQRlUIKK2LNuKMea/0cYQF2JAeA+xMfXyCsSLsgW56Q/oQOnVYRV09LKMNahh2ZJZ UjR5MkF1mrHwBSw5NiMM68TujiQheWAxMR+kpTdEbhY0vP7smxRKS3621IsX7yW5j9Yv wXfUjqNmnWWQ27XIKr3ELiMQ/CKOMziQqCKHWoSdMedEsRwq9F2sVuGz2Pry/gA94r60 2hYB6/J9Bn2uqKDAm0wYtf1cw/R2kKvc6mDdLpb3moRJMnjF2jRSFKZrCwMN9REjLdKT HTCzVm6eUNaHaCnAN9muBXdvmVZLFALoX4L1x+EhQIa2u1KRPUAYP2zijGzosSTs0g/0 vnVA== X-Forwarded-Encrypted: i=1; AJvYcCVni/f6oZ35+fYXlmLU2XjSlmqfPc5b94/NmDoQc+zImLLMwWFa3TjtNOqgXLaTusWovq6KOetYTVOrRoE=@vger.kernel.org X-Gm-Message-State: AOJu0YyFiTYAn/BDgtctDUDeEXRXdZN/AWS+Stez3U2W8uS88GMuspV/ Ex4D4FgfY+Ssn0dBXyVZ71CW5F7hRw9J5kGsv83yar8+EKvq59IctCM2y34zjYEvIQ== X-Gm-Gg: ATEYQzwgvgsTumppz4L0QJIoZDPShroa/1Wv6QdH54HvpY59iyfAS87s5WJLbtALvct 57qnzSLMFGN0IQNEkCHobPajJExNKOLD3oS0EpMmfH4MljLRGNMiDiTAqdlXspczgapq8po76NS l+l3kQvhVflOwgYayg9KIVZqEbMlVEEPLywQopMIzk2YUzU325FWSikT6mf4yXJ0L/zlo5FjcfT 1fImlx1Oc4VFxaVlkkgm4iyabwAGCthtBV+lBCXO71Ac6AtXZwWpsabz8furqcnoOS3d+rVqFEB A9NR4zXzsknTmAs08UmTEssAQqLk6VODm8wwHb6P/S9vzazzBnrM9+TgBrmKfIQG7djahdFVc5n 3p1HgAokbsmKi0qSLZqdGWHff4zjRB63GgbSQxJjkYb0a8q9jHUNKbcnlxsknoIOxOLlqujBDDm oTUwecUTP5YPGysEXPQSnOEy9j4iYC+whrtKP4lsGO8ROGIvVITneL+QOcxqSAXNHRmnAH8+cIR GHfKUfl X-Received: by 2002:a17:90b:3fc4:b0:35b:9f51:a755 with SMTP id 98e67ed59e1d1-35c0092752bmr1620066a91.18.1774329635438; Mon, 23 Mar 2026 22:20:35 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:19a5:8f2f:d584:8078]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c03124a87sm1068647a91.3.2026.03.23.22.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 22:20:35 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 7/7] PCI: mediatek-gen3: Integrate new pwrctrl API Date: Tue, 24 Mar 2026 13:19:59 +0800 Message-ID: <20260324052002.4072430-8-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.983.g0bb29b3bc5-goog In-Reply-To: <20260324052002.4072430-1-wenst@chromium.org> References: <20260324052002.4072430-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the new PCI pwrctrl API and PCI slot binding and power drivers, we now have a way to describe and power up WiFi/BT adapters connected through a PCIe or M.2 slot, or populated onto the mainboard itself. The latter case has the adapter layout or design copied verbatim, replacing the slot with direct connections. Integrate the PCI pwrctrl API into the PCIe driver, so that power is properly enabled before PCIe link training is done, allowing the card to successfully be detected. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Bartosz Golaszewski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Chen-Yu Tsai --- Changes since v5: - Adapt to PCI_PWRCTRL_SLOT -> PCI_PWRCTRL_GENERIC Kconfig symbol namechange --- drivers/pci/controller/Kconfig | 1 + drivers/pci/controller/pcie-mediatek-gen3.c | 38 ++++++++++++++++----- 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 5aaed8ac6e44..686349e09cd3 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -222,6 +222,7 @@ config PCIE_MEDIATEK_GEN3 depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST depends on PCI_MSI select IRQ_MSI_LIB + select PCI_PWRCTRL_GENERIC help Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. This PCIe controller is compatible with Gen3, Gen2 and Gen1 speed, diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index 208866d33c77..a94fdbaf47fe 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -421,15 +422,23 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_= pcie *pcie) val |=3D PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); + } + + err =3D pci_pwrctrl_power_on_devices(pcie->dev); + if (err) { + dev_err(pcie->dev, "Failed to power on devices: %pe\n", ERR_PTR(err)); + return err; + } =20 - /* - * Described in PCIe CEM specification revision 6.0. - * - * The deassertion of PERST# should be delayed 100ms (TPVPERL) - * for the power and clock to become stable. - */ - msleep(PCIE_T_PVPERL_MS); + /* + * Described in PCIe CEM specification revision 6.0. + * + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + msleep(PCIE_T_PVPERL_MS); =20 + if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) { /* De-assert reset signals */ val &=3D ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); @@ -449,6 +458,8 @@ static void mtk_pcie_devices_power_down(struct mtk_gen3= _pcie *pcie) val |=3D PCIE_PE_RSTB; writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG); } + + pci_pwrctrl_power_off_devices(pcie->dev); } =20 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) @@ -1209,9 +1220,15 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) return dev_err_probe(dev, err, "Failed to setup IRQ domains\n"); =20 + err =3D pci_pwrctrl_create_devices(pcie->dev); + if (err) { + goto err_tear_down_irq; + dev_err_probe(dev, err, "failed to create pwrctrl devices\n"); + } + err =3D mtk_pcie_setup(pcie); if (err) - goto err_tear_down_irq; + goto err_destroy_pwrctrl; =20 host->ops =3D &mtk_pcie_ops; host->sysdata =3D pcie; @@ -1225,6 +1242,9 @@ static int mtk_pcie_probe(struct platform_device *pde= v) err_power_down_pcie: mtk_pcie_devices_power_down(pcie); mtk_pcie_power_down(pcie); +err_destroy_pwrctrl: + if (err !=3D -EPROBE_DEFER) + pci_pwrctrl_destroy_devices(pcie->dev); err_tear_down_irq: mtk_pcie_irq_teardown(pcie); return err; @@ -1240,7 +1260,9 @@ static void mtk_pcie_remove(struct platform_device *p= dev) pci_remove_root_bus(host->bus); pci_unlock_rescan_remove(); =20 + pci_pwrctrl_power_off_devices(pcie->dev); mtk_pcie_power_down(pcie); + pci_pwrctrl_destroy_devices(pcie->dev); mtk_pcie_irq_teardown(pcie); } =20 --=20 2.53.0.983.g0bb29b3bc5-goog