From nobody Fri Apr 3 16:00:25 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2EBB388E4E; Tue, 24 Mar 2026 02:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774321014; cv=none; b=riWidOJzo4uUrwoSfnsJ3aVSUGw4LShBkN/+K8q6kvKcLuFVTcTxgiijG2e4Bvd1v7A24yr1AcgIHiPQnmSwgeWFN75NOWP0lfUJhBqMu/B5GJ1yfuR58c+sntolxw8ND1/2MnhXNoQAhhcb+w91ja+V3yCJrdpXh5Mtp/p/wd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774321014; c=relaxed/simple; bh=iVybwPPMJxkW0F2npBOCFZ1DZK6j5vOiDvF/sjgpWA8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JHr7WDpvBILFp2FxwCzX75qOvVy4t0McJW01eIt4CwIDkDCpnB55Wc3pieGWQ4e0ZIo0vc/PsrpEo2OH8BiWvFx/qHfjjbk7CGOFjdhhAeY6/g7gFomYhzM4UWLV5XnNYPTyNIqNE2yhciixfsVuIs+YomE+6xvAM3aoqixMkT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=kQsb/OUY; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="kQsb/OUY" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 62O2rWVW1278451, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1774320812; bh=6XmEXoNvQpHnGXXW5vJRRUsAQOh6nBmLz22bOxzyt0Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=kQsb/OUYrG/ZFJfcLlp4jjeAeYGxIGiwiqYlhDLxXzsw3nj3rbzHx1BN9fDI0/ZcL 13gefIWbAvwCQE+D+n77sxJCQ8EJ+EKAthzNx/5FX02hMmXJbdhsZk7lG38GKtSNdc ixmTiOxnwI2nsLlfpL/s0WCIFivvvQjoGyczLjNmqBszzQIyhoPq6wZnGy3Otqg419 8KKlDcsR83DDptJinPGJyut85Eos4+xtAzI3QjvcDVmZgM6SaNERTeRqWV9fckmR7b s4makJc8UALpO1VDw47kJyxyMKwiqArt4KcHq88tjdoha32AtKrWGSMIgJhR2tRG7L Cmxsabc9sdtug== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 62O2rWVW1278451 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 24 Mar 2026 10:53:32 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:33 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:32 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:32 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 02/10] arm64: dts: realtek: Add clock support for RTD1625 Date: Tue, 24 Mar 2026 10:53:23 +0800 Message-ID: <20260324025332.3416977-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the clock controller nodes and osc27m fixed clock for the Realtek RTD1625 SoC. Signed-off-by: Yu-Chun Lin --- Changes in v5: - Reordered device nodes alphabetically. --- arch/arm64/boot/dts/realtek/kent.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi index ae006ce24420..3f3383872a49 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -26,6 +26,15 @@ timer { ; }; =20 + clocks { + osc27m: osc { + compatible =3D "fixed-clock"; + clock-frequency =3D <27000000>; + clock-output-names =3D "osc27m"; + #clock-cells =3D <0>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -141,6 +150,13 @@ rbus: bus@98000000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 + cc: clock-controller@0 { + compatible =3D "realtek,rtd1625-crt-clk"; + reg =3D <0x0 0x900>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + uart0: serial@7800 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x7800 0x100>; @@ -150,6 +166,20 @@ uart0: serial@7800 { reg-shift =3D <2>; status =3D "disabled"; }; + + ic: clock-controller@7088 { + compatible =3D "realtek,rtd1625-iso-clk"; + reg =3D <0x7088 0x8>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + iso_s_cc: clock-controller@146310 { + compatible =3D "realtek,rtd1625-iso-s-clk"; + reg =3D <0x146310 0x8>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; =20 gic: interrupt-controller@ff100000 { --=20 2.34.1