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+0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:32 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Date: Tue, 24 Mar 2026 10:53:22 +0800 Message-ID: <20260324025332.3416977-2-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DT binding schema for Realtek RTD1625 clock and reset controller Co-developed-by: Cheng-Yu Lee Signed-off-by: Cheng-Yu Lee Signed-off-by: Yu-Chun Lin Reviewed-by: Krzysztof Kozlowski --- Changes in v5: - Removed hardware bit position encoding from the reset binding and redesgi= ned reset IDs as sequential values. --- .../bindings/clock/realtek,rtd1625-clk.yaml | 52 ++++++ MAINTAINERS | 9 + .../dt-bindings/clock/realtek,rtd1625-clk.h | 164 +++++++++++++++++ include/dt-bindings/reset/realtek,rtd1625.h | 171 ++++++++++++++++++ 4 files changed, 396 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/realtek,rtd1625= -clk.yaml create mode 100644 include/dt-bindings/clock/realtek,rtd1625-clk.h create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h diff --git a/Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.ya= ml b/Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml new file mode 100644 index 000000000000..6fabc2da3975 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/realtek,rtd1625-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTD1625 Clock & Reset Controller + +maintainers: + - Yu-Chun Lin + +description: | + The Realtek RTD1625 Clock Controller manages and distributes clock + signals to various controllers and implements a Reset Controller for the + SoC peripherals. + + Clocks and resets are referenced by unique identifiers, which are define= d as + preprocessor macros in include/dt-bindings/clock/realtek,rtd1625-clk.h a= nd + include/dt-bindings/reset/realtek,rtd1625.h. + +properties: + compatible: + enum: + - realtek,rtd1625-crt-clk + - realtek,rtd1625-iso-clk + - realtek,rtd1625-iso-s-clk + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@98000000 { + compatible =3D "realtek,rtd1625-crt-clk"; + reg =3D <98000000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d7241695df96..721356d4c02c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22222,6 +22222,15 @@ S: Maintained F: Documentation/devicetree/bindings/net/dsa/realtek.yaml F: drivers/net/dsa/realtek/* =20 +REALTEK SOC CLOCK AND RESET DRIVERS +M: Cheng-Yu Lee +M: Yu-Chun Lin +L: devicetree@vger.kernel.org +L: linux-clk@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/clock/realtek* +F: include/dt-bindings/clock/realtek* + REALTEK SPI-NAND M: Chris Packham S: Maintained diff --git a/include/dt-bindings/clock/realtek,rtd1625-clk.h b/include/dt-b= indings/clock/realtek,rtd1625-clk.h new file mode 100644 index 000000000000..61ca652d6880 --- /dev/null +++ b/include/dt-bindings/clock/realtek,rtd1625-clk.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Realtek Semiconductor Corp. + */ +#ifndef __DT_BINDINGS_RTK_CLOCK_RTD1625_H +#define __DT_BINDINGS_RTK_CLOCK_RTD1625_H + +#define RTD1625_CRT_CLK_EN_MISC 0 +#define RTD1625_CRT_CLK_EN_PCIE0 1 +#define RTD1625_CRT_CLK_EN_DIP 2 +#define RTD1625_CRT_CLK_EN_GSPI 3 +#define RTD1625_CRT_CLK_EN_ISO_MISC 5 +#define RTD1625_CRT_CLK_EN_SDS 6 +#define RTD1625_CRT_CLK_EN_HDMI 7 +#define RTD1625_CRT_CLK_EN_GPU 9 +#define RTD1625_CRT_CLK_EN_VE1 10 +#define RTD1625_CRT_CLK_EN_VE2 11 +#define RTD1625_CRT_CLK_EN_MD 18 +#define RTD1625_CRT_CLK_EN_TP 19 +#define RTD1625_CRT_CLK_EN_RCIC 20 +#define RTD1625_CRT_CLK_EN_NF 21 +#define RTD1625_CRT_CLK_EN_EMMC 22 +#define RTD1625_CRT_CLK_EN_SD 23 +#define RTD1625_CRT_CLK_EN_SDIO_IP 24 +#define RTD1625_CRT_CLK_EN_MIPI_CSI 25 +#define RTD1625_CRT_CLK_EN_EMMC_IP 26 +#define RTD1625_CRT_CLK_EN_SDIO 27 +#define RTD1625_CRT_CLK_EN_SD_IP 28 +#define RTD1625_CRT_CLK_EN_TPB 30 +#define RTD1625_CRT_CLK_EN_MISC_SC1 31 +#define RTD1625_CRT_CLK_EN_MISC_I2C_3 32 +#define RTD1625_CRT_CLK_EN_ACPU 33 +#define RTD1625_CRT_CLK_EN_JPEG 34 +#define RTD1625_CRT_CLK_EN_MISC_SC0 37 +#define RTD1625_CRT_CLK_EN_HDMIRX 45 +#define RTD1625_CRT_CLK_EN_HSE 46 +#define RTD1625_CRT_CLK_EN_FAN 49 +#define RTD1625_CRT_CLK_EN_SATA_WRAP_SYS 52 +#define RTD1625_CRT_CLK_EN_SATA_WRAP_SYSH 53 +#define RTD1625_CRT_CLK_EN_SATA_MAC_SYSH 54 +#define RTD1625_CRT_CLK_EN_R2RDSC 55 +#define RTD1625_CRT_CLK_EN_TPC 56 +#define RTD1625_CRT_CLK_EN_PCIE1 57 +#define RTD1625_CRT_CLK_EN_MISC_I2C_4 58 +#define RTD1625_CRT_CLK_EN_MISC_I2C_5 59 +#define RTD1625_CRT_CLK_EN_TSIO 60 +#define RTD1625_CRT_CLK_EN_VE4 61 +#define RTD1625_CRT_CLK_EN_EDP 62 +#define RTD1625_CRT_CLK_EN_TSIO_TRX 63 +#define RTD1625_CRT_CLK_EN_PCIE2 64 +#define RTD1625_CRT_CLK_EN_EARC 66 +#define RTD1625_CRT_CLK_EN_LITE 67 +#define RTD1625_CRT_CLK_EN_MIPI_DSI 68 +#define RTD1625_CRT_CLK_EN_NPUPP 69 +#define RTD1625_CRT_CLK_EN_NPU 70 +#define RTD1625_CRT_CLK_EN_AUCPU0 71 +#define RTD1625_CRT_CLK_EN_AUCPU1 72 +#define RTD1625_CRT_CLK_EN_NSRAM 73 +#define RTD1625_CRT_CLK_EN_HDMITOP 74 +#define RTD1625_CRT_CLK_EN_AUCPU_ISO_NPU 76 +#define RTD1625_CRT_CLK_EN_KEYLADDER 77 +#define RTD1625_CRT_CLK_EN_IFCP_KLM 78 +#define RTD1625_CRT_CLK_EN_IFCP 79 +#define RTD1625_CRT_CLK_EN_MDL_GENPW 80 +#define RTD1625_CRT_CLK_EN_MDL_CHIP 81 +#define RTD1625_CRT_CLK_EN_MDL_IP 82 +#define RTD1625_CRT_CLK_EN_MDLM2M 83 +#define RTD1625_CRT_CLK_EN_MDL_XTAL 84 +#define RTD1625_CRT_CLK_EN_TEST_MUX 85 +#define RTD1625_CRT_CLK_EN_DLA 86 +#define RTD1625_CRT_CLK_EN_TPCW 88 +#define RTD1625_CRT_CLK_EN_GPU_TS_SRC 89 +#define RTD1625_CRT_CLK_EN_VI 91 +#define RTD1625_CRT_CLK_EN_LVDS1 92 +#define RTD1625_CRT_CLK_EN_LVDS2 93 +#define RTD1625_CRT_CLK_EN_AUCPU 94 +#define RTD1625_CRT_CLK_EN_UR1 96 +#define RTD1625_CRT_CLK_EN_UR2 97 +#define RTD1625_CRT_CLK_EN_UR3 98 +#define RTD1625_CRT_CLK_EN_UR4 99 +#define RTD1625_CRT_CLK_EN_UR5 100 +#define RTD1625_CRT_CLK_EN_UR6 101 +#define RTD1625_CRT_CLK_EN_UR7 102 +#define RTD1625_CRT_CLK_EN_UR8 103 +#define RTD1625_CRT_CLK_EN_UR9 104 +#define RTD1625_CRT_CLK_EN_UR_TOP 105 +#define RTD1625_CRT_CLK_EN_MISC_I2C_7 110 +#define RTD1625_CRT_CLK_EN_MISC_I2C_6 111 +#define RTD1625_CRT_CLK_EN_SPI0 112 +#define RTD1625_CRT_CLK_EN_SPI1 113 +#define RTD1625_CRT_CLK_EN_SPI2 114 +#define RTD1625_CRT_CLK_EN_LSADC0 120 +#define RTD1625_CRT_CLK_EN_LSADC1 121 +#define RTD1625_CRT_CLK_EN_ISOMIS_DMA 122 +#define RTD1625_CRT_CLK_EN_DPTX 124 +#define RTD1625_CRT_CLK_EN_NPU_MIPI_CSI 125 +#define RTD1625_CRT_CLK_EN_EDPTX 126 +#define RTD1625_CRT_CLK_HIFI 128 +#define RTD1625_CRT_CLK_NPU_MIPI_CSI 129 +#define RTD1625_CRT_CLK_NPU 130 +#define RTD1625_CRT_CLK_NPU_SYSH 132 +#define RTD1625_CRT_CLK_HIFI_SCPU 133 +#define RTD1625_CRT_CLK_GPU 134 +#define RTD1625_CRT_CLK_GPU2D 135 +#define RTD1625_CRT_CLK_MIPI_DSI_PCLK 136 +#define RTD1625_CRT_CLK_VE1 137 +#define RTD1625_CRT_CLK_VE2 138 +#define RTD1625_CRT_CLK_VE4 139 +#define RTD1625_CRT_CLK_SYS 141 +#define RTD1625_CRT_CLK_SYSH 142 +#define RTD1625_CRT_PLL_SDIO_REF 145 +#define RTD1625_CRT_PLL_CR_REF 146 +#define RTD1625_CRT_PLL_EMMC_REF 147 +#define RTD1625_CRT_CLK_MIS_SC0 148 +#define RTD1625_CRT_CLK_MIS_SC1 149 +#define RTD1625_CRT_PLL_SCPU 150 +#define RTD1625_CRT_PLL_VE1 151 +#define RTD1625_CRT_PLL_DDSA 152 +#define RTD1625_CRT_PLL_PSAUDA1 153 +#define RTD1625_CRT_PLL_PSAUDA2 154 +#define RTD1625_CRT_PLL_BUS 155 +#define RTD1625_CRT_PLL_SDIO 156 +#define RTD1625_CRT_PLL_SDIO_VP0 157 +#define RTD1625_CRT_PLL_SDIO_VP1 158 +#define RTD1625_CRT_PLL_DCSB 159 +#define RTD1625_CRT_PLL_GPU 160 +#define RTD1625_CRT_PLL_NPU 161 +#define RTD1625_CRT_PLL_VE2 162 +#define RTD1625_CRT_PLL_HIFI 163 +#define RTD1625_CRT_PLL_SD 164 +#define RTD1625_CRT_PLL_SD_VP0 165 +#define RTD1625_CRT_PLL_SD_VP1 166 +#define RTD1625_CRT_PLL_EMMC 167 +#define RTD1625_CRT_PLL_EMMC_VP0 168 +#define RTD1625_CRT_PLL_EMMC_VP1 169 +#define RTD1625_CRT_PLL_ACPU 170 +#define RTD1625_CRT_CLK_DET 171 + +#define RTD1625_ISO_CLK_EN_USB_P4 0 +#define RTD1625_ISO_CLK_EN_USB_P3 1 +#define RTD1625_ISO_CLK_EN_MISC_CEC0 2 +#define RTD1625_ISO_CLK_EN_CBUSRX_SYS 3 +#define RTD1625_ISO_CLK_EN_CBUSTX_SYS 4 +#define RTD1625_ISO_CLK_EN_CBUS_SYS 5 +#define RTD1625_ISO_CLK_EN_CBUS_OSC 6 +#define RTD1625_ISO_CLK_EN_MISC_UR0 8 +#define RTD1625_ISO_CLK_EN_I2C0 9 +#define RTD1625_ISO_CLK_EN_I2C1 10 +#define RTD1625_ISO_CLK_EN_ETN_250M 11 +#define RTD1625_ISO_CLK_EN_ETN_SYS 12 +#define RTD1625_ISO_CLK_EN_USB_DRD 13 +#define RTD1625_ISO_CLK_EN_USB_HOST 14 +#define RTD1625_ISO_CLK_EN_USB_U3_HOST 15 +#define RTD1625_ISO_CLK_EN_USB 16 +#define RTD1625_ISO_CLK_EN_VTC 17 +#define RTD1625_ISO_CLK_EN_MISC_VFD 18 + +#define RTD1625_ISO_S_CLK_EN_ISOM_MIS 0 +#define RTD1625_ISO_S_CLK_EN_ISOM_GPIOM 1 +#define RTD1625_ISO_S_CLK_EN_TIMER7 2 +#define RTD1625_ISO_S_CLK_EN_IRDA 3 +#define RTD1625_ISO_S_CLK_EN_UR10 4 + +#endif /* __DT_BINDINGS_RTK_CLOCK_RTD1625_H */ diff --git a/include/dt-bindings/reset/realtek,rtd1625.h b/include/dt-bindi= ngs/reset/realtek,rtd1625.h new file mode 100644 index 000000000000..31e7fa66ef31 --- /dev/null +++ b/include/dt-bindings/reset/realtek,rtd1625.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Realtek Semiconductor Corp. + */ + +#ifndef __DT_BINDINGS_RTK_RESET_RTD1625_H +#define __DT_BINDINGS_RTK_RESET_RTD1625_H + +#define RTD1625_CRT_RSTN_MISC 0 +#define RTD1625_CRT_RSTN_DIP 1 +#define RTD1625_CRT_RSTN_GSPI 2 +#define RTD1625_CRT_RSTN_SDS 3 +#define RTD1625_CRT_RSTN_SDS_REG 4 +#define RTD1625_CRT_RSTN_SDS_PHY 5 +#define RTD1625_CRT_RSTN_GPU2D 6 +#define RTD1625_CRT_RSTN_DC_PHY 7 +#define RTD1625_CRT_RSTN_DCPHY_CRT 8 +#define RTD1625_CRT_RSTN_LSADC 9 +#define RTD1625_CRT_RSTN_SE 10 +#define RTD1625_CRT_RSTN_DLA 11 +#define RTD1625_CRT_RSTN_JPEG 12 +#define RTD1625_CRT_RSTN_SD 13 +#define RTD1625_CRT_RSTN_SDIO 14 +#define RTD1625_CRT_RSTN_PCR_CNT 15 +#define RTD1625_CRT_RSTN_PCIE0_STITCH 16 +#define RTD1625_CRT_RSTN_PCIE0_PHY 17 +#define RTD1625_CRT_RSTN_PCIE0 18 +#define RTD1625_CRT_RSTN_PCIE0_CORE 19 +#define RTD1625_CRT_RSTN_PCIE0_POWER 20 +#define RTD1625_CRT_RSTN_PCIE0_NONSTICH 21 +#define RTD1625_CRT_RSTN_PCIE0_PHY_MDIO 22 +#define RTD1625_CRT_RSTN_PCIE0_SGMII_MDIO 23 +#define RTD1625_CRT_RSTN_VO2 24 +#define RTD1625_CRT_RSTN_MISC_SC0 25 +#define RTD1625_CRT_RSTN_MD 26 +#define RTD1625_CRT_RSTN_LVDS1 27 +#define RTD1625_CRT_RSTN_LVDS2 28 +#define RTD1625_CRT_RSTN_MISC_SC1 29 +#define RTD1625_CRT_RSTN_I2C_3 30 +#define RTD1625_CRT_RSTN_FAN 31 +#define RTD1625_CRT_RSTN_TVE 32 +#define RTD1625_CRT_RSTN_AIO 33 +#define RTD1625_CRT_RSTN_VO 34 +#define RTD1625_CRT_RSTN_MIPI_CSI 35 +#define RTD1625_CRT_RSTN_HDMIRX 36 +#define RTD1625_CRT_RSTN_HDMIRX_WRAP 37 +#define RTD1625_CRT_RSTN_HDMI 38 +#define RTD1625_CRT_RSTN_DISP 39 +#define RTD1625_CRT_RSTN_SATA_PHY_POW1 40 +#define RTD1625_CRT_RSTN_SATA_PHY_POW0 41 +#define RTD1625_CRT_RSTN_SATA_MDIO1 42 +#define RTD1625_CRT_RSTN_SATA_MDIO0 43 +#define RTD1625_CRT_RSTN_SATA_WRAP 44 +#define RTD1625_CRT_RSTN_SATA_MAC_P1 45 +#define RTD1625_CRT_RSTN_SATA_MAC_P0 46 +#define RTD1625_CRT_RSTN_SATA_MAC_COM 47 +#define RTD1625_CRT_RSTN_PCIE1_STITCH 48 +#define RTD1625_CRT_RSTN_PCIE1_PHY 49 +#define RTD1625_CRT_RSTN_PCIE1 50 +#define RTD1625_CRT_RSTN_PCIE1_CORE 51 +#define RTD1625_CRT_RSTN_PCIE1_POWER 52 +#define RTD1625_CRT_RSTN_PCIE1_NONSTICH 53 +#define RTD1625_CRT_RSTN_PCIE1_PHY_MDIO 54 +#define RTD1625_CRT_RSTN_HDMITOP 55 +#define RTD1625_CRT_RSTN_I2C_4 56 +#define RTD1625_CRT_RSTN_I2C_5 57 +#define RTD1625_CRT_RSTN_TSIO 58 +#define RTD1625_CRT_RSTN_VI 59 +#define RTD1625_CRT_RSTN_EDP 60 +#define RTD1625_CRT_RSTN_VE1_MMU 61 +#define RTD1625_CRT_RSTN_VE1_MMU_FUNC 62 +#define RTD1625_CRT_RSTN_HSE_MMU 63 +#define RTD1625_CRT_RSTN_HSE_MMU_FUNC 64 +#define RTD1625_CRT_RSTN_MDLM2M 65 +#define RTD1625_CRT_RSTN_ISO_GSPI 66 +#define RTD1625_CRT_RSTN_SOFT_NPU 67 +#define RTD1625_CRT_RSTN_SPI2EMMC 68 +#define RTD1625_CRT_RSTN_EARC 69 +#define RTD1625_CRT_RSTN_VE1 70 +#define RTD1625_CRT_RSTN_PCIE2_STITCH 71 +#define RTD1625_CRT_RSTN_PCIE2_PHY 72 +#define RTD1625_CRT_RSTN_PCIE2 73 +#define RTD1625_CRT_RSTN_PCIE2_CORE 74 +#define RTD1625_CRT_RSTN_PCIE2_POWER 75 +#define RTD1625_CRT_RSTN_PCIE2_NONSTICH 76 +#define RTD1625_CRT_RSTN_PCIE2_PHY_MDIO 77 +#define RTD1625_CRT_RSTN_DCPHY_UMCTL2 78 +#define RTD1625_CRT_RSTN_MIPI_DSI 79 +#define RTD1625_CRT_RSTN_HIFM 80 +#define RTD1625_CRT_RSTN_NSRAM 81 +#define RTD1625_CRT_RSTN_AUCPU0_REG 82 +#define RTD1625_CRT_RSTN_MDL_GENPW 83 +#define RTD1625_CRT_RSTN_MDL_CHIP 84 +#define RTD1625_CRT_RSTN_MDL_IP 85 +#define RTD1625_CRT_RSTN_TEST_MUX 86 +#define RTD1625_CRT_RSTN_ISO_BIST 87 +#define RTD1625_CRT_RSTN_MAIN_BIST 88 +#define RTD1625_CRT_RSTN_MAIN2_BIST 89 +#define RTD1625_CRT_RSTN_VE1_BIST 90 +#define RTD1625_CRT_RSTN_VE2_BIST 91 +#define RTD1625_CRT_RSTN_DCPHY_BIST 92 +#define RTD1625_CRT_RSTN_GPU_BIST 93 +#define RTD1625_CRT_RSTN_DISP_BIST 94 +#define RTD1625_CRT_RSTN_NPU_BIST 95 +#define RTD1625_CRT_RSTN_CAS_BIST 96 +#define RTD1625_CRT_RSTN_VE4_BIST 97 +#define RTD1625_CRT_RSTN_EMMC 98 +#define RTD1625_CRT_RSTN_GPU 99 +#define RTD1625_CRT_RSTN_VE2 100 +#define RTD1625_CRT_RSTN_UR1 101 +#define RTD1625_CRT_RSTN_UR2 102 +#define RTD1625_CRT_RSTN_UR3 103 +#define RTD1625_CRT_RSTN_UR4 104 +#define RTD1625_CRT_RSTN_UR5 105 +#define RTD1625_CRT_RSTN_UR6 106 +#define RTD1625_CRT_RSTN_UR7 107 +#define RTD1625_CRT_RSTN_UR8 108 +#define RTD1625_CRT_RSTN_UR9 109 +#define RTD1625_CRT_RSTN_UR_TOP 110 +#define RTD1625_CRT_RSTN_I2C_7 111 +#define RTD1625_CRT_RSTN_I2C_6 112 +#define RTD1625_CRT_RSTN_SPI0 113 +#define RTD1625_CRT_RSTN_SPI1 114 +#define RTD1625_CRT_RSTN_SPI2 115 +#define RTD1625_CRT_RSTN_LSADC0 116 +#define RTD1625_CRT_RSTN_LSADC1 117 +#define RTD1625_CRT_RSTN_ISOMIS_DMA 118 +#define RTD1625_CRT_RSTN_AUDIO_ADC 119 +#define RTD1625_CRT_RSTN_DPTX 120 +#define RTD1625_CRT_RSTN_AUCPU1_REG 121 +#define RTD1625_CRT_RSTN_EDPTX 122 + +/* ISO reset */ +#define RTD1625_ISO_RSTN_VFD 0 +#define RTD1625_ISO_RSTN_CEC0 1 +#define RTD1625_ISO_RSTN_CEC1 2 +#define RTD1625_ISO_RSTN_CBUSTX 3 +#define RTD1625_ISO_RSTN_CBUSRX 4 +#define RTD1625_ISO_RSTN_USB3_PHY2_XTAL_POW 5 +#define RTD1625_ISO_RSTN_UR0 6 +#define RTD1625_ISO_RSTN_GMAC 7 +#define RTD1625_ISO_RSTN_GPHY 8 +#define RTD1625_ISO_RSTN_I2C_0 9 +#define RTD1625_ISO_RSTN_I2C_1 10 +#define RTD1625_ISO_RSTN_CBUS 11 +#define RTD1625_ISO_RSTN_USB_DRD 12 +#define RTD1625_ISO_RSTN_USB_HOST 13 +#define RTD1625_ISO_RSTN_USB_PHY_0 14 +#define RTD1625_ISO_RSTN_USB_PHY_1 15 +#define RTD1625_ISO_RSTN_USB_PHY_2 16 +#define RTD1625_ISO_RSTN_USB 17 +#define RTD1625_ISO_RSTN_TYPE_C 18 +#define RTD1625_ISO_RSTN_USB_U3_HOST 19 +#define RTD1625_ISO_RSTN_USB3_PHY0_POW 20 +#define RTD1625_ISO_RSTN_USB3_P0_MDIO 21 +#define RTD1625_ISO_RSTN_USB3_PHY1_POW 22 +#define RTD1625_ISO_RSTN_USB3_P1_MDIO 23 +#define RTD1625_ISO_RSTN_VTC 24 +#define RTD1625_ISO_RSTN_USB3_PHY2_POW 25 +#define RTD1625_ISO_RSTN_USB3_P2_MDIO 26 +#define RTD1625_ISO_RSTN_USB_PHY_3 27 +#define RTD1625_ISO_RSTN_USB_PHY_4 28 + +/* ISO_S reset */ +#define RTD1625_ISO_S_RSTN_ISOM_MIS 0 +#define RTD1625_ISO_S_RSTN_GPIOM 1 +#define RTD1625_ISO_S_RSTN_TIMER7 2 +#define RTD1625_ISO_S_RSTN_IRDA 3 +#define RTD1625_ISO_S_RSTN_UR10 4 + +#endif /* __DT_BINDINGS_RTK_RESET_RTD1625_H */ --=20 2.34.1 From nobody Sun Apr 5 13:06:01 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2EBB388E4E; Tue, 24 Mar 2026 02:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774321014; cv=none; b=riWidOJzo4uUrwoSfnsJ3aVSUGw4LShBkN/+K8q6kvKcLuFVTcTxgiijG2e4Bvd1v7A24yr1AcgIHiPQnmSwgeWFN75NOWP0lfUJhBqMu/B5GJ1yfuR58c+sntolxw8ND1/2MnhXNoQAhhcb+w91ja+V3yCJrdpXh5Mtp/p/wd8= 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10:53:32 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:33 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:32 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:32 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 02/10] arm64: dts: realtek: Add clock support for RTD1625 Date: Tue, 24 Mar 2026 10:53:23 +0800 Message-ID: <20260324025332.3416977-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the clock controller nodes and osc27m fixed clock for the Realtek RTD1625 SoC. Signed-off-by: Yu-Chun Lin --- Changes in v5: - Reordered device nodes alphabetically. --- arch/arm64/boot/dts/realtek/kent.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi index ae006ce24420..3f3383872a49 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -26,6 +26,15 @@ timer { ; }; =20 + clocks { + osc27m: osc { + compatible =3D "fixed-clock"; + clock-frequency =3D <27000000>; + clock-output-names =3D "osc27m"; + #clock-cells =3D <0>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -141,6 +150,13 @@ rbus: bus@98000000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 + cc: clock-controller@0 { + compatible =3D "realtek,rtd1625-crt-clk"; + reg =3D <0x0 0x900>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + uart0: serial@7800 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x7800 0x100>; @@ -150,6 +166,20 @@ uart0: serial@7800 { reg-shift =3D <2>; status =3D "disabled"; }; + + ic: clock-controller@7088 { + compatible =3D "realtek,rtd1625-iso-clk"; + reg =3D <0x7088 0x8>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + iso_s_cc: clock-controller@146310 { + compatible =3D "realtek,rtd1625-iso-s-clk"; + reg =3D <0x146310 0x8>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; =20 gic: interrupt-controller@ff100000 { --=20 2.34.1 From nobody Sun Apr 5 13:06:01 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD967388E7A; Tue, 24 Mar 2026 02:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774321015; cv=none; b=t8UMxLFPbmTXm8H4vEDJHcwABFCD1ihbpXcA0d/8YOfv/NWq6F6T5h1koewBT3FGvKAc+CUqsAq87z6N3lpfMUUL5T6E+aoCDIs8FGQhl8lBSIB59Btt0WbuFlQHeXJ9N/UUBFD6xRsiV/gdpXuDzVayIMBtAUQDkteJ5cEGqfU= ARC-Message-Signature: i=1; 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Tue, 24 Mar 2026 10:53:33 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:33 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:33 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 03/10] reset: Add Realtek basic reset support Date: Tue, 24 Mar 2026 10:53:24 +0800 Message-ID: <20260324025332.3416977-4-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Define the reset operations backed by a regmap-based register interface and prepare the reset controller to be registered through the reset framework. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - Created drivers/reset/realtek/ directory and include/linux/reset/realtek.= h. - Extracted the common reset helpers: - Moved the source code to drivers/reset/realtek/common.c and - the header to include/linux/reset/realtek.h - Renamed rtk_reset_bank to rtk_reset_desc. - Added 'bits' member to rtk_reset_desc structure. - Removed rtk_reset_get_id() and rtk_reset_get_bank() helper. - Introduced rtk_reset_get_desc(). --- MAINTAINERS | 1 + drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/realtek/Kconfig | 3 ++ drivers/reset/realtek/Makefile | 2 + drivers/reset/realtek/common.c | 91 ++++++++++++++++++++++++++++++++++ include/linux/reset/realtek.h | 25 ++++++++++ 7 files changed, 124 insertions(+) create mode 100644 drivers/reset/realtek/Kconfig create mode 100644 drivers/reset/realtek/Makefile create mode 100644 drivers/reset/realtek/common.c create mode 100644 include/linux/reset/realtek.h diff --git a/MAINTAINERS b/MAINTAINERS index 721356d4c02c..9419b0497e0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22229,6 +22229,7 @@ L: devicetree@vger.kernel.org L: linux-clk@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/clock/realtek* +F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* =20 REALTEK SPI-NAND diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7ce151f6a7e4..03be1931f264 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -398,6 +398,7 @@ config RESET_ZYNQMP =20 source "drivers/reset/amlogic/Kconfig" source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/realtek/Kconfig" source "drivers/reset/spacemit/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index fc0cc99f8514..4407d1630070 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,6 +2,7 @@ obj-y +=3D core.o obj-y +=3D amlogic/ obj-y +=3D hisilicon/ +obj-y +=3D realtek/ obj-y +=3D spacemit/ obj-y +=3D starfive/ obj-y +=3D sti/ diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig new file mode 100644 index 000000000000..99a14d355803 --- /dev/null +++ b/drivers/reset/realtek/Kconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +config RESET_RTK_COMMON + bool diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile new file mode 100644 index 000000000000..b59a3f7f2453 --- /dev/null +++ b/drivers/reset/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RESET_RTK_COMMON) +=3D common.o diff --git a/drivers/reset/realtek/common.c b/drivers/reset/realtek/common.c new file mode 100644 index 000000000000..b9e3219dc8f7 --- /dev/null +++ b/drivers/reset/realtek/common.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include + +struct rtk_reset_data { + struct reset_controller_dev rcdev; + struct rtk_reset_desc *descs; + struct regmap *regmap; +}; + +static inline struct rtk_reset_data *to_rtk_reset_controller(struct reset_= controller_dev *r) +{ + return container_of(r, struct rtk_reset_data, rcdev); +} + +static inline struct rtk_reset_desc *rtk_reset_get_desc(struct rtk_reset_d= ata *data, + unsigned long idx) +{ + return &data->descs[idx]; +} + +static int rtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data =3D to_rtk_reset_controller(rcdev); + struct rtk_reset_desc *desc =3D rtk_reset_get_desc(data, idx); + u32 mask =3D desc->write_en ? (0x3 << desc->bit) : BIT(desc->bit); + u32 val =3D desc->write_en ? (0x2 << desc->bit) : 0; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data =3D to_rtk_reset_controller(rcdev); + struct rtk_reset_desc *desc =3D rtk_reset_get_desc(data, idx); + u32 mask =3D desc->write_en ? (0x3 << desc->bit) : BIT(desc->bit); + u32 val =3D mask; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_status(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data =3D to_rtk_reset_controller(rcdev); + struct rtk_reset_desc *desc =3D rtk_reset_get_desc(data, idx); + u32 val; + int ret; + + ret =3D regmap_read(data->regmap, desc->ofs, &val); + if (ret) + return ret; + + return !((val >> desc->bit) & 1); +} + +static const struct reset_control_ops rtk_reset_ops =3D { + .assert =3D rtk_reset_assert, + .deassert =3D rtk_reset_deassert, + .status =3D rtk_reset_status, +}; + +int rtk_reset_controller_add(struct device *dev, + struct rtk_reset_initdata *initdata) +{ + struct rtk_reset_data *data; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap =3D initdata->regmap; + data->descs =3D initdata->descs; + data->rcdev.owner =3D THIS_MODULE; + data->rcdev.ops =3D &rtk_reset_ops; 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charset="utf-8" From: Cheng-Yu Lee Add rtk_clk_probe() to set up the shared regmap, register clock hardware, add the clock provider, and optionally register a reset controller when reset bank data is provided. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - Synchronized with reset controller changes. --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/realtek/Kconfig | 28 +++++++++++++++++ drivers/clk/realtek/Makefile | 4 +++ drivers/clk/realtek/common.c | 59 ++++++++++++++++++++++++++++++++++++ drivers/clk/realtek/common.h | 43 ++++++++++++++++++++++++++ 7 files changed, 137 insertions(+) create mode 100644 drivers/clk/realtek/Kconfig create mode 100644 drivers/clk/realtek/Makefile create mode 100644 drivers/clk/realtek/common.c create mode 100644 drivers/clk/realtek/common.h diff --git a/MAINTAINERS b/MAINTAINERS index 9419b0497e0b..31f4a5a66394 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22229,6 +22229,7 @@ L: devicetree@vger.kernel.org L: linux-clk@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/clock/realtek* +F: drivers/clk/realtek/* F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* =20 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3d803b4cf5c1..d60f6415b0a3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -519,6 +519,7 @@ source "drivers/clk/nuvoton/Kconfig" source "drivers/clk/pistachio/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/ralink/Kconfig" +source "drivers/clk/realtek/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f7bce3951a30..69b84d1e7bcc 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -140,6 +140,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) +=3D pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) +=3D pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) +=3D qcom/ obj-y +=3D ralink/ +obj-$(CONFIG_COMMON_CLK_REALTEK) +=3D realtek/ obj-y +=3D renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) +=3D rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) +=3D samsung/ diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig new file mode 100644 index 000000000000..63eb3fb3e79a --- /dev/null +++ b/drivers/clk/realtek/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only +config COMMON_CLK_REALTEK + bool "Clock driver for Realtek SoCs" + depends on ARCH_REALTEK || COMPILE_TEST + default y + help + Enable the common clock framework infrastructure for Realtek + system-on-chip platforms. + + This provides the base support required by individual Realtek + clock controller drivers to expose clocks to peripheral devices. + + If you have a Realtek-based platform, say Y. + +if COMMON_CLK_REALTEK + +config RTK_CLK_COMMON + tristate "Realtek Clock Common" + depends on RESET_CONTROLLER + select RESET_RTK_COMMON + help + Common helper code shared by Realtek clock controller drivers. + + This provides utility functions and data structures used by + multiple Realtek clock implementations, and include integration + with reset controllers where required. + +endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile new file mode 100644 index 000000000000..377ec776ee47 --- /dev/null +++ b/drivers/clk/realtek/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RTK_CLK_COMMON) +=3D clk-rtk.o + +clk-rtk-y +=3D common.o diff --git a/drivers/clk/realtek/common.c b/drivers/clk/realtek/common.c new file mode 100644 index 000000000000..18a0d82ded0c --- /dev/null +++ b/drivers/clk/realtek/common.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include "common.h" + +int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc = *desc) +{ + int i, ret; + struct regmap *regmap; + struct device *dev =3D &pdev->dev; + struct rtk_reset_initdata reset_initdata =3D {0}; + + regmap =3D device_node_to_regmap(pdev->dev.of_node); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n"); + + for (i =3D 0; i < desc->num_clks; i++) + desc->clks[i]->regmap =3D regmap; + + for (i =3D 0; i < desc->clk_data->num; i++) { + struct clk_hw *hw =3D desc->clk_data->hws[i]; + + if (!hw) + continue; + + ret =3D devm_clk_hw_register(dev, hw); + + if (ret) { + dev_warn(dev, "failed to register hw of clk%d: %d\n", i, + ret); + desc->clk_data->hws[i] =3D NULL; + } + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + desc->clk_data); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + if (!desc->num_reset_descs) + return 0; + + reset_initdata.regmap =3D regmap; + reset_initdata.num_descs =3D desc->num_reset_descs; + reset_initdata.descs =3D desc->reset_descs; + + return rtk_reset_controller_add(dev, &reset_initdata); +} +EXPORT_SYMBOL_GPL(rtk_clk_probe); + +MODULE_DESCRIPTION("Realtek clock infrastructure"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/realtek/common.h b/drivers/clk/realtek/common.h new file mode 100644 index 000000000000..9cf013f9ba2b --- /dev/null +++ b/drivers/clk/realtek/common.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016-2019 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_COMMON_H +#define __CLK_REALTEK_COMMON_H + +#include +#include +#include +#include +#include +#include + +#define __clk_regmap_hw(_p) ((_p)->hw) + +struct device; +struct platform_device; + +struct clk_regmap { + struct clk_hw hw; + struct regmap *regmap; +}; + +struct rtk_clk_desc { + struct clk_hw_onecell_data *clk_data; + struct clk_regmap **clks; + size_t num_clks; + struct rtk_reset_desc *reset_descs; + size_t num_reset_descs; +}; + +static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) +{ + return container_of(hw, struct clk_regmap, hw); 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Tue, 24 Mar 2026 10:53:33 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:33 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 05/10] clk: realtek: Add support for phase locked loops (PLLs) Date: Tue, 24 Mar 2026 10:53:26 +0800 Message-ID: <20260324025332.3416977-6-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Provide a full set of PLL operations for programmable PLLs and a read-only variant for fixed or hardware-managed PLLs. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - None. --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-pll.c | 156 +++++++++++++++++++++++++++++++ drivers/clk/realtek/clk-pll.h | 47 ++++++++++ drivers/clk/realtek/freq_table.c | 35 +++++++ drivers/clk/realtek/freq_table.h | 23 +++++ 5 files changed, 263 insertions(+) create mode 100644 drivers/clk/realtek/clk-pll.c create mode 100644 drivers/clk/realtek/clk-pll.h create mode 100644 drivers/clk/realtek/freq_table.c create mode 100644 drivers/clk/realtek/freq_table.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 377ec776ee47..a89ad77993e9 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) +=3D clk-rtk.o =20 clk-rtk-y +=3D common.o +clk-rtk-y +=3D clk-pll.o +clk-rtk-y +=3D freq_table.o diff --git a/drivers/clk/realtek/clk-pll.c b/drivers/clk/realtek/clk-pll.c new file mode 100644 index 000000000000..6bb9084956b8 --- /dev/null +++ b/drivers/clk/realtek/clk-pll.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include "clk-pll.h" + +#define TIMEOUT 2000 + +static int wait_freq_ready(struct clk_pll *clkp) +{ + u32 pollval; + + if (!clkp->freq_ready_valid) + return 0; + + return regmap_read_poll_timeout_atomic(clkp->clkr.regmap, clkp->freq_read= y_reg, pollval, + (pollval & clkp->freq_ready_mask) + =3D=3D clkp->freq_ready_val, 0, TIMEOUT); +} + +static bool is_power_on(struct clk_pll *clkp) +{ + u32 val; + + if (!clkp->power_reg) + return true; + + if (regmap_read(clkp->clkr.regmap, clkp->power_reg, &val)) + return true; + + return (val & clkp->power_mask) =3D=3D clkp->power_val_on; +} + +static void clk_pll_disable(struct clk_hw *hw) +{ + struct clk_pll *clkp =3D to_clk_pll(hw); + + if (!clkp->seq_power_off) + return; + + regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_off, + clkp->num_seq_power_off); +} + +static int clk_pll_is_enabled(struct clk_hw *hw) +{ + struct clk_pll *clkp =3D to_clk_pll(hw); + + return is_power_on(clkp); +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_pll *clkp =3D to_clk_pll(hw); + const struct freq_table *ftblv =3D NULL; + + ftblv =3D ftbl_find_by_rate(clkp->freq_tbl, req->rate); + if (!ftblv) + return -EINVAL; + + req->rate =3D ftblv->rate; + return 0; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pll *clkp =3D to_clk_pll(hw); + const struct freq_table *fv; + u32 freq_val; + + if (regmap_read(clkp->clkr.regmap, clkp->freq_reg, &freq_val)) + return 0; + + freq_val &=3D clkp->freq_mask; + + fv =3D ftbl_find_by_val_with_mask(clkp->freq_tbl, clkp->freq_mask, + freq_val); + return fv ? fv->rate : 0; +} + +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_pll *clkp =3D to_clk_pll(hw); + const struct freq_table *fv; + int ret; + + fv =3D ftbl_find_by_rate(clkp->freq_tbl, rate); + if (!fv || fv->rate !=3D rate) + return -EINVAL; + + if (clkp->seq_pre_set_freq) { + ret =3D regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq, + clkp->num_seq_pre_set_freq); + if (ret) + return ret; + } + + ret =3D regmap_update_bits(clkp->clkr.regmap, clkp->freq_reg, + clkp->freq_mask, fv->val); + if (ret) + return ret; + + if (clkp->seq_post_set_freq) { + ret =3D regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_fre= q, + clkp->num_seq_post_set_freq); + if (ret) + return ret; + } + + if (is_power_on(clkp)) { + ret =3D wait_freq_ready(clkp); + if (ret) + return ret; + } + + return 0; +} + +static int clk_pll_enable(struct clk_hw *hw) +{ + struct clk_pll *clkp =3D to_clk_pll(hw); + int ret; + + if (!clkp->seq_power_on) + return 0; + + if (is_power_on(clkp)) + return 0; + + ret =3D regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_power_on, + clkp->num_seq_power_on); + if (ret) + return ret; + + return wait_freq_ready(clkp); +} + +const struct clk_ops rtk_clk_pll_ops =3D { + .enable =3D clk_pll_enable, + .disable =3D clk_pll_disable, + .is_enabled =3D clk_pll_is_enabled, + .recalc_rate =3D clk_pll_recalc_rate, + .determine_rate =3D clk_pll_determine_rate, + .set_rate =3D clk_pll_set_rate, +}; +EXPORT_SYMBOL_GPL(rtk_clk_pll_ops); + +const struct clk_ops rtk_clk_pll_ro_ops =3D { + .recalc_rate =3D clk_pll_recalc_rate, +}; +EXPORT_SYMBOL_GPL(rtk_clk_pll_ro_ops); diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h new file mode 100644 index 000000000000..2d27a44a270c --- /dev/null +++ b/drivers/clk/realtek/clk-pll.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2019 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_PLL_H +#define __CLK_REALTEK_CLK_PLL_H + +#include "common.h" +#include "freq_table.h" + +struct clk_pll { + struct clk_regmap clkr; + const struct reg_sequence *seq_power_on; + u32 num_seq_power_on; + const struct reg_sequence *seq_power_off; + u32 num_seq_power_off; + const struct reg_sequence *seq_pre_set_freq; + u32 num_seq_pre_set_freq; + const struct reg_sequence *seq_post_set_freq; + u32 num_seq_post_set_freq; + const struct freq_table *freq_tbl; + u32 freq_reg; + u32 freq_mask; + u32 freq_ready_valid; + u32 freq_ready_mask; + u32 freq_ready_reg; + u32 freq_ready_val; + u32 power_reg; + u32 power_mask; + u32 power_val_on; +}; + +#define __clk_pll_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr) + +static inline struct clk_pll *to_clk_pll(struct clk_hw *hw) +{ + struct clk_regmap *clkr =3D to_clk_regmap(hw); + + return container_of(clkr, struct clk_pll, clkr); +} + +extern const struct clk_ops rtk_clk_pll_ops; +extern const struct clk_ops rtk_clk_pll_ro_ops; + +#endif /* __CLK_REALTEK_CLK_PLL_H */ diff --git a/drivers/clk/realtek/freq_table.c b/drivers/clk/realtek/freq_ta= ble.c new file mode 100644 index 000000000000..26a0d2d3e851 --- /dev/null +++ b/drivers/clk/realtek/freq_table.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "freq_table.h" + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate) +{ + unsigned long best_rate =3D 0; + const struct freq_table *best =3D NULL; + + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if (ftbl->rate =3D=3D rate) + return ftbl; + + if (ftbl->rate > rate) + continue; + + if (ftbl->rate > best_rate) { + best_rate =3D ftbl->rate; + best =3D ftbl; + } + } + + return best; +} + +const struct freq_table * +ftbl_find_by_val_with_mask(const struct freq_table *ftbl, u32 mask, u32 va= lue) +{ + for (; !IS_FREQ_TABLE_END(ftbl); ftbl++) { + if ((ftbl->val & mask) =3D=3D (value & mask)) + return ftbl; + } + return NULL; +}; diff --git a/drivers/clk/realtek/freq_table.h b/drivers/clk/realtek/freq_ta= ble.h new file mode 100644 index 000000000000..383ae939fd1e --- /dev/null +++ b/drivers/clk/realtek/freq_table.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct freq_table { + u32 val; + unsigned long rate; +}; + +/* ofs check */ +#define CLK_OFS_INVALID -1 +#define CLK_OFS_IS_VALID(_ofs) ((_ofs) !=3D CLK_OFS_INVALID) + +#define FREQ_TABLE_END \ + { \ + .rate =3D 0 \ + } +#define IS_FREQ_TABLE_END(_f) ((_f)->rate =3D=3D 0) + +const struct freq_table *ftbl_find_by_rate(const struct freq_table *ftbl, + unsigned long rate); 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Tue, 24 Mar 2026 10:53:33 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 06/10] clk: realtek: Add support for gate clock Date: Tue, 24 Mar 2026 10:53:27 +0800 Message-ID: <20260324025332.3416977-7-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Introduce clk_regmap_gate_ops supporting enable, disable, is_enabled, and disable_unused for standard regmap gate clocks. Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - None. --- drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-regmap-gate.c | 66 +++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 65 ++++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index a89ad77993e9..74375f8127ac 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -2,5 +2,7 @@ obj-$(CONFIG_RTK_CLK_COMMON) +=3D clk-rtk.o =20 clk-rtk-y +=3D common.o + clk-rtk-y +=3D clk-pll.o +clk-rtk-y +=3D clk-regmap-gate.o clk-rtk-y +=3D freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/cl= k-regmap-gate.c new file mode 100644 index 000000000000..5174283c2c21 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include "clk-regmap-gate.h" + +static int clk_regmap_gate_enable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg =3D to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask =3D BIT(clkg->bit_idx); + val =3D BIT(clkg->bit_idx); + + if (clkg->write_en) { + mask |=3D BIT(clkg->bit_idx + 1); + val |=3D BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static void clk_regmap_gate_disable(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg =3D to_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask =3D BIT(clkg->bit_idx); + val =3D 0; + + if (clkg->write_en) { + mask |=3D BIT(clkg->bit_idx + 1); + val |=3D BIT(clkg->bit_idx + 1); + } + + regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap_gate *clkg =3D to_clk_regmap_gate(hw); + int ret; + u32 val; + + ret =3D regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops rtk_clk_regmap_gate_ops =3D { + .enable =3D clk_regmap_gate_enable, + .disable =3D clk_regmap_gate_disable, + .is_enabled =3D clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(rtk_clk_regmap_gate_ops); + +const struct clk_ops rtk_clk_regmap_gate_ro_ops =3D { + .is_enabled =3D clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(rtk_clk_regmap_gate_ro_ops); diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/cl= k-regmap-gate.h new file mode 100644 index 000000000000..b93357bd5a0d --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "common.h" + +struct clk_regmap_gate { + struct clk_regmap clkr; + int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __clk_regmap_gate_hw(_p) __clk_regmap_hw(&(_p)->clkr) + +#define __CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, = \ + _write_en) \ + struct clk_regmap_gate _name =3D { \ + .clkr.hw.init =3D CLK_HW_INIT(#_name, _parent, _ops, _flags), \ + .gate_ofs =3D _ofs, \ + .bit_idx =3D _bit_idx, \ + .write_en =3D _write_en, \ + } + +#define CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en)= \ + __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs,= \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_= en) \ + __CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, = \ + _ofs, _bit_idx, _write_en) + +#define __CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, = \ + _write_en) \ + struct clk_regmap_gate _name =3D { \ + .clkr.hw.init =3D CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ + .gate_ofs =3D _ofs, \ + .bit_idx =3D _bit_idx, \ + .write_en =3D _write_en, \ + } + +#define CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en= ) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs= , \ + _bit_idx, _write_en) + +#define CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write= _en) \ + __CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, = \ + _ofs, _bit_idx, _write_en) + +static inline struct clk_regmap_gate *to_clk_regmap_gate(struct clk_hw *hw) +{ + struct clk_regmap *clkr =3D to_clk_regmap(hw); + + return container_of(clkr, struct clk_regmap_gate, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_gate_ops; +extern const struct clk_ops rtk_clk_regmap_gate_ro_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ --=20 2.34.1 From nobody Sun Apr 5 13:06:01 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8308388E60; Tue, 24 Mar 2026 02:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774321014; cv=none; b=fW8hI+EMMVyoOsah0qYNtsKyhNxMEIOEIcKmAtWdyBxlQtB8qptFMGNEqbscXZDeRcfAOLXxLcH4DDVOqUa1uJxR6yKpPwHHAEjMtnrFpGAZRV9f3dSd1SH2Csl49r6u16h5zuob17hn6yqrUt2vbLFG2NSxeLwErD04mjPqvto= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774321014; 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Tue, 24 Mar 2026 10:53:34 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:34 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 07/10] clk: realtek: Add support for mux clock Date: Tue, 24 Mar 2026 10:53:28 +0800 Message-ID: <20260324025332.3416977-8-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Add a simple regmap-based clk_ops implementation for Realtek mux clocks. The implementation supports parent selection and rate determination through regmap-backed register access. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - None. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-mux.c | 46 ++++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-mux.h | 43 ++++++++++++++++++++++++++ 3 files changed, 90 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-mux.c create mode 100644 drivers/clk/realtek/clk-regmap-mux.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 74375f8127ac..f90dc57fcfdb 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -5,4 +5,5 @@ clk-rtk-y +=3D common.o =20 clk-rtk-y +=3D clk-pll.o clk-rtk-y +=3D clk-regmap-gate.o +clk-rtk-y +=3D clk-regmap-mux.o clk-rtk-y +=3D freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-mux.c b/drivers/clk/realtek/clk= -regmap-mux.c new file mode 100644 index 000000000000..d1612de2e2bc --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include "clk-regmap-mux.h" + +static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) +{ + struct clk_regmap_mux *clkm =3D to_clk_regmap_mux(hw); + int num_parents =3D clk_hw_get_num_parents(hw); + u32 val; + int ret; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->mux_ofs, &val); + if (ret) + return 0; + + val =3D val >> clkm->shift & clkm->mask; + + if (val >=3D num_parents) + return 0; + + return val; +} + +static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap_mux *clkm =3D to_clk_regmap_mux(hw); + + return regmap_update_bits(clkm->clkr.regmap, clkm->mux_ofs, + clkm->mask << clkm->shift, index << clkm->shift); +} + +const struct clk_ops rtk_clk_regmap_mux_ops =3D { + .set_parent =3D clk_regmap_mux_set_parent, + .get_parent =3D clk_regmap_mux_get_parent, + .determine_rate =3D __clk_mux_determine_rate, +}; +EXPORT_SYMBOL_GPL(rtk_clk_regmap_mux_ops); + +const struct clk_ops rtk_clk_regmap_mux_ro_ops =3D { + .get_parent =3D clk_regmap_mux_get_parent, +}; +EXPORT_SYMBOL_GPL(rtk_clk_regmap_mux_ro_ops); diff --git a/drivers/clk/realtek/clk-regmap-mux.h b/drivers/clk/realtek/clk= -regmap-mux.h new file mode 100644 index 000000000000..cf7ab6a0604c --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-mux.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_MUX_H +#define __CLK_REALTEK_CLK_REGMAP_MUX_H + +#include "common.h" + +struct clk_regmap_mux { + struct clk_regmap clkr; + int mux_ofs; + unsigned int mask; + unsigned int shift; +}; + +#define __clk_regmap_mux_hw(_p) __clk_regmap_hw(&(_p)->clkr) + +#define __CLK_REGMAP_MUX(_name, _parents, _ops, _flags, _ofs, _sft, _mask)= \ + struct clk_regmap_mux _name =3D { \ + .clkr.hw.init =3D \ + CLK_HW_INIT_PARENTS(#_name, _parents, _ops, _flags), \ + .mux_ofs =3D _ofs, \ + .shift =3D _sft, \ + .mask =3D _mask, \ + } + +#define CLK_REGMAP_MUX(_name, _parents, _flags, _ofs, _sft, _mask) = \ + __CLK_REGMAP_MUX(_name, _parents, &rtk_clk_regmap_mux_ops, _flags, _ofs, \ + _sft, _mask) + +static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw) +{ + struct clk_regmap *clkr =3D to_clk_regmap(hw); + + return container_of(clkr, struct clk_regmap_mux, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_mux_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_MUX_H */ --=20 2.34.1 From nobody Sun Apr 5 13:06:01 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E50EA3890EB; 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Tue, 24 Mar 2026 10:53:34 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:35 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:34 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:34 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 08/10] clk: realtek: Add support for MMC-tuned PLL clocks Date: Tue, 24 Mar 2026 10:53:29 +0800 Message-ID: <20260324025332.3416977-9-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Add clk_pll_mmc_ops for enable/disable, prepare, rate control, and status operations on MMC PLL clocks. Also add clk_pll_mmc_phase_ops to support phase get/set operations. Signed-off-by: Cheng-Yu Lee Co-developed-by: Jyan Chou Signed-off-by: Jyan Chou Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - None. --- MAINTAINERS | 8 + drivers/clk/realtek/Kconfig | 3 + drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-pll-mmc.c | 399 ++++++++++++++++++++++++++++++ drivers/clk/realtek/clk-pll.h | 21 ++ 5 files changed, 433 insertions(+) create mode 100644 drivers/clk/realtek/clk-pll-mmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 31f4a5a66394..074d7f33c32b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22233,6 +22233,14 @@ F: drivers/clk/realtek/* F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* =20 +REALTEK SOC PLL CLOCK FOR MMC SUPPORT +M: Cheng-Yu Lee +M: Jyan Chou +M: Yu-Chun Lin +L: linux-clk@vger.kernel.org +S: Supported +F: drivers/clk/realtek/clk-pll-mmc.c + REALTEK SPI-NAND M: Chris Packham S: Maintained diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig index 63eb3fb3e79a..5d790ce526ab 100644 --- a/drivers/clk/realtek/Kconfig +++ b/drivers/clk/realtek/Kconfig @@ -25,4 +25,7 @@ config RTK_CLK_COMMON multiple Realtek clock implementations, and include integration with reset controllers where required. =20 +config RTK_CLK_PLL_MMC + bool + endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index f90dc57fcfdb..fd7d777902c8 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -7,3 +7,5 @@ clk-rtk-y +=3D clk-pll.o clk-rtk-y +=3D clk-regmap-gate.o clk-rtk-y +=3D clk-regmap-mux.o clk-rtk-y +=3D freq_table.o + +clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) +=3D clk-pll-mmc.o diff --git a/drivers/clk/realtek/clk-pll-mmc.c b/drivers/clk/realtek/clk-pl= l-mmc.c new file mode 100644 index 000000000000..017663738c1f --- /dev/null +++ b/drivers/clk/realtek/clk-pll-mmc.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include "clk-pll.h" + +#define PLL_EMMC1_OFFSET 0x0 +#define PLL_EMMC2_OFFSET 0x4 +#define PLL_EMMC3_OFFSET 0x8 +#define PLL_EMMC4_OFFSET 0xc +#define PLL_SSC_DIG_EMMC1_OFFSET 0x0 +#define PLL_SSC_DIG_EMMC3_OFFSET 0xc +#define PLL_SSC_DIG_EMMC4_OFFSET 0x10 + +#define PLL_MMC_SSC_DIV_N_VAL 0x1b + +#define PLL_PHRT0_MASK BIT(1) +#define PLL_PHSEL_MASK GENMASK(4, 0) +#define PLL_SSCPLL_RS_MASK GENMASK(12, 10) +#define PLL_SSCPLL_ICP_MASK GENMASK(9, 5) +#define PLL_SSC_DIV_EXT_F_MASK GENMASK(25, 13) +#define PLL_PI_IBSELH_MASK GENMASK(28, 27) +#define PLL_SSC_DIV_N_MASK GENMASK(23, 16) +#define PLL_NCODE_SSC_EMMC_MASK GENMASK(20, 13) +#define PLL_FCODE_SSC_EMMC_MASK GENMASK(12, 0) +#define PLL_GRAN_EST_EM_MC_MASK GENMASK(20, 0) +#define PLL_EN_SSC_EMMC_MASK BIT(0) +#define PLL_FLAG_INITAL_EMMC_MASK BIT(1) + +#define PLL_PHRT0_SHIFT 1 +#define PLL_SSCPLL_RS_SHIFT 10 +#define PLL_SSCPLL_ICP_SHIFT 5 +#define PLL_SSC_DIV_EXT_F_SHIFT 13 +#define PLL_PI_IBSELH_SHIFT 27 +#define PLL_SSC_DIV_N_SHIFT 16 +#define PLL_NCODE_SSC_EMMC_SHIFT 13 +#define PLL_FLAG_INITAL_EMMC_SHIFT 8 + +#define CYCLE_DEGREES 360 +#define PHASE_STEPS 32 +#define PHASE_SCALE_FACTOR 1125 + +static inline int get_phrt0(struct clk_pll_mmc *clkm, u32 *val) +{ + u32 reg; + int ret; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, = ®); + if (ret) + return ret; + + *val =3D (reg >> PLL_PHRT0_SHIFT) & PLL_PHRT0_MASK; + return 0; +} + +static inline int set_phrt0(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OF= FSET, + PLL_PHRT0_MASK, val << PLL_PHRT0_SHIFT); +} + +static inline int get_phsel(struct clk_pll_mmc *clkm, int id, u32 *val) +{ + int ret; + u32 raw_val; + u32 sft =3D id ? 8 : 3; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, = &raw_val); + if (ret) + return ret; + + *val =3D (raw_val >> sft) & PLL_PHSEL_MASK; + return 0; +} + +static inline int set_phsel(struct clk_pll_mmc *clkm, int id, u32 val) +{ + u32 sft =3D id ? 8 : 3; + + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OF= FSET, + PLL_PHSEL_MASK << sft, val << sft); +} + +static inline int set_sscpll_rs(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_SSCPLL_RS_MASK, val << PLL_SSCPLL_RS_SHIFT); +} + +static inline int set_sscpll_icp(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_SSCPLL_ICP_MASK, val << PLL_SSCPLL_ICP_SHIFT); +} + +static inline int get_ssc_div_ext_f(struct clk_pll_mmc *clkm, u32 *val) +{ + u32 raw_val; + int ret; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OFFSET, = &raw_val); + if (ret) + return ret; + + *val =3D (raw_val & PLL_SSC_DIV_EXT_F_MASK) >> PLL_SSC_DIV_EXT_F_SHIFT; + return 0; +} + +static inline int set_ssc_div_ext_f(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_SSC_DIV_EXT_F_MASK, + val << PLL_SSC_DIV_EXT_F_SHIFT); +} + +static inline int set_pi_ibselh(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_PI_IBSELH_MASK, val << PLL_PI_IBSELH_SHIFT); +} + +static inline int set_ssc_div_n(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC3_OF= FSET, + PLL_SSC_DIV_N_MASK, val << PLL_SSC_DIV_N_SHIFT); +} + +static inline int get_ssc_div_n(struct clk_pll_mmc *clkm, u32 *val) +{ + int ret; + u32 raw_val; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC3_OFFSET, = &raw_val); + if (ret) + return ret; + + *val =3D (raw_val & PLL_SSC_DIV_N_MASK) >> PLL_SSC_DIV_N_SHIFT; + return 0; +} + +static inline int set_pow_ctl(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_write(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC4_OFFSET, = val); +} + +static inline int get_pow_ctl(struct clk_pll_mmc *clkm, u32 *val) +{ + int ret; + u32 raw_val; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC4_OFFSET, = &raw_val); + + *val =3D raw_val; + + return ret; +} + +static int clk_pll_mmc_phase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_hw *hwp =3D clk_hw_get_parent(hw); + struct clk_pll_mmc *clkm; + int phase_id; + u32 val; + int ret; + + if (!hwp) + return -ENOENT; + + clkm =3D to_clk_pll_mmc(hwp); + phase_id =3D (hw - &clkm->phase0_hw) ? 1 : 0; + val =3D DIV_ROUND_CLOSEST(degrees * 100, PHASE_SCALE_FACTOR); + ret =3D set_phsel(clkm, phase_id, val); + if (ret) + return ret; + + usleep_range(10, 20); + return 0; +} + +static int clk_pll_mmc_phase_get_phase(struct clk_hw *hw) +{ + struct clk_hw *hwp; + struct clk_pll_mmc *clkm; + int phase_id; + int ret; + u32 val; + + hwp =3D clk_hw_get_parent(hw); + if (!hwp) + return -ENOENT; + + clkm =3D to_clk_pll_mmc(hwp); + phase_id =3D (hw - &clkm->phase0_hw) ? 1 : 0; + ret =3D get_phsel(clkm, phase_id, &val); + if (ret) + return ret; + + val =3D DIV_ROUND_CLOSEST(val * CYCLE_DEGREES, PHASE_STEPS); + + return val; +} + +const struct clk_ops rtk_clk_pll_mmc_phase_ops =3D { + .set_phase =3D clk_pll_mmc_phase_set_phase, + .get_phase =3D clk_pll_mmc_phase_get_phase, +}; +EXPORT_SYMBOL_GPL(rtk_clk_pll_mmc_phase_ops); + +static int clk_pll_mmc_prepare(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + + return set_pow_ctl(clkm, 7); +} + +static void clk_pll_mmc_unprepare(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + + set_pow_ctl(clkm, 0); +} + +static int clk_pll_mmc_is_prepared(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val; + int ret; + + ret =3D get_pow_ctl(clkm, &val); + if (ret) + return 1; + + return val !=3D 0x0; +} + +static int clk_pll_mmc_enable(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + int ret; + + ret =3D set_phrt0(clkm, 1); + if (ret) + return ret; + + udelay(10); + return 0; +} + +static void clk_pll_mmc_disable(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + + set_phrt0(clkm, 0); + udelay(10); +} + +static int clk_pll_mmc_is_enabled(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val; + int ret; + + ret =3D get_phrt0(clkm, &val); + if (ret) + return 1; + + return val =3D=3D 0x1; +} + +static unsigned long clk_pll_mmc_recalc_rate(struct clk_hw *hw, unsigned l= ong parent_rate) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val, ext_f; + int ret; + + ret =3D get_ssc_div_n(clkm, &val); + if (ret) + return ret; + + ret =3D get_ssc_div_ext_f(clkm, &ext_f); + if (ret) + return ret; + + return parent_rate / 4 * (val + 2) + (parent_rate / 4 * ext_f) / 8192; +} + +static int clk_pll_mmc_determine_rate(struct clk_hw *hw, struct clk_rate_r= equest *req) +{ + u32 val =3D DIV_ROUND_CLOSEST(req->rate * 4, req->best_parent_rate); + + req->rate =3D req->best_parent_rate * val / 4; + return 0; +} + +static int clk_pll_mmc_set_rate(struct clk_hw *hw, unsigned long rate, uns= igned long parent_rate) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val =3D PLL_MMC_SSC_DIV_N_VAL; + int ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_FLAG_INITAL_EMMC_MASK, 0x0 << PLL_FLAG_INITAL_EMMC_SHIFT); + if (ret) + return ret; + + ret =3D set_ssc_div_n(clkm, val); + if (ret) + return ret; + + ret =3D set_ssc_div_ext_f(clkm, 1517); + if (ret) + return ret; + + switch (val) { + case 31 ... 46: + ret |=3D set_pi_ibselh(clkm, 3); + ret |=3D set_sscpll_rs(clkm, 3); + ret |=3D set_sscpll_icp(clkm, 2); + break; + + case 20 ... 30: + ret |=3D set_pi_ibselh(clkm, 2); + ret |=3D set_sscpll_rs(clkm, 3); + ret |=3D set_sscpll_icp(clkm, 1); + break; + + case 10 ... 19: + ret |=3D set_pi_ibselh(clkm, 1); + ret |=3D set_sscpll_rs(clkm, 2); + ret |=3D set_sscpll_icp(clkm, 1); + break; + + case 5 ... 9: + ret |=3D set_pi_ibselh(clkm, 0); + ret |=3D set_sscpll_rs(clkm, 2); + ret |=3D set_sscpll_icp(clkm, 0); + break; + } + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC3_OFFSET, + PLL_NCODE_SSC_EMMC_MASK, + 27 << PLL_NCODE_SSC_EMMC_SHIFT); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC3_OFFSET, + PLL_FCODE_SSC_EMMC_MASK, 321); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC4_OFFSET, + PLL_GRAN_EST_EM_MC_MASK, 5985); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_EN_SSC_EMMC_MASK, 0x1); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_EN_SSC_EMMC_MASK, 0x0); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_FLAG_INITAL_EMMC_MASK, + 0x1 << PLL_FLAG_INITAL_EMMC_SHIFT); + if (ret) + return ret; + + usleep_range(10, 20); + return 0; +} + +const struct clk_ops rtk_clk_pll_mmc_ops =3D { + .prepare =3D clk_pll_mmc_prepare, + .unprepare =3D clk_pll_mmc_unprepare, + .is_prepared =3D clk_pll_mmc_is_prepared, + .enable =3D clk_pll_mmc_enable, + .disable =3D clk_pll_mmc_disable, + .is_enabled =3D clk_pll_mmc_is_enabled, + .recalc_rate =3D clk_pll_mmc_recalc_rate, + .determine_rate =3D clk_pll_mmc_determine_rate, + .set_rate =3D clk_pll_mmc_set_rate, +}; +EXPORT_SYMBOL_GPL(rtk_clk_pll_mmc_ops); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h index 2d27a44a270c..9cf219871218 100644 --- a/drivers/clk/realtek/clk-pll.h +++ b/drivers/clk/realtek/clk-pll.h @@ -44,4 +44,25 @@ static inline struct clk_pll *to_clk_pll(struct clk_hw *= hw) extern const struct clk_ops rtk_clk_pll_ops; extern const struct clk_ops rtk_clk_pll_ro_ops; =20 +struct clk_pll_mmc { + struct clk_regmap clkr; + int pll_ofs; + int ssc_dig_ofs; + struct clk_hw phase0_hw; + struct clk_hw phase1_hw; + u32 set_rate_val_53_97_set_ipc: 1; +}; + +#define __clk_pll_mmc_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr) + +static inline struct clk_pll_mmc *to_clk_pll_mmc(struct clk_hw *hw) +{ + struct clk_regmap *clkr =3D to_clk_regmap(hw); + + return container_of(clkr, struct clk_pll_mmc, clkr); +} + +extern const struct clk_ops rtk_clk_pll_mmc_ops; +extern const struct clk_ops rtk_clk_pll_mmc_phase_ops; + #endif /* __CLK_REALTEK_CLK_PLL_H */ --=20 2.34.1 From nobody Sun Apr 5 13:06:01 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E8BD38A719; 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Tue, 24 Mar 2026 10:53:34 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:35 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:34 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 09/10] clk: realtek: Add RTD1625-CRT clock controller driver Date: Tue, 24 Mar 2026 10:53:30 +0800 Message-ID: <20260324025332.3416977-10-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Add support for the CRT (Clock, Reset, and Test) controller on the Realtek RTD1625 SoC. This driver provides clock and reset management for the system, allowing peripheral clients to request necessary resources for operation. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - Added '#include '. - Replaced rtk_reset_bank array with rtk_reset_desc descriptor. - Implemented complete a mapping table for all reset IDs. --- drivers/clk/realtek/Kconfig | 14 + drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-rtd1625-crt.c | 913 ++++++++++++++++++++++++++ 3 files changed, 928 insertions(+) create mode 100644 drivers/clk/realtek/clk-rtd1625-crt.c diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig index 5d790ce526ab..046f86af266d 100644 --- a/drivers/clk/realtek/Kconfig +++ b/drivers/clk/realtek/Kconfig @@ -28,4 +28,18 @@ config RTK_CLK_COMMON config RTK_CLK_PLL_MMC bool =20 +config COMMON_CLK_RTD1625 + tristate "RTD1625 Clock Controller" + select RTK_CLK_COMMON + select RTK_CLK_PLL_MMC + default y + help + Support for the clock controller on Realtek RTD1625 SoCs. + + This driver provides clock sources, gating, multiplexing, and + reset control for peripherals on the RTD1625 platform. + + Say Y here if your system is based on the RTD1625 and you need + its peripheral devices to function. + endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index fd7d777902c8..c992f97dfbc7 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -9,3 +9,4 @@ clk-rtk-y +=3D clk-regmap-mux.o clk-rtk-y +=3D freq_table.o =20 clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) +=3D clk-pll-mmc.o +obj-$(CONFIG_COMMON_CLK_RTD1625) +=3D clk-rtd1625-crt.o diff --git a/drivers/clk/realtek/clk-rtd1625-crt.c b/drivers/clk/realtek/cl= k-rtd1625-crt.c new file mode 100644 index 000000000000..a56978aef83a --- /dev/null +++ b/drivers/clk/realtek/clk-rtd1625-crt.c @@ -0,0 +1,913 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include "clk-pll.h" +#include "clk-regmap-gate.h" +#include "clk-regmap-mux.h" + +#define RTD1625_CRT_CLK_MAX 172 +#define RTD1625_CRT_RSTN_MAX 123 + +#define RTD1625_REG_PLL_ACPU1 0x10c +#define RTD1625_REG_PLL_ACPU2 0x110 +#define RTD1625_REG_PLL_SSC_DIG_ACPU0 0x5c0 +#define RTD1625_REG_PLL_SSC_DIG_ACPU1 0x5c4 +#define RTD1625_REG_PLL_SSC_DIG_ACPU2 0x5c8 +#define RTD1625_REG_PLL_SSC_DIG_ACPU_DBG2 0x5dc + +#define RTD1625_REG_PLL_VE1_1 0x114 +#define RTD1625_REG_PLL_VE1_2 0x118 +#define RTD1625_REG_PLL_SSC_DIG_VE1_0 0x580 +#define RTD1625_REG_PLL_SSC_DIG_VE1_1 0x584 +#define RTD1625_REG_PLL_SSC_DIG_VE1_2 0x588 +#define RTD1625_REG_PLL_SSC_DIG_VE1_DBG2 0x59c + +#define RTD1625_REG_PLL_GPU1 0x1c0 +#define RTD1625_REG_PLL_GPU2 0x1c4 +#define RTD1625_REG_PLL_SSC_DIG_GPU0 0x5a0 +#define RTD1625_REG_PLL_SSC_DIG_GPU1 0x5a4 +#define RTD1625_REG_PLL_SSC_DIG_GPU2 0x5a8 +#define RTD1625_REG_PLL_SSC_DIG_GPU_DBG2 0x5bc + +#define RTD1625_REG_PLL_NPU1 0x1c8 +#define RTD1625_REG_PLL_NPU2 0x1cc +#define RTD1625_REG_PLL_SSC_DIG_NPU0 0x800 +#define RTD1625_REG_PLL_SSC_DIG_NPU1 0x804 +#define RTD1625_REG_PLL_SSC_DIG_NPU2 0x808 +#define RTD1625_REG_PLL_SSC_DIG_NPU_DBG2 0x81c + +#define RTD1625_REG_PLL_VE2_1 0x1d0 +#define RTD1625_REG_PLL_VE2_2 0x1d4 +#define RTD1625_REG_PLL_SSC_DIG_VE2_0 0x5e0 +#define RTD1625_REG_PLL_SSC_DIG_VE2_1 0x5e4 +#define RTD1625_REG_PLL_SSC_DIG_VE2_2 0x5e8 +#define RTD1625_REG_PLL_SSC_DIG_VE2_DBG2 0x5fc + +#define RTD1625_REG_PLL_HIFI1 0x1d8 +#define RTD1625_REG_PLL_HIFI2 0x1dc +#define RTD1625_REG_PLL_SSC_DIG_HIFI0 0x6e0 +#define RTD1625_REG_PLL_SSC_DIG_HIFI1 0x6e4 +#define RTD1625_REG_PLL_SSC_DIG_HIFI2 0x6e8 +#define RTD1625_REG_PLL_SSC_DIG_HIFI_DBG2 0x6fc + +#define RTD1625_REG_PLL_BUS1 0x524 + +#define RTD1625_REG_PLL_SSC_DIG_DDSA1 0x564 + +#define RTD1625_REG_PLL_SSC_DIG_DCSB1 0x544 + +static const char * const clk_gpu_parents[] =3D {"pll_gpu", "clk_sys"}; +static CLK_REGMAP_MUX(clk_gpu, clk_gpu_parents, CLK_SET_RATE_PARENT | CLK_= SET_RATE_NO_REPARENT, + 0x28, 12, 0x1); +static const char * const clk_ve_parents[] =3D {"pll_vo", "clk_sysh", "pll= _ve1", "pll_ve2"}; +static CLK_REGMAP_MUX(clk_ve1, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_S= ET_RATE_NO_REPARENT, + 0x4c, 0, 0x3); +static CLK_REGMAP_MUX(clk_ve2, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_S= ET_RATE_NO_REPARENT, + 0x4c, 3, 0x3); +static CLK_REGMAP_MUX(clk_ve4, clk_ve_parents, CLK_SET_RATE_PARENT | CLK_S= ET_RATE_NO_REPARENT, + 0x4c, 6, 0x3); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_misc, CLK_IS_CRITICAL, 0x50, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie0, 0, 0x50, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_gspi, 0, 0x50, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_iso_misc, 0, 0x50, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sds, 0, 0x50, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmi, 0, 0x50, 14, 1); +static CLK_REGMAP_GATE(clk_en_gpu, "clk_gpu", CLK_SET_RATE_PARENT, 0x50, 1= 8, 1); +static CLK_REGMAP_GATE(clk_en_ve1, "clk_ve1", CLK_SET_RATE_PARENT, 0x50, 2= 0, 1); +static CLK_REGMAP_GATE(clk_en_ve2, "clk_ve2", CLK_SET_RATE_PARENT, 0x50, 2= 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_se, 0, 0x50, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_md, 0, 0x54, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tp, CLK_IS_CRITICAL, 0x54, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_rcic, 0, 0x54, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_nf, 0, 0x54, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_emmc, 0, 0x54, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sd, 0, 0x54, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sdio_ip, 0, 0x54, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mipi_csi, 0, 0x54, 18, 1); +static CLK_REGMAP_GATE(clk_en_emmc_ip, "pll_emmc", CLK_SET_RATE_PARENT, 0x= 54, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sdio, 0, 0x54, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sd_ip, 0, 0x54, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tpb, 0, 0x54, 28, 1); +static CLK_REGMAP_GATE(clk_en_misc_sc1, "clk_en_misc", 0, 0x54, 30, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_3, "clk_en_misc", 0, 0x58, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_jpeg, 0, 0x58, 4, 1); +static CLK_REGMAP_GATE(clk_en_acpu, "pll_acpu", CLK_SET_RATE_PARENT, + 0x58, 6, 1); +static CLK_REGMAP_GATE(clk_en_misc_sc0, "clk_en_misc", 0, 0x58, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmirx, 0, 0x58, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hse, CLK_IS_CRITICAL, 0x58, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_fan, 0, 0x5c, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_wrap_sys, 0, 0x5c, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_wrap_sysh, 0, 0x5c, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_sata_mac_sysh, 0, 0x5c, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_r2rdsc, 0, 0x5c, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie1, 0, 0x5c, 18, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_4, "clk_en_misc", 0, 0x5c, 20, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_5, "clk_en_misc", 0, 0x5c, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tsio, 0, 0x5c, 24, 1); +static CLK_REGMAP_GATE(clk_en_ve4, "clk_ve4", CLK_SET_RATE_PARENT, + 0x5c, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_edp, 0, 0x5c, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tsio_trx, 0, 0x5c, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_pcie2, 0, 0x8c, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_earc, 0, 0x8c, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lite, 0, 0x8c, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mipi_dsi, 0, 0x8c, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npupp, 0, 0x8c, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npu, 0, 0x8c, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu0, 0, 0x8c, 14, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu1, 0, 0x8c, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_nsram, 0, 0x8c, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_hdmitop, 0, 0x8c, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu_iso_npu, 0, 0x8c, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_keyladder, 0, 0x8c, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ifcp_klm, 0, 0x8c, 28, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ifcp, 0, 0x8c, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_genpw, 0, 0xb0, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_chip, 0, 0xb0, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_ip, 0, 0xb0, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdlm2m, 0, 0xb0, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_mdl_xtal, 0, 0xb0, 8, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_test_mux, 0, 0xb0, 10, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_dla, 0, 0xb0, 12, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_tpcw, 0, 0xb0, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_gpu_ts_src, 0, 0xb0, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_vi, 0, 0xb0, 22, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lvds1, 0, 0xb0, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lvds2, 0, 0xb0, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_aucpu, 0, 0xb0, 28, 1); +static CLK_REGMAP_GATE(clk_en_ur1, "clk_en_ur_top", 0, 0x884, 0, 1); +static CLK_REGMAP_GATE(clk_en_ur2, "clk_en_ur_top", 0, 0x884, 2, 1); +static CLK_REGMAP_GATE(clk_en_ur3, "clk_en_ur_top", 0, 0x884, 4, 1); +static CLK_REGMAP_GATE(clk_en_ur4, "clk_en_ur_top", 0, 0x884, 6, 1); +static CLK_REGMAP_GATE(clk_en_ur5, "clk_en_ur_top", 0, 0x884, 8, 1); +static CLK_REGMAP_GATE(clk_en_ur6, "clk_en_ur_top", 0, 0x884, 10, 1); +static CLK_REGMAP_GATE(clk_en_ur7, "clk_en_ur_top", 0, 0x884, 12, 1); +static CLK_REGMAP_GATE(clk_en_ur8, "clk_en_ur_top", 0, 0x884, 14, 1); +static CLK_REGMAP_GATE(clk_en_ur9, "clk_en_ur_top", 0, 0x884, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ur_top, CLK_IS_CRITICAL, 0x884, 18= , 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_7, "clk_en_misc", 0, 0x884, 28, 1); +static CLK_REGMAP_GATE(clk_en_misc_i2c_6, "clk_en_misc", 0, 0x884, 30, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi0, 0, 0x894, 0, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi1, 0, 0x894, 2, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_spi2, 0, 0x894, 4, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lsadc0, 0, 0x894, 16, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_lsadc1, 0, 0x894, 18, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_isomis_dma, 0, 0x894, 20, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_dptx, 0, 0x894, 24, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_npu_mipi_csi, 0, 0x894, 26, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_edptx, 0, 0x894, 28, 1); + +#define FREQ_NF_MASK 0x7ffff +#define FREQ_NF(_r, _nf) {.rate =3D _r, .val =3D (_nf),} + +static const struct freq_table acpu_tbl[] =3D { + FREQ_NF(513000000, 0x11000), + FREQ_TABLE_END +}; + +static const struct freq_table ve_tbl[] =3D { + FREQ_NF(553500000, 0x12800), + FREQ_NF(661500000, 0x16800), + FREQ_NF(688500000, 0x17800), + FREQ_TABLE_END +}; + +static const struct freq_table bus_tbl[] =3D { + FREQ_NF(513000000, 0x11000), + FREQ_NF(540000000, 0x12000), + FREQ_NF(553500000, 0x12800), + FREQ_TABLE_END +}; + +static const struct freq_table ddsa_tbl[] =3D { + FREQ_NF(432000000, 0xe000), + FREQ_TABLE_END +}; + +static const struct freq_table gpu_tbl[] =3D { + FREQ_NF(405000000, 0xd000), + FREQ_NF(540000000, 0x12000), + FREQ_NF(661500000, 0x16800), + FREQ_NF(729000000, 0x19000), + FREQ_NF(810000000, 0x1c000), + FREQ_NF(850500000, 0x1d800), + FREQ_TABLE_END +}; + +static const struct freq_table hifi_tbl[] =3D { + FREQ_NF(756000000, 0x1a000), + FREQ_NF(810000000, 0x1c000), + FREQ_TABLE_END +}; + +static const struct freq_table npu_tbl[] =3D { + FREQ_NF(661500000, 0x16800), + FREQ_NF(729000000, 0x19000), + FREQ_NF(810000000, 0x1c000), + FREQ_TABLE_END +}; + +static const struct reg_sequence pll_acpu_seq_power_on[] =3D { + {RTD1625_REG_PLL_ACPU2, 0x5}, + {RTD1625_REG_PLL_ACPU2, 0x7}, + {RTD1625_REG_PLL_ACPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_ACPU2, 0x1e1f8e}, + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x5, 200}, + {RTD1625_REG_PLL_ACPU2, 0x3}, +}; + +static const struct reg_sequence pll_acpu_seq_power_off[] =3D { + {RTD1625_REG_PLL_ACPU2, 0x4}, +}; + +static const struct reg_sequence pll_acpu_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x4}, +}; + +static const struct reg_sequence pll_acpu_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_ACPU0, 0x5}, +}; + +static struct clk_pll pll_acpu =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_acpu", "osc27m", &rtk_clk_pll_ops, CLK= _GET_RATE_NOCACHE), + .seq_power_on =3D pll_acpu_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_acpu_seq_power_on), + .seq_power_off =3D pll_acpu_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_acpu_seq_power_off), + .seq_pre_set_freq =3D pll_acpu_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_acpu_seq_pre_set_freq), + .seq_post_set_freq =3D pll_acpu_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_acpu_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_ACPU1, + .freq_tbl =3D acpu_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_ACPU_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_ACPU2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static const struct reg_sequence pll_ve1_seq_power_on[] =3D { + {RTD1625_REG_PLL_VE1_2, 0x5}, + {RTD1625_REG_PLL_VE1_2, 0x7}, + {RTD1625_REG_PLL_VE1_1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x5, 200}, + {RTD1625_REG_PLL_VE1_2, 0x3}, +}; + +static const struct reg_sequence pll_ve1_seq_power_off[] =3D { + {RTD1625_REG_PLL_VE1_2, 0x4}, +}; + +static const struct reg_sequence pll_ve1_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x4}, +}; + +static const struct reg_sequence pll_ve1_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE1_0, 0x5}, +}; + +static struct clk_pll pll_ve1 =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_ve1", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_ve1_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_ve1_seq_power_on), + .seq_power_off =3D pll_ve1_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_ve1_seq_power_off), + .seq_pre_set_freq =3D pll_ve1_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_ve1_seq_pre_set_freq), + .seq_post_set_freq =3D pll_ve1_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_ve1_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_VE1_1, + .freq_tbl =3D ve_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_VE1_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_VE1_2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static struct clk_pll pll_ddsa =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_ddsa", "osc27m", &rtk_clk_pll_ro_ops, + CLK_GET_RATE_NOCACHE), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_DDSA1, + .freq_tbl =3D ddsa_tbl, + .freq_mask =3D FREQ_NF_MASK, +}; + +static struct clk_pll pll_bus =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_bus", "osc27m", &rtk_clk_pll_ro_ops, C= LK_GET_RATE_NOCACHE), + .freq_reg =3D RTD1625_REG_PLL_BUS1, + .freq_tbl =3D bus_tbl, + .freq_mask =3D FREQ_NF_MASK, +}; + +static CLK_FIXED_FACTOR(clk_sys, "clk_sys", "pll_bus", 2, 1, 0); + +static struct clk_pll pll_dcsb =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_dcsb", "osc27m", &rtk_clk_pll_ro_ops, + CLK_GET_RATE_NOCACHE), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_DCSB1, + .freq_tbl =3D bus_tbl, + .freq_mask =3D FREQ_NF_MASK, +}; + +static CLK_FIXED_FACTOR(clk_sysh, "clk_sysh", "pll_dcsb", 1, 1, 0); + +static const struct reg_sequence pll_gpu_seq_power_on[] =3D { + {RTD1625_REG_PLL_GPU2, 0x5}, + {RTD1625_REG_PLL_GPU2, 0x7}, + {RTD1625_REG_PLL_GPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x5, 200}, + {RTD1625_REG_PLL_GPU2, 0x3}, +}; + +static const struct reg_sequence pll_gpu_seq_power_off[] =3D { + {RTD1625_REG_PLL_GPU2, 0x4}, +}; + +static const struct reg_sequence pll_gpu_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x4}, +}; + +static const struct reg_sequence pll_gpu_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_GPU0, 0x5}, +}; + +static struct clk_pll pll_gpu =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_gpu", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_gpu_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_gpu_seq_power_on), + .seq_power_off =3D pll_gpu_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_gpu_seq_power_off), + .seq_pre_set_freq =3D pll_gpu_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_gpu_seq_pre_set_freq), + .seq_post_set_freq =3D pll_gpu_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_gpu_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_GPU1, + .freq_tbl =3D gpu_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_GPU_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_GPU2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static const struct reg_sequence pll_npu_seq_power_on[] =3D { + {RTD1625_REG_PLL_NPU2, 0x5}, + {RTD1625_REG_PLL_NPU2, 0x7}, + {RTD1625_REG_PLL_NPU1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x5, 200}, + {RTD1625_REG_PLL_NPU2, 0x3}, +}; + +static const struct reg_sequence pll_npu_seq_power_off[] =3D { + {RTD1625_REG_PLL_NPU2, 0x4}, + {RTD1625_REG_PLL_NPU1, 0x54010}, +}; + +static const struct reg_sequence pll_npu_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x4}, +}; + +static const struct reg_sequence pll_npu_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_NPU0, 0x5}, +}; + +static struct clk_pll pll_npu =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_npu", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_npu_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_npu_seq_power_on), + .seq_power_off =3D pll_npu_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_npu_seq_power_off), + .seq_pre_set_freq =3D pll_npu_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_npu_seq_pre_set_freq), + .seq_post_set_freq =3D pll_npu_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_npu_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_NPU1, + .freq_tbl =3D npu_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_NPU_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_NPU2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static CLK_FIXED_FACTOR(clk_npu, "clk_npu", "pll_npu", 1, 1, CLK_SET_RATE_= PARENT); +static CLK_FIXED_FACTOR(clk_npu_mipi_csi, "clk_npu_mipi_csi", "pll_npu", 1= , 1, + CLK_SET_RATE_PARENT); + +static const struct reg_sequence pll_ve2_seq_power_on[] =3D { + {RTD1625_REG_PLL_VE2_2, 0x5}, + {RTD1625_REG_PLL_VE2_2, 0x7}, + {RTD1625_REG_PLL_VE2_1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x5, 200}, + {RTD1625_REG_PLL_VE2_2, 0x3}, +}; + +static const struct reg_sequence pll_ve2_seq_power_off[] =3D { + {RTD1625_REG_PLL_VE2_2, 0x4}, +}; + +static const struct reg_sequence pll_ve2_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x4}, +}; + +static const struct reg_sequence pll_ve2_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_VE2_0, 0x5}, +}; + +static struct clk_pll pll_ve2 =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_ve2", "osc27m", &rtk_clk_pll_ops, CLK_= GET_RATE_NOCACHE), + .seq_power_on =3D pll_ve2_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_ve2_seq_power_on), + .seq_power_off =3D pll_ve2_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_ve2_seq_power_off), + .seq_pre_set_freq =3D pll_ve2_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_ve2_seq_pre_set_freq), + .seq_post_set_freq =3D pll_ve2_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_ve2_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_VE2_1, + .freq_tbl =3D ve_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_VE2_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_VE2_2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static const struct reg_sequence pll_hifi_seq_power_on[] =3D { + {RTD1625_REG_PLL_HIFI2, 0x5}, + {RTD1625_REG_PLL_HIFI2, 0x7}, + {RTD1625_REG_PLL_HIFI1, 0x54000}, + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x4}, + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x5, 200}, + {RTD1625_REG_PLL_HIFI2, 0x3}, +}; + +static const struct reg_sequence pll_hifi_seq_power_off[] =3D { + {RTD1625_REG_PLL_HIFI2, 0x4}, +}; + +static const struct reg_sequence pll_hifi_seq_pre_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x4}, +}; + +static const struct reg_sequence pll_hifi_seq_post_set_freq[] =3D { + {RTD1625_REG_PLL_SSC_DIG_HIFI0, 0x5}, +}; + +static struct clk_pll pll_hifi =3D { + .clkr.hw.init =3D CLK_HW_INIT("pll_hifi", "osc27m", &rtk_clk_pll_ops, CLK= _GET_RATE_NOCACHE), + .seq_power_on =3D pll_hifi_seq_power_on, + .num_seq_power_on =3D ARRAY_SIZE(pll_hifi_seq_power_on), + .seq_power_off =3D pll_hifi_seq_power_off, + .num_seq_power_off =3D ARRAY_SIZE(pll_hifi_seq_power_off), + .seq_pre_set_freq =3D pll_hifi_seq_pre_set_freq, + .num_seq_pre_set_freq =3D ARRAY_SIZE(pll_hifi_seq_pre_set_freq), + .seq_post_set_freq =3D pll_hifi_seq_post_set_freq, + .num_seq_post_set_freq =3D ARRAY_SIZE(pll_hifi_seq_post_set_freq), + .freq_reg =3D RTD1625_REG_PLL_SSC_DIG_HIFI1, + .freq_tbl =3D hifi_tbl, + .freq_mask =3D FREQ_NF_MASK, + .freq_ready_reg =3D RTD1625_REG_PLL_SSC_DIG_HIFI_DBG2, + .freq_ready_mask =3D BIT(20), + .freq_ready_val =3D BIT(20), + .power_reg =3D RTD1625_REG_PLL_HIFI2, + .power_mask =3D 0x7, + .power_val_on =3D 0x3, +}; + +static CLK_FIXED_FACTOR(pll_emmc_ref, "pll_emmc_ref", "osc27m", 1, 1, 0); + +static struct clk_pll_mmc pll_emmc =3D { + .pll_ofs =3D 0x1f0, + .ssc_dig_ofs =3D 0x6b0, + .clkr.hw.init =3D CLK_HW_INIT("pll_emmc", "pll_emmc_ref", &rtk_clk_pll_= mmc_ops, 0), + .phase0_hw.init =3D CLK_HW_INIT("pll_emmc_vp0", "pll_emmc", &rtk_clk_pll_= mmc_phase_ops, 0), + .phase1_hw.init =3D CLK_HW_INIT("pll_emmc_vp1", "pll_emmc", &rtk_clk_pll_= mmc_phase_ops, 0), +}; + +static struct clk_regmap *rtd1625_crt_regmap_clks[] =3D { + &clk_en_misc.clkr, + &clk_en_pcie0.clkr, + &clk_en_gspi.clkr, + &clk_en_iso_misc.clkr, + &clk_en_sds.clkr, + &clk_en_hdmi.clkr, + &clk_en_gpu.clkr, + &clk_en_ve1.clkr, + &clk_en_ve2.clkr, + &clk_en_se.clkr, + &clk_en_md.clkr, + &clk_en_tp.clkr, + &clk_en_rcic.clkr, + &clk_en_nf.clkr, + &clk_en_emmc.clkr, + &clk_en_sd.clkr, + &clk_en_sdio_ip.clkr, + &clk_en_mipi_csi.clkr, + &clk_en_emmc_ip.clkr, + &clk_en_sdio.clkr, + &clk_en_sd_ip.clkr, + &clk_en_tpb.clkr, + &clk_en_misc_sc1.clkr, + &clk_en_misc_i2c_3.clkr, + &clk_en_jpeg.clkr, + &clk_en_acpu.clkr, + &clk_en_misc_sc0.clkr, + &clk_en_hdmirx.clkr, + &clk_en_hse.clkr, + &clk_en_fan.clkr, + &clk_en_sata_wrap_sys.clkr, + &clk_en_sata_wrap_sysh.clkr, + &clk_en_sata_mac_sysh.clkr, + &clk_en_r2rdsc.clkr, + &clk_en_pcie1.clkr, + &clk_en_misc_i2c_4.clkr, + &clk_en_misc_i2c_5.clkr, + &clk_en_tsio.clkr, + &clk_en_ve4.clkr, + &clk_en_edp.clkr, + &clk_en_tsio_trx.clkr, + &clk_en_pcie2.clkr, + &clk_en_earc.clkr, + &clk_en_lite.clkr, + &clk_en_mipi_dsi.clkr, + &clk_en_npupp.clkr, + &clk_en_npu.clkr, + &clk_en_aucpu0.clkr, + &clk_en_aucpu1.clkr, + &clk_en_nsram.clkr, + &clk_en_hdmitop.clkr, + &clk_en_aucpu_iso_npu.clkr, + &clk_en_keyladder.clkr, + &clk_en_ifcp_klm.clkr, + &clk_en_ifcp.clkr, + &clk_en_mdl_genpw.clkr, + &clk_en_mdl_chip.clkr, + &clk_en_mdl_ip.clkr, + &clk_en_mdlm2m.clkr, + &clk_en_mdl_xtal.clkr, + &clk_en_test_mux.clkr, + &clk_en_dla.clkr, + &clk_en_tpcw.clkr, + &clk_en_gpu_ts_src.clkr, + &clk_en_vi.clkr, + &clk_en_lvds1.clkr, + &clk_en_lvds2.clkr, + &clk_en_aucpu.clkr, + &clk_en_ur1.clkr, + &clk_en_ur2.clkr, + &clk_en_ur3.clkr, + &clk_en_ur4.clkr, + &clk_en_ur5.clkr, + &clk_en_ur6.clkr, + &clk_en_ur7.clkr, + &clk_en_ur8.clkr, + &clk_en_ur9.clkr, + &clk_en_ur_top.clkr, + &clk_en_misc_i2c_7.clkr, + &clk_en_misc_i2c_6.clkr, + &clk_en_spi0.clkr, + &clk_en_spi1.clkr, + &clk_en_spi2.clkr, + &clk_en_lsadc0.clkr, + &clk_en_lsadc1.clkr, + &clk_en_isomis_dma.clkr, + &clk_en_dptx.clkr, + &clk_en_npu_mipi_csi.clkr, + &clk_en_edptx.clkr, + &clk_gpu.clkr, + &clk_ve1.clkr, + &clk_ve2.clkr, + &clk_ve4.clkr, + &pll_ve1.clkr, + &pll_ddsa.clkr, + &pll_bus.clkr, + &pll_dcsb.clkr, + &pll_gpu.clkr, + &pll_npu.clkr, + &pll_ve2.clkr, + &pll_hifi.clkr, + &pll_emmc.clkr, + &pll_acpu.clkr, +}; + +static struct rtk_reset_desc rtd1625_crt_reset_descs[] =3D { + /* Bank 0: offset 0x0 */ + [RTD1625_CRT_RSTN_MISC] =3D { .ofs =3D 0x0, .bit =3D 0, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DIP] =3D { .ofs =3D 0x0, .bit =3D 2, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_GSPI] =3D { .ofs =3D 0x0, .bit =3D 4, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDS] =3D { .ofs =3D 0x0, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDS_REG] =3D { .ofs =3D 0x0, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDS_PHY] =3D { .ofs =3D 0x0, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_GPU2D] =3D { .ofs =3D 0x0, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DC_PHY] =3D { .ofs =3D 0x0, .bit =3D 22, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DCPHY_CRT] =3D { .ofs =3D 0x0, .bit =3D 24, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_LSADC] =3D { .ofs =3D 0x0, .bit =3D 26, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SE] =3D { .ofs =3D 0x0, .bit =3D 28, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DLA] =3D { .ofs =3D 0x0, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 1: offset 0x4 */ + [RTD1625_CRT_RSTN_JPEG] =3D { .ofs =3D 0x4, .bit =3D 0, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SD] =3D { .ofs =3D 0x4, .bit =3D 2, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SDIO] =3D { .ofs =3D 0x4, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCR_CNT] =3D { .ofs =3D 0x4, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_STITCH] =3D { .ofs =3D 0x4, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY] =3D { .ofs =3D 0x4, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0] =3D { .ofs =3D 0x4, .bit =3D 14, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_CORE] =3D { .ofs =3D 0x4, .bit =3D 16, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_POWER] =3D { .ofs =3D 0x4, .bit =3D 18, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_NONSTICH] =3D { .ofs =3D 0x4, .bit =3D 20, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_PHY_MDIO] =3D { .ofs =3D 0x4, .bit =3D 22, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE0_SGMII_MDIO] =3D { .ofs =3D 0x4, .bit =3D 24, .wri= te_en =3D 1 }, + [RTD1625_CRT_RSTN_VO2] =3D { .ofs =3D 0x4, .bit =3D 28, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_MISC_SC0] =3D { .ofs =3D 0x4, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 2: offset 0x8 */ + [RTD1625_CRT_RSTN_MD] =3D { .ofs =3D 0x8, .bit =3D 4, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_LVDS1] =3D { .ofs =3D 0x8, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_LVDS2] =3D { .ofs =3D 0x8, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_MISC_SC1] =3D { .ofs =3D 0x8, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_I2C_3] =3D { .ofs =3D 0x8, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_FAN] =3D { .ofs =3D 0x8, .bit =3D 14, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_TVE] =3D { .ofs =3D 0x8, .bit =3D 16, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_AIO] =3D { .ofs =3D 0x8, .bit =3D 18, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_VO] =3D { .ofs =3D 0x8, .bit =3D 20, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_MIPI_CSI] =3D { .ofs =3D 0x8, .bit =3D 22, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_HDMIRX] =3D { .ofs =3D 0x8, .bit =3D 24, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_HDMIRX_WRAP] =3D { .ofs =3D 0x8, .bit =3D 26, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_HDMI] =3D { .ofs =3D 0x8, .bit =3D 28, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_DISP] =3D { .ofs =3D 0x8, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 3: offset 0xc */ + [RTD1625_CRT_RSTN_SATA_PHY_POW1] =3D { .ofs =3D 0xc, .bit =3D 0, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SATA_PHY_POW0] =3D { .ofs =3D 0xc, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO1] =3D { .ofs =3D 0xc, .bit =3D 4, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MDIO0] =3D { .ofs =3D 0xc, .bit =3D 6, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_WRAP] =3D { .ofs =3D 0xc, .bit =3D 8, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P1] =3D { .ofs =3D 0xc, .bit =3D 10, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_P0] =3D { .ofs =3D 0xc, .bit =3D 12, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_SATA_MAC_COM] =3D { .ofs =3D 0xc, .bit =3D 14, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_STITCH] =3D { .ofs =3D 0xc, .bit =3D 16, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY] =3D { .ofs =3D 0xc, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1] =3D { .ofs =3D 0xc, .bit =3D 20, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_CORE] =3D { .ofs =3D 0xc, .bit =3D 22, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_POWER] =3D { .ofs =3D 0xc, .bit =3D 24, .write_e= n =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_NONSTICH] =3D { .ofs =3D 0xc, .bit =3D 26, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE1_PHY_MDIO] =3D { .ofs =3D 0xc, .bit =3D 28, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_HDMITOP] =3D { .ofs =3D 0xc, .bit =3D 30, .write_e= n =3D 1 }, + /* Bank 4: offset 0x68 */ + [RTD1625_CRT_RSTN_I2C_4] =3D { .ofs =3D 0x68, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_I2C_5] =3D { .ofs =3D 0x68, .bit =3D 4, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_TSIO] =3D { .ofs =3D 0x68, .bit =3D 6, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VI] =3D { .ofs =3D 0x68, .bit =3D 8, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_EDP] =3D { .ofs =3D 0x68, .bit =3D 10, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1_MMU] =3D { .ofs =3D 0x68, .bit =3D 12, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1_MMU_FUNC] =3D { .ofs =3D 0x68, .bit =3D 14, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_HSE_MMU] =3D { .ofs =3D 0x68, .bit =3D 16, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_HSE_MMU_FUNC] =3D { .ofs =3D 0x68, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDLM2M] =3D { .ofs =3D 0x68, .bit =3D 20, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_ISO_GSPI] =3D { .ofs =3D 0x68, .bit =3D 22, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SOFT_NPU] =3D { .ofs =3D 0x68, .bit =3D 24, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_SPI2EMMC] =3D { .ofs =3D 0x68, .bit =3D 26, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_EARC] =3D { .ofs =3D 0x68, .bit =3D 28, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1] =3D { .ofs =3D 0x68, .bit =3D 30, .write_= en =3D 1 }, + /* Bank 5: offset 0x90 */ + [RTD1625_CRT_RSTN_PCIE2_STITCH] =3D { .ofs =3D 0x90, .bit =3D 0, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY] =3D { .ofs =3D 0x90, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2] =3D { .ofs =3D 0x90, .bit =3D 4, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_CORE] =3D { .ofs =3D 0x90, .bit =3D 6, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_POWER] =3D { .ofs =3D 0x90, .bit =3D 8, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_NONSTICH] =3D { .ofs =3D 0x90, .bit =3D 10, .writ= e_en =3D 1 }, + [RTD1625_CRT_RSTN_PCIE2_PHY_MDIO] =3D { .ofs =3D 0x90, .bit =3D 12, .writ= e_en =3D 1 }, + [RTD1625_CRT_RSTN_DCPHY_UMCTL2] =3D { .ofs =3D 0x90, .bit =3D 14, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MIPI_DSI] =3D { .ofs =3D 0x90, .bit =3D 16, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_HIFM] =3D { .ofs =3D 0x90, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_NSRAM] =3D { .ofs =3D 0x90, .bit =3D 20, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_AUCPU0_REG] =3D { .ofs =3D 0x90, .bit =3D 22, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDL_GENPW] =3D { .ofs =3D 0x90, .bit =3D 24, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDL_CHIP] =3D { .ofs =3D 0x90, .bit =3D 26, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MDL_IP] =3D { .ofs =3D 0x90, .bit =3D 28, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_TEST_MUX] =3D { .ofs =3D 0x90, .bit =3D 30, .write_= en =3D 1 }, + /* Bank 6: offset 0xb8 */ + [RTD1625_CRT_RSTN_ISO_BIST] =3D { .ofs =3D 0xb8, .bit =3D 0, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MAIN_BIST] =3D { .ofs =3D 0xb8, .bit =3D 2, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_MAIN2_BIST] =3D { .ofs =3D 0xb8, .bit =3D 4, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE1_BIST] =3D { .ofs =3D 0xb8, .bit =3D 6, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE2_BIST] =3D { .ofs =3D 0xb8, .bit =3D 8, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_DCPHY_BIST] =3D { .ofs =3D 0xb8, .bit =3D 10, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_GPU_BIST] =3D { .ofs =3D 0xb8, .bit =3D 12, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_DISP_BIST] =3D { .ofs =3D 0xb8, .bit =3D 14, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_NPU_BIST] =3D { .ofs =3D 0xb8, .bit =3D 16, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_CAS_BIST] =3D { .ofs =3D 0xb8, .bit =3D 18, .write_= en =3D 1 }, + [RTD1625_CRT_RSTN_VE4_BIST] =3D { .ofs =3D 0xb8, .bit =3D 20, .write_= en =3D 1 }, + /* Bank 7: offset 0x454 (DUMMY0, no write_en) */ + [RTD1625_CRT_RSTN_EMMC] =3D { .ofs =3D 0x454, .bit =3D 0 }, + /* Bank 8: offset 0x458 (DUMMY1, no write_en) */ + [RTD1625_CRT_RSTN_GPU] =3D { .ofs =3D 0x458, .bit =3D 0 }, + /* Bank 9: offset 0x464 (DUMMY4, no write_en) */ + [RTD1625_CRT_RSTN_VE2] =3D { .ofs =3D 0x464, .bit =3D 0 }, + /* Bank 10: offset 0x880 */ + [RTD1625_CRT_RSTN_UR1] =3D { .ofs =3D 0x880, .bit =3D 0, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR2] =3D { .ofs =3D 0x880, .bit =3D 2, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR3] =3D { .ofs =3D 0x880, .bit =3D 4, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR4] =3D { .ofs =3D 0x880, .bit =3D 6, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR5] =3D { .ofs =3D 0x880, .bit =3D 8, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR6] =3D { .ofs =3D 0x880, .bit =3D 10, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR7] =3D { .ofs =3D 0x880, .bit =3D 12, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR8] =3D { .ofs =3D 0x880, .bit =3D 14, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR9] =3D { .ofs =3D 0x880, .bit =3D 16, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_UR_TOP] =3D { .ofs =3D 0x880, .bit =3D 18, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_I2C_7] =3D { .ofs =3D 0x880, .bit =3D 28, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_I2C_6] =3D { .ofs =3D 0x880, .bit =3D 30, .write= _en =3D 1 }, + /* Bank 11: offset 0x890 */ + [RTD1625_CRT_RSTN_SPI0] =3D { .ofs =3D 0x890, .bit =3D 0, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_SPI1] =3D { .ofs =3D 0x890, .bit =3D 2, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_SPI2] =3D { .ofs =3D 0x890, .bit =3D 4, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_LSADC0] =3D { .ofs =3D 0x890, .bit =3D 16, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_LSADC1] =3D { .ofs =3D 0x890, .bit =3D 18, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_ISOMIS_DMA] =3D { .ofs =3D 0x890, .bit =3D 20, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_AUDIO_ADC] =3D { .ofs =3D 0x890, .bit =3D 22, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_DPTX] =3D { .ofs =3D 0x890, .bit =3D 24, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_AUCPU1_REG] =3D { .ofs =3D 0x890, .bit =3D 26, .write= _en =3D 1 }, + [RTD1625_CRT_RSTN_EDPTX] =3D { .ofs =3D 0x890, .bit =3D 28, .write= _en =3D 1 }, +}; + +static struct clk_hw_onecell_data rtd1625_crt_hw_data =3D { + .num =3D RTD1625_CRT_CLK_MAX, + .hws =3D { + [RTD1625_CRT_CLK_EN_MISC] =3D &__clk_regmap_gate_hw(&clk_en_misc), + [RTD1625_CRT_CLK_EN_PCIE0] =3D &__clk_regmap_gate_hw(&clk_en_pcie0), + [RTD1625_CRT_CLK_EN_GSPI] =3D &__clk_regmap_gate_hw(&clk_en_gspi), + [RTD1625_CRT_CLK_EN_ISO_MISC] =3D &__clk_regmap_gate_hw(&clk_en_iso_misc= ), + [RTD1625_CRT_CLK_EN_SDS] =3D &__clk_regmap_gate_hw(&clk_en_sds), + [RTD1625_CRT_CLK_EN_HDMI] =3D &__clk_regmap_gate_hw(&clk_en_hdmi), + [RTD1625_CRT_CLK_EN_GPU] =3D &__clk_regmap_gate_hw(&clk_en_gpu), + [RTD1625_CRT_CLK_EN_VE1] =3D &__clk_regmap_gate_hw(&clk_en_ve1), + [RTD1625_CRT_CLK_EN_VE2] =3D &__clk_regmap_gate_hw(&clk_en_ve2), + [RTD1625_CRT_CLK_EN_MD] =3D &__clk_regmap_gate_hw(&clk_en_md), + [RTD1625_CRT_CLK_EN_TP] =3D &__clk_regmap_gate_hw(&clk_en_tp), + [RTD1625_CRT_CLK_EN_RCIC] =3D &__clk_regmap_gate_hw(&clk_en_rcic), + [RTD1625_CRT_CLK_EN_NF] =3D &__clk_regmap_gate_hw(&clk_en_nf), + [RTD1625_CRT_CLK_EN_EMMC] =3D &__clk_regmap_gate_hw(&clk_en_emmc), + [RTD1625_CRT_CLK_EN_SD] =3D &__clk_regmap_gate_hw(&clk_en_sd), + [RTD1625_CRT_CLK_EN_SDIO_IP] =3D &__clk_regmap_gate_hw(&clk_en_sdio_ip), + [RTD1625_CRT_CLK_EN_MIPI_CSI] =3D &__clk_regmap_gate_hw(&clk_en_mipi_csi= ), + [RTD1625_CRT_CLK_EN_EMMC_IP] =3D &__clk_regmap_gate_hw(&clk_en_emmc_ip), + [RTD1625_CRT_CLK_EN_SDIO] =3D &__clk_regmap_gate_hw(&clk_en_sdio), + [RTD1625_CRT_CLK_EN_SD_IP] =3D &__clk_regmap_gate_hw(&clk_en_sd_ip), + [RTD1625_CRT_CLK_EN_TPB] =3D &__clk_regmap_gate_hw(&clk_en_tpb), + [RTD1625_CRT_CLK_EN_MISC_SC1] =3D &__clk_regmap_gate_hw(&clk_en_misc_sc1= ), + [RTD1625_CRT_CLK_EN_MISC_I2C_3] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_3), + [RTD1625_CRT_CLK_EN_ACPU] =3D &__clk_regmap_gate_hw(&clk_en_acpu), + [RTD1625_CRT_CLK_EN_JPEG] =3D &__clk_regmap_gate_hw(&clk_en_jpeg), + [RTD1625_CRT_CLK_EN_MISC_SC0] =3D &__clk_regmap_gate_hw(&clk_en_misc_sc0= ), + [RTD1625_CRT_CLK_EN_HDMIRX] =3D &__clk_regmap_gate_hw(&clk_en_hdmirx), + [RTD1625_CRT_CLK_EN_HSE] =3D &__clk_regmap_gate_hw(&clk_en_hse), + [RTD1625_CRT_CLK_EN_FAN] =3D &__clk_regmap_gate_hw(&clk_en_fan), + [RTD1625_CRT_CLK_EN_SATA_WRAP_SYS] =3D &__clk_regmap_gate_hw(&clk_en_sat= a_wrap_sys), + [RTD1625_CRT_CLK_EN_SATA_WRAP_SYSH] =3D &__clk_regmap_gate_hw(&clk_en_sa= ta_wrap_sysh), + [RTD1625_CRT_CLK_EN_SATA_MAC_SYSH] =3D &__clk_regmap_gate_hw(&clk_en_sat= a_mac_sysh), + [RTD1625_CRT_CLK_EN_R2RDSC] =3D &__clk_regmap_gate_hw(&clk_en_r2rdsc), + [RTD1625_CRT_CLK_EN_PCIE1] =3D &__clk_regmap_gate_hw(&clk_en_pcie1), + [RTD1625_CRT_CLK_EN_MISC_I2C_4] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_4), + [RTD1625_CRT_CLK_EN_MISC_I2C_5] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_5), + [RTD1625_CRT_CLK_EN_TSIO] =3D &__clk_regmap_gate_hw(&clk_en_tsio), + [RTD1625_CRT_CLK_EN_VE4] =3D &__clk_regmap_gate_hw(&clk_en_ve4), + [RTD1625_CRT_CLK_EN_EDP] =3D &__clk_regmap_gate_hw(&clk_en_edp), + [RTD1625_CRT_CLK_EN_TSIO_TRX] =3D &__clk_regmap_gate_hw(&clk_en_tsio_trx= ), + [RTD1625_CRT_CLK_EN_PCIE2] =3D &__clk_regmap_gate_hw(&clk_en_pcie2), + [RTD1625_CRT_CLK_EN_EARC] =3D &__clk_regmap_gate_hw(&clk_en_earc), + [RTD1625_CRT_CLK_EN_LITE] =3D &__clk_regmap_gate_hw(&clk_en_lite), + [RTD1625_CRT_CLK_EN_MIPI_DSI] =3D &__clk_regmap_gate_hw(&clk_en_mipi_dsi= ), + [RTD1625_CRT_CLK_EN_NPUPP] =3D &__clk_regmap_gate_hw(&clk_en_npupp), + [RTD1625_CRT_CLK_EN_NPU] =3D &__clk_regmap_gate_hw(&clk_en_npu), + [RTD1625_CRT_CLK_EN_AUCPU0] =3D &__clk_regmap_gate_hw(&clk_en_aucpu0), + [RTD1625_CRT_CLK_EN_AUCPU1] =3D &__clk_regmap_gate_hw(&clk_en_aucpu1), + [RTD1625_CRT_CLK_EN_NSRAM] =3D &__clk_regmap_gate_hw(&clk_en_nsram), + [RTD1625_CRT_CLK_EN_HDMITOP] =3D &__clk_regmap_gate_hw(&clk_en_hdmitop), + [RTD1625_CRT_CLK_EN_AUCPU_ISO_NPU] =3D &__clk_regmap_gate_hw(&clk_en_auc= pu_iso_npu), + [RTD1625_CRT_CLK_EN_KEYLADDER] =3D &__clk_regmap_gate_hw(&clk_en_keyladd= er), + [RTD1625_CRT_CLK_EN_IFCP_KLM] =3D &__clk_regmap_gate_hw(&clk_en_ifcp_kl= m), + [RTD1625_CRT_CLK_EN_IFCP] =3D &__clk_regmap_gate_hw(&clk_en_ifcp), + [RTD1625_CRT_CLK_EN_MDL_GENPW] =3D &__clk_regmap_gate_hw(&clk_en_mdl_gen= pw), + [RTD1625_CRT_CLK_EN_MDL_CHIP] =3D &__clk_regmap_gate_hw(&clk_en_mdl_chi= p), + [RTD1625_CRT_CLK_EN_MDL_IP] =3D &__clk_regmap_gate_hw(&clk_en_mdl_ip), + [RTD1625_CRT_CLK_EN_MDLM2M] =3D &__clk_regmap_gate_hw(&clk_en_mdlm2m), + [RTD1625_CRT_CLK_EN_MDL_XTAL] =3D &__clk_regmap_gate_hw(&clk_en_mdl_xta= l), + [RTD1625_CRT_CLK_EN_TEST_MUX] =3D &__clk_regmap_gate_hw(&clk_en_test_mu= x), + [RTD1625_CRT_CLK_EN_DLA] =3D &__clk_regmap_gate_hw(&clk_en_dla), + [RTD1625_CRT_CLK_EN_TPCW] =3D &__clk_regmap_gate_hw(&clk_en_tpcw), + [RTD1625_CRT_CLK_EN_GPU_TS_SRC] =3D &__clk_regmap_gate_hw(&clk_en_gpu_ts= _src), + [RTD1625_CRT_CLK_EN_VI] =3D &__clk_regmap_gate_hw(&clk_en_vi), + [RTD1625_CRT_CLK_EN_LVDS1] =3D &__clk_regmap_gate_hw(&clk_en_lvds1), + [RTD1625_CRT_CLK_EN_LVDS2] =3D &__clk_regmap_gate_hw(&clk_en_lvds2), + [RTD1625_CRT_CLK_EN_AUCPU] =3D &__clk_regmap_gate_hw(&clk_en_aucpu), + [RTD1625_CRT_CLK_EN_UR1] =3D &__clk_regmap_gate_hw(&clk_en_ur1), + [RTD1625_CRT_CLK_EN_UR2] =3D &__clk_regmap_gate_hw(&clk_en_ur2), + [RTD1625_CRT_CLK_EN_UR3] =3D &__clk_regmap_gate_hw(&clk_en_ur3), + [RTD1625_CRT_CLK_EN_UR4] =3D &__clk_regmap_gate_hw(&clk_en_ur4), + [RTD1625_CRT_CLK_EN_UR5] =3D &__clk_regmap_gate_hw(&clk_en_ur5), + [RTD1625_CRT_CLK_EN_UR6] =3D &__clk_regmap_gate_hw(&clk_en_ur6), + [RTD1625_CRT_CLK_EN_UR7] =3D &__clk_regmap_gate_hw(&clk_en_ur7), + [RTD1625_CRT_CLK_EN_UR8] =3D &__clk_regmap_gate_hw(&clk_en_ur8), + [RTD1625_CRT_CLK_EN_UR9] =3D &__clk_regmap_gate_hw(&clk_en_ur9), + [RTD1625_CRT_CLK_EN_UR_TOP] =3D &__clk_regmap_gate_hw(&clk_en_ur_top), + [RTD1625_CRT_CLK_EN_MISC_I2C_7] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_7), + [RTD1625_CRT_CLK_EN_MISC_I2C_6] =3D &__clk_regmap_gate_hw(&clk_en_misc_i= 2c_6), + [RTD1625_CRT_CLK_EN_SPI0] =3D &__clk_regmap_gate_hw(&clk_en_spi0), + [RTD1625_CRT_CLK_EN_SPI1] =3D &__clk_regmap_gate_hw(&clk_en_spi1), + [RTD1625_CRT_CLK_EN_SPI2] =3D &__clk_regmap_gate_hw(&clk_en_spi2), + [RTD1625_CRT_CLK_EN_LSADC0] =3D &__clk_regmap_gate_hw(&clk_en_lsadc0), + [RTD1625_CRT_CLK_EN_LSADC1] =3D &__clk_regmap_gate_hw(&clk_en_lsadc1), + [RTD1625_CRT_CLK_EN_ISOMIS_DMA] =3D &__clk_regmap_gate_hw(&clk_en_isomis= _dma), + [RTD1625_CRT_CLK_EN_DPTX] =3D &__clk_regmap_gate_hw(&clk_en_dptx), + [RTD1625_CRT_CLK_EN_NPU_MIPI_CSI] =3D &__clk_regmap_gate_hw(&clk_en_npu_= mipi_csi), + [RTD1625_CRT_CLK_EN_EDPTX] =3D &__clk_regmap_gate_hw(&clk_en_edptx), + [RTD1625_CRT_CLK_GPU] =3D &__clk_regmap_mux_hw(&clk_gpu), + [RTD1625_CRT_CLK_VE1] =3D &__clk_regmap_mux_hw(&clk_ve1), + [RTD1625_CRT_CLK_VE2] =3D &__clk_regmap_mux_hw(&clk_ve2), + [RTD1625_CRT_CLK_VE4] =3D &__clk_regmap_mux_hw(&clk_ve4), + [RTD1625_CRT_PLL_VE1] =3D &__clk_pll_hw(&pll_ve1), + [RTD1625_CRT_PLL_DDSA] =3D &__clk_pll_hw(&pll_ddsa), + [RTD1625_CRT_PLL_BUS] =3D &__clk_pll_hw(&pll_bus), + [RTD1625_CRT_CLK_SYS] =3D &clk_sys.hw, + [RTD1625_CRT_PLL_DCSB] =3D &__clk_pll_hw(&pll_dcsb), + [RTD1625_CRT_CLK_SYSH] =3D &clk_sysh.hw, + [RTD1625_CRT_PLL_GPU] =3D &__clk_pll_hw(&pll_gpu), + [RTD1625_CRT_PLL_NPU] =3D &__clk_pll_hw(&pll_npu), + [RTD1625_CRT_PLL_VE2] =3D &__clk_pll_hw(&pll_ve2), + [RTD1625_CRT_PLL_HIFI] =3D &__clk_pll_hw(&pll_hifi), + [RTD1625_CRT_PLL_EMMC_REF] =3D &pll_emmc_ref.hw, + [RTD1625_CRT_PLL_EMMC] =3D &__clk_pll_mmc_hw(&pll_emmc), + [RTD1625_CRT_PLL_EMMC_VP0] =3D &pll_emmc.phase0_hw, + [RTD1625_CRT_PLL_EMMC_VP1] =3D &pll_emmc.phase1_hw, + [RTD1625_CRT_PLL_ACPU] =3D &__clk_pll_hw(&pll_acpu), + [RTD1625_CRT_CLK_NPU] =3D &clk_npu.hw, + [RTD1625_CRT_CLK_NPU_MIPI_CSI] =3D &clk_npu_mipi_csi.hw, + + [RTD1625_CRT_CLK_MAX] =3D NULL, + }, +}; + +static const struct rtk_clk_desc rtd1625_crt_desc =3D { + .clk_data =3D &rtd1625_crt_hw_data, + .clks =3D rtd1625_crt_regmap_clks, + .num_clks =3D ARRAY_SIZE(rtd1625_crt_regmap_clks), + .reset_descs =3D rtd1625_crt_reset_descs, + .num_reset_descs =3D RTD1625_CRT_RSTN_MAX, +}; + +static int rtd1625_crt_probe(struct platform_device *pdev) +{ + const struct rtk_clk_desc *desc; + + desc =3D of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + return rtk_clk_probe(pdev, desc); +} + +static const struct of_device_id rtd1625_crt_match[] =3D { + {.compatible =3D "realtek,rtd1625-crt-clk", .data =3D &rtd1625_crt_desc,}, + {/* sentinel */} +}; + +static struct platform_driver rtd1625_crt_driver =3D { + .probe =3D rtd1625_crt_probe, + .driver =3D { + .name =3D "rtk-rtd1625-crt-clk", + .of_match_table =3D rtd1625_crt_match, + }, +}; + +static int __init rtd1625_crt_init(void) +{ + return platform_driver_register(&rtd1625_crt_driver); +} +subsys_initcall(rtd1625_crt_init); + +MODULE_DESCRIPTION("Reatek RTD1625 CRT Controller Driver"); +MODULE_AUTHOR("Cheng-Yu Lee "); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sun Apr 5 13:06:01 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F93C388E6A; Tue, 24 Mar 2026 02:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774321015; cv=none; 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rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 62O2rZX71278472 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 24 Mar 2026 10:53:35 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 24 Mar 2026 10:53:35 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 24 Mar 2026 10:53:35 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v5 10/10] clk: realtek: Add RTD1625-ISO clock controller driver Date: Tue, 24 Mar 2026 10:53:31 +0800 Message-ID: <20260324025332.3416977-11-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260324025332.3416977-1-eleanor.lin@realtek.com> References: <20260324025332.3416977-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Add support for the ISO (Isolation) domain clock controller on the Realtek RTD1625 SoC. This controller manages clocks in the always-on power domain, ensuring essential services remain functional even when the main system power is gated. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v5: - Added '#include '. - Replaced rtk_reset_bank arrays with rtk_reset_desc descriptors. - Implemented complete mapping tables for all reset IDs. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-rtd1625-iso.c | 188 ++++++++++++++++++++++++++ 2 files changed, 189 insertions(+) create mode 100644 drivers/clk/realtek/clk-rtd1625-iso.c diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index c992f97dfbc7..1680435e1e0f 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -10,3 +10,4 @@ clk-rtk-y +=3D freq_table.o =20 clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) +=3D clk-pll-mmc.o obj-$(CONFIG_COMMON_CLK_RTD1625) +=3D clk-rtd1625-crt.o +obj-$(CONFIG_COMMON_CLK_RTD1625) +=3D clk-rtd1625-iso.o diff --git a/drivers/clk/realtek/clk-rtd1625-iso.c b/drivers/clk/realtek/cl= k-rtd1625-iso.c new file mode 100644 index 000000000000..cfe82c9d4457 --- /dev/null +++ b/drivers/clk/realtek/clk-rtd1625-iso.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include +#include +#include +#include "clk-regmap-gate.h" + +#define RTD1625_ISO_CLK_MAX 19 +#define RTD1625_ISO_RSTN_MAX 29 +#define RTD1625_ISO_S_CLK_MAX 5 +#define RTD1625_ISO_S_RSTN_MAX 5 + +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_p4, 0, 0x4, 0, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_p3, 0, 0x4, 1, 0); +static CLK_REGMAP_GATE(clk_en_misc_cec0, "clk_en_misc", 0, 0x4, 2, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbusrx_sys, 0, 0x4, 3, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbustx_sys, 0, 0x4, 4, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbus_sys, 0, 0x4, 5, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbus_osc, 0, 0x4, 6, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_i2c0, 0, 0x4, 9, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_i2c1, 0, 0x4, 10, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_etn_250m, 0, 0x4, 11, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_etn_sys, 0, 0x4, 12, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_drd, 0, 0x4, 13, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_host, 0, 0x4, 14, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_u3_host, 0, 0x4, 15, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb, 0, 0x4, 16, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_vtc, 0, 0x4, 17, 0); +static CLK_REGMAP_GATE(clk_en_misc_vfd, "clk_en_misc", 0, 0x4, 18, 0); + +static struct clk_regmap *rtd1625_clk_regmap_list[] =3D { + &clk_en_usb_p4.clkr, + &clk_en_usb_p3.clkr, + &clk_en_misc_cec0.clkr, + &clk_en_cbusrx_sys.clkr, + &clk_en_cbustx_sys.clkr, + &clk_en_cbus_sys.clkr, + &clk_en_cbus_osc.clkr, + &clk_en_i2c0.clkr, + &clk_en_i2c1.clkr, + &clk_en_etn_250m.clkr, + &clk_en_etn_sys.clkr, + &clk_en_usb_drd.clkr, + &clk_en_usb_host.clkr, + &clk_en_usb_u3_host.clkr, + &clk_en_usb.clkr, + &clk_en_vtc.clkr, + &clk_en_misc_vfd.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_iso_clk_data =3D { + .num =3D RTD1625_ISO_CLK_MAX, + .hws =3D { + [RTD1625_ISO_CLK_EN_USB_P4] =3D &__clk_regmap_gate_hw(&clk_en_usb_p= 4), + [RTD1625_ISO_CLK_EN_USB_P3] =3D &__clk_regmap_gate_hw(&clk_en_usb_p= 3), + [RTD1625_ISO_CLK_EN_MISC_CEC0] =3D &__clk_regmap_gate_hw(&clk_en_misc_= cec0), + [RTD1625_ISO_CLK_EN_CBUSRX_SYS] =3D &__clk_regmap_gate_hw(&clk_en_cbusr= x_sys), + [RTD1625_ISO_CLK_EN_CBUSTX_SYS] =3D &__clk_regmap_gate_hw(&clk_en_cbust= x_sys), + [RTD1625_ISO_CLK_EN_CBUS_SYS] =3D &__clk_regmap_gate_hw(&clk_en_cbus_= sys), + [RTD1625_ISO_CLK_EN_CBUS_OSC] =3D &__clk_regmap_gate_hw(&clk_en_cbus_= osc), + [RTD1625_ISO_CLK_EN_I2C0] =3D &__clk_regmap_gate_hw(&clk_en_i2c0), + [RTD1625_ISO_CLK_EN_I2C1] =3D &__clk_regmap_gate_hw(&clk_en_i2c1), + [RTD1625_ISO_CLK_EN_ETN_250M] =3D &__clk_regmap_gate_hw(&clk_en_etn_2= 50m), + [RTD1625_ISO_CLK_EN_ETN_SYS] =3D &__clk_regmap_gate_hw(&clk_en_etn_s= ys), + [RTD1625_ISO_CLK_EN_USB_DRD] =3D &__clk_regmap_gate_hw(&clk_en_usb_d= rd), + [RTD1625_ISO_CLK_EN_USB_HOST] =3D &__clk_regmap_gate_hw(&clk_en_usb_h= ost), + [RTD1625_ISO_CLK_EN_USB_U3_HOST] =3D &__clk_regmap_gate_hw(&clk_en_usb_u= 3_host), + [RTD1625_ISO_CLK_EN_USB] =3D &__clk_regmap_gate_hw(&clk_en_usb), + [RTD1625_ISO_CLK_EN_VTC] =3D &__clk_regmap_gate_hw(&clk_en_vtc), + [RTD1625_ISO_CLK_EN_MISC_VFD] =3D &__clk_regmap_gate_hw(&clk_en_misc_= vfd), + [RTD1625_ISO_CLK_MAX] =3D NULL, + }, +}; + +static struct rtk_reset_desc rtd1625_iso_reset_descs[] =3D { + [RTD1625_ISO_RSTN_VFD] =3D { .ofs =3D 0x88, .bit =3D 0 }, + [RTD1625_ISO_RSTN_CEC0] =3D { .ofs =3D 0x88, .bit =3D 2 }, + [RTD1625_ISO_RSTN_CEC1] =3D { .ofs =3D 0x88, .bit =3D 3 }, + [RTD1625_ISO_RSTN_CBUSTX] =3D { .ofs =3D 0x88, .bit =3D 5 }, + [RTD1625_ISO_RSTN_CBUSRX] =3D { .ofs =3D 0x88, .bit =3D 6 }, + [RTD1625_ISO_RSTN_USB3_PHY2_XTAL_POW] =3D { .ofs =3D 0x88, .bit =3D 7 }, + [RTD1625_ISO_RSTN_UR0] =3D { .ofs =3D 0x88, .bit =3D 8 }, + [RTD1625_ISO_RSTN_GMAC] =3D { .ofs =3D 0x88, .bit =3D 9 }, + [RTD1625_ISO_RSTN_GPHY] =3D { .ofs =3D 0x88, .bit =3D 10 }, + [RTD1625_ISO_RSTN_I2C_0] =3D { .ofs =3D 0x88, .bit =3D 11 }, + [RTD1625_ISO_RSTN_I2C_1] =3D { .ofs =3D 0x88, .bit =3D 12 }, + [RTD1625_ISO_RSTN_CBUS] =3D { .ofs =3D 0x88, .bit =3D 13 }, + [RTD1625_ISO_RSTN_USB_DRD] =3D { .ofs =3D 0x88, .bit =3D 14 }, + [RTD1625_ISO_RSTN_USB_HOST] =3D { .ofs =3D 0x88, .bit =3D 15 }, + [RTD1625_ISO_RSTN_USB_PHY_0] =3D { .ofs =3D 0x88, .bit =3D 16 }, + [RTD1625_ISO_RSTN_USB_PHY_1] =3D { .ofs =3D 0x88, .bit =3D 17 }, + [RTD1625_ISO_RSTN_USB_PHY_2] =3D { .ofs =3D 0x88, .bit =3D 18 }, + [RTD1625_ISO_RSTN_USB] =3D { .ofs =3D 0x88, .bit =3D 19 }, + [RTD1625_ISO_RSTN_TYPE_C] =3D { .ofs =3D 0x88, .bit =3D 20 }, + [RTD1625_ISO_RSTN_USB_U3_HOST] =3D { .ofs =3D 0x88, .bit =3D 21 }, + [RTD1625_ISO_RSTN_USB3_PHY0_POW] =3D { .ofs =3D 0x88, .bit =3D 22 }, + [RTD1625_ISO_RSTN_USB3_P0_MDIO] =3D { .ofs =3D 0x88, .bit =3D 23 }, + [RTD1625_ISO_RSTN_USB3_PHY1_POW] =3D { .ofs =3D 0x88, .bit =3D 24 }, + [RTD1625_ISO_RSTN_USB3_P1_MDIO] =3D { .ofs =3D 0x88, .bit =3D 25 }, + [RTD1625_ISO_RSTN_VTC] =3D { .ofs =3D 0x88, .bit =3D 26 }, + [RTD1625_ISO_RSTN_USB3_PHY2_POW] =3D { .ofs =3D 0x88, .bit =3D 27 }, + [RTD1625_ISO_RSTN_USB3_P2_MDIO] =3D { .ofs =3D 0x88, .bit =3D 28 }, + [RTD1625_ISO_RSTN_USB_PHY_3] =3D { .ofs =3D 0x88, .bit =3D 29 }, + [RTD1625_ISO_RSTN_USB_PHY_4] =3D { .ofs =3D 0x88, .bit =3D 30 }, +}; + +static const struct rtk_clk_desc rtd1625_iso_desc =3D { + .clk_data =3D &rtd1625_iso_clk_data, + .clks =3D rtd1625_clk_regmap_list, + .num_clks =3D ARRAY_SIZE(rtd1625_clk_regmap_list), + .reset_descs =3D rtd1625_iso_reset_descs, + .num_reset_descs =3D RTD1625_ISO_RSTN_MAX, +}; + +static CLK_REGMAP_GATE_NO_PARENT(clk_en_irda, 0, 0x4, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ur10, 0, 0x4, 8, 1); + +static struct clk_regmap *rtd1625_iso_s_clk_regmap_list[] =3D { + &clk_en_irda.clkr, + &clk_en_ur10.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_iso_s_clk_data =3D { + .num =3D RTD1625_ISO_S_CLK_MAX, + .hws =3D { + [RTD1625_ISO_S_CLK_EN_IRDA] =3D &__clk_regmap_gate_hw(&clk_en_irda), + [RTD1625_ISO_S_CLK_EN_UR10] =3D &__clk_regmap_gate_hw(&clk_en_ur10), + [RTD1625_ISO_S_CLK_MAX] =3D NULL, + }, +}; + +static struct rtk_reset_desc rtd1625_iso_s_reset_descs[] =3D { + [RTD1625_ISO_S_RSTN_ISOM_MIS] =3D { .ofs =3D 0x310, .bit =3D 0, .write_en= =3D 1 }, + [RTD1625_ISO_S_RSTN_GPIOM] =3D { .ofs =3D 0x310, .bit =3D 2, .write_en= =3D 1 }, + [RTD1625_ISO_S_RSTN_TIMER7] =3D { .ofs =3D 0x310, .bit =3D 4, .write_en= =3D 1 }, + [RTD1625_ISO_S_RSTN_IRDA] =3D { .ofs =3D 0x310, .bit =3D 6, .write_en= =3D 1 }, + [RTD1625_ISO_S_RSTN_UR10] =3D { .ofs =3D 0x310, .bit =3D 8, .write_en= =3D 1 }, +}; + +static const struct rtk_clk_desc rtd1625_iso_s_desc =3D { + .clk_data =3D &rtd1625_iso_s_clk_data, + .clks =3D rtd1625_iso_s_clk_regmap_list, + .num_clks =3D ARRAY_SIZE(rtd1625_iso_s_clk_regmap_list), + .reset_descs =3D rtd1625_iso_s_reset_descs, + .num_reset_descs =3D RTD1625_ISO_S_RSTN_MAX, +}; + +static int rtd1625_iso_probe(struct platform_device *pdev) +{ + const struct rtk_clk_desc *desc; + + desc =3D of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + return rtk_clk_probe(pdev, desc); +} + +static const struct of_device_id rtd1625_iso_match[] =3D { + {.compatible =3D "realtek,rtd1625-iso-clk", .data =3D &rtd1625_iso_desc}, + {.compatible =3D "realtek,rtd1625-iso-s-clk", .data =3D &rtd1625_iso_s_de= sc}, + {/* sentinel */} +}; + +static struct platform_driver rtd1625_iso_driver =3D { + .probe =3D rtd1625_iso_probe, + .driver =3D { + .name =3D "rtk-rtd1625-iso-clk", + .of_match_table =3D rtd1625_iso_match, + }, +}; + +static int __init rtd1625_iso_init(void) +{ + return platform_driver_register(&rtd1625_iso_driver); +} +subsys_initcall(rtd1625_iso_init); + +MODULE_DESCRIPTION("Realtek RTD1625 ISO Controller Driver"); +MODULE_AUTHOR("Cheng-Yu Lee "); +MODULE_LICENSE("GPL"); --=20 2.34.1