From nobody Thu Apr 2 10:56:41 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DECD34D90C; Tue, 24 Mar 2026 00:46:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774313209; cv=none; b=hfP6RBqE91Jvab7svKokFsqRFr0wTeY+vAZRapuzRrg0/Ale26z8xrU+sN08/se3IXlk0s35tnu1GO1VnDPAPrQuhIY2z4C8kivF4gfKzKHZv4NQMo81VpkR4ZDoz+MgOfM2toaXQJogn8a0z4MO2xoGn6yMGFhEu2ru+b1yYoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774313209; c=relaxed/simple; bh=MFZWogFnHqFSZKefxWXjpdRCaY3X2l1UQDQz8jBRbDY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DZDhngf3ajJK7oWeqoyDPnM318NArxwqE/shPmfAlZZ7OTLLqJArElVOvzj0CC/5J8ByU/0lIV//sNJ1ZtC5NnLiTsi2p+XZgNys8jf9+iPsU0knURxhH1iHA5ktalgErNZwuD57y1/OKDzyP5BzXO9ArPdlZ/0mKvXK+D79QzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Nh6iCa3I; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Nh6iCa3I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774313208; x=1805849208; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MFZWogFnHqFSZKefxWXjpdRCaY3X2l1UQDQz8jBRbDY=; b=Nh6iCa3IrlhIw10rDBiEVu2cNovS7AolNFJoqbdPAHIsVO7dC811mK+I 4nbklwakLk7SFuXRPNc2WJViQt5mi5ExlK6VQejdBE2DESagk44GkZzgQ GAz25ZIw67BseRqjdR0Elr0Iy1DcsiP8sm/oE/IPssB7meTfvUK3FEePd UKWXCWdW76rKMeYbyN21Iovk6byR6jqljNNOS+V603+yl+C0UX0uLW66F 872kLCKb/wecnpHmEiMqXgHhE0BZxUsoTbFJHGg8Q3xgHN13UFeTRQp3M IAexLcDhWBZ5d2SaQC/vyEfQ5QW8uVthzWQzxOxnq7MbALeGvoLQaCpDd A==; X-CSE-ConnectionGUID: ejPgRkj+QIyX+ibhav7O1g== X-CSE-MsgGUID: xcxKbaC4Qj+QW7KRUaPFfw== X-IronPort-AV: E=McAfee;i="6800,10657,11738"; a="86397137" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="86397137" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2026 17:46:48 -0700 X-CSE-ConnectionGUID: 2/jXmcqKQeCEi+iOtWETQw== X-CSE-MsgGUID: Q04zkw1ZQlCSI+7X2rajbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="221322811" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa008.fm.intel.com with ESMTP; 23 Mar 2026 17:46:43 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi , Kan Liang Subject: [Patch v7 12/24] perf/x86: Enable XMM register sampling for REGS_USER case Date: Tue, 24 Mar 2026 08:41:06 +0800 Message-Id: <20260324004118.3772171-13-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260324004118.3772171-1-dapeng1.mi@linux.intel.com> References: <20260324004118.3772171-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds support for XMM register sampling in the REGS_USER case. To handle simultaneous sampling of XMM registers for both REGS_INTR and REGS_USER cases, a per-CPU `x86_user_regs` is introduced to store REGS_USER-specific XMM registers. This prevents REGS_USER-specific XMM register data from being overwritten by REGS_INTR-specific data if they share the same `x86_perf_regs` structure. To sample user-space XMM registers, the `x86_pmu_update_user_ext_regs()` helper function is added. It checks if the `TIF_NEED_FPU_LOAD` flag is set. If so, the user-space XMM register data can be directly retrieved from the cached task FPU state, as the corresponding hardware registers have been cleared or switched to kernel-space data. Otherwise, the data must be read from the hardware registers using the `xsaves` instruction. For PEBS events, `x86_pmu_update_user_ext_regs()` checks if the PEBS-sampled XMM register data belongs to user-space. If so, no further action is needed. Otherwise, the user-space XMM register data needs to be re-sampled using the same method as for non-PEBS events. Co-developed-by: Kan Liang Signed-off-by: Kan Liang Signed-off-by: Dapeng Mi --- arch/x86/events/core.c | 95 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 82 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 22965a8a22b3..a5643c875190 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -696,7 +696,7 @@ int x86_pmu_hw_config(struct perf_event *event) return -EINVAL; } =20 - if (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) { + if (event->attr.sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_U= SER)) { /* * Besides the general purpose registers, XMM registers may * be collected as well. @@ -707,15 +707,6 @@ int x86_pmu_hw_config(struct perf_event *event) } } =20 - if (event->attr.sample_type & PERF_SAMPLE_REGS_USER) { - /* - * Currently XMM registers sampling for REGS_USER is not - * supported yet. - */ - if (event_has_extended_regs(event)) - return -EINVAL; - } - return x86_setup_perfctr(event); } =20 @@ -1745,6 +1736,28 @@ static void x86_pmu_del(struct perf_event *event, in= t flags) static_call_cond(x86_pmu_del)(event); } =20 +/* + * When both PERF_SAMPLE_REGS_INTR and PERF_SAMPLE_REGS_USER are set, + * an additional x86_perf_regs is required to save user-space registers. + * Without this, user-space register data may be overwritten by kernel-spa= ce + * registers. + */ +static DEFINE_PER_CPU(struct x86_perf_regs, x86_user_regs); +static void x86_pmu_perf_get_regs_user(struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct x86_perf_regs *x86_regs_user =3D this_cpu_ptr(&x86_user_regs); + struct perf_regs regs_user; + + perf_get_regs_user(®s_user, regs); + data->regs_user.abi =3D regs_user.abi; + if (regs_user.regs) { + x86_regs_user->regs =3D *regs_user.regs; + data->regs_user.regs =3D &x86_regs_user->regs; + } else + data->regs_user.regs =3D NULL; +} + static void x86_pmu_setup_gpregs_data(struct perf_event *event, struct perf_sample_data *data, struct pt_regs *regs) @@ -1757,7 +1770,14 @@ static void x86_pmu_setup_gpregs_data(struct perf_ev= ent *event, data->regs_user.abi =3D perf_reg_abi(current); data->regs_user.regs =3D regs; } else if (!(current->flags & PF_KTHREAD)) { - perf_get_regs_user(&data->regs_user, regs); + /* + * It cannot guarantee that the kernel will never + * touch the registers outside of the pt_regs, + * especially when more and more registers + * (e.g., SIMD, eGPR) are added. The live data + * cannot be used. + */ + x86_pmu_perf_get_regs_user(data, regs); } else { data->regs_user.abi =3D PERF_SAMPLE_REGS_ABI_NONE; data->regs_user.regs =3D NULL; @@ -1800,6 +1820,43 @@ static inline void x86_pmu_update_xregs(struct x86_p= erf_regs *perf_regs, perf_regs->xmm_space =3D xsave->i387.xmm_space; } =20 +/* + * This function retrieves cached user-space fpu registers (XMM/YMM/ZMM). + * If TIF_NEED_FPU_LOAD is set, it indicates that the user-space FPU state + * is cached. Otherwise, the data should be read directly from the hardware + * registers. + */ +static inline u64 x86_pmu_update_user_xregs(struct perf_sample_data *data, + u64 mask, u64 ignore_mask) +{ + struct x86_perf_regs *perf_regs; + struct xregs_state *xsave; + struct fpu *fpu; + struct fpstate *fps; + + if (data->regs_user.abi =3D=3D PERF_SAMPLE_REGS_ABI_NONE) + return 0; + + if (test_thread_flag(TIF_NEED_FPU_LOAD)) { + perf_regs =3D container_of(data->regs_user.regs, + struct x86_perf_regs, regs); + fpu =3D x86_task_fpu(current); + /* + * If __task_fpstate is set, it holds the right pointer, + * otherwise fpstate will. + */ + fps =3D READ_ONCE(fpu->__task_fpstate); + if (!fps) + fps =3D fpu->fpstate; + xsave =3D &fps->regs.xsave; + + x86_pmu_update_xregs(perf_regs, xsave, mask); + return 0; + } + + return mask & ~ignore_mask; +} + static void x86_pmu_sample_xregs(struct perf_event *event, struct perf_sample_data *data, u64 ignore_mask) @@ -1807,6 +1864,7 @@ static void x86_pmu_sample_xregs(struct perf_event *e= vent, struct xregs_state *xsave =3D per_cpu(ext_regs_buf, smp_processor_id()); u64 sample_type =3D event->attr.sample_type; struct x86_perf_regs *perf_regs; + u64 user_mask =3D 0; u64 intr_mask =3D 0; u64 mask =3D 0; =20 @@ -1817,15 +1875,26 @@ static void x86_pmu_sample_xregs(struct perf_event = *event, mask |=3D XFEATURE_MASK_SSE; =20 mask &=3D x86_pmu.ext_regs_mask; + if ((sample_type & PERF_SAMPLE_REGS_USER) && data->regs_user.abi) + user_mask =3D x86_pmu_update_user_xregs(data, mask, ignore_mask); =20 if ((sample_type & PERF_SAMPLE_REGS_INTR) && data->regs_intr.abi) intr_mask =3D mask & ~ignore_mask; =20 + if (user_mask | intr_mask) { + xsave->header.xfeatures =3D 0; + xsaves_nmi(xsave, user_mask | intr_mask); + } + + if (user_mask) { + perf_regs =3D container_of(data->regs_user.regs, + struct x86_perf_regs, regs); + x86_pmu_update_xregs(perf_regs, xsave, user_mask); + } + if (intr_mask) { perf_regs =3D container_of(data->regs_intr.regs, struct x86_perf_regs, regs); - xsave->header.xfeatures =3D 0; - xsaves_nmi(xsave, mask); x86_pmu_update_xregs(perf_regs, xsave, intr_mask); } } --=20 2.34.1