From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43E9F37D101; Tue, 24 Mar 2026 18:16:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376198; cv=none; b=tmdT3C/9zmQBC7duMqeCjNXEZ4GNsvIpI8WsltvQbeNPjqHW1dKkIePy5h6/UBnZJkwu9Ax6CcbiV4JMW1A5lacSZgIcHvhcwqP+WgBdOaJpyQbV1UJODNm6maOvKbUew+u50NtaLmIPwOPoR2uI5X5FqSSYzD/n9ykLX/DmwbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376198; c=relaxed/simple; bh=hpBLvfVKe2gXEk92KVwlFaLVWr1gtfKzkp/0ToQ1c6s=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=lqFbij9AxmGVu7AY5GP7jkpBpcaL4BoNYUd/ZuqpqHtSVcbpxbNYC7kgYRph4gClJIPgjbx5XJsDPRWOt/QKoXRhaI13jdBPE5q/uroaIQ2e2hmiYsrqQR7M5pwnbYntHKDBVrzoUDT0UwfoKj80Bepu2ZXcLECrMBhiS1xyS5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bXgM8zAt; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bXgM8zAt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376197; x=1805912197; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=hpBLvfVKe2gXEk92KVwlFaLVWr1gtfKzkp/0ToQ1c6s=; b=bXgM8zAtIDFIgmrGUcRxoiW3nNUfMBFgHFuZfPW8OUpQUB6MquhToITg oSYVp48rpGSxworWmSkqqvhomKZdn5rrlH3rDacxBVxxxiDpm4QznsGbF ghZsxl5cMwj7h3nKk2izhayD2UOKgzRVdZRov8bvsblIHaD8Vhr3nv5// T4IL/h/5gNDxYPnfNuAQm/YbpdLVwUIdpTuEhYqabxvq3+CNLBsSf+msc ryn4rd8IPkVPWncg8CBG/l8VGzDs/AgeXkh99sz2MYkO5CmdJp0q1SkCy +gGTAEVxY8qFMFoMRfEmqsTlSPzlTRisxn4YNoVuWGrZ1nUYArxgXwfU+ w==; X-CSE-ConnectionGUID: Lxfk0Yx/SZuv/sn18eXAug== X-CSE-MsgGUID: r2Jb4fZERhW5Ljrz6RVg9A== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="86879393" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="86879393" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:16:37 -0700 X-CSE-ConnectionGUID: 12myZWtxTzeYodboi/+sXw== X-CSE-MsgGUID: qYXCfrdjSCqtsl1dk/Dksw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="262362803" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:16:37 -0700 Date: Tue, 24 Mar 2026 11:16:36 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 01/10] x86/bhi: x86/vmscape: Move LFENCE out of clear_bhb_loop() Message-ID: <20260324-vmscape-bhb-v8-1-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, BHB clearing sequence is followed by an LFENCE to prevent transient execution of subsequent indirect branches prematurely. However, LFENCE barrier could be unnecessary in certain cases. For example, when kernel is using BHI_DIS_S mitigation, and BHB clearing is only needed for userspace. In such cases, LFENCE is redundant because ring transitions would provide the necessary serialization. Below is a quick recap of BHI mitigation options: On Alder Lake and newer - BHI_DIS_S: Hardware control to mitigate BHI in ring0. This has low performance overhead. - Long loop: Alternatively, longer version of BHB clearing sequence can be used to mitigate BHI. It can also be used to mitigate BHI variant of VMSCAPE. This is not yet implemented in Linux. On older CPUs - Short loop: Clears BHB at kernel entry and VMexit. The "Long loop" is effective on older CPUs as well, but should be avoided because of unnecessary overhead. On Alder Lake and newer CPUs, eIBRS isolates the indirect targets between guest and host. But when affected by the BHI variant of VMSCAPE, a guest's branch history may still influence indirect branches in userspace. This also means the big hammer IBPB could be replaced with a cheaper option that clears the BHB at exit-to-userspace after a VMexit. In preparation for adding the support for BHB sequence (without LFENCE) on newer CPUs, move the LFENCE to the caller side after clear_bhb_loop() is executed. Allow callers to decide whether they need the LFENCE or not. This adds a few extra bytes to the call sites, but it obviates the need for multiple variants of clear_bhb_loop(). Suggested-by: Dave Hansen Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- arch/x86/entry/entry_64.S | 5 ++++- arch/x86/include/asm/nospec-branch.h | 4 ++-- arch/x86/net/bpf_jit_comp.c | 2 ++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 42447b1e1dff..3a180a36ca0e 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1528,6 +1528,9 @@ SYM_CODE_END(rewind_stack_and_make_dead) * refactored in the future if needed. The .skips are for safety, to ensure * that all RETs are in the second half of a cacheline to mitigate Indirect * Target Selection, rather than taking the slowpath via its_return_thunk. + * + * Note, callers should use a speculation barrier like LFENCE immediately = after + * a call to this function to ensure BHB is cleared before indirect branch= es. */ SYM_FUNC_START(clear_bhb_loop) ANNOTATE_NOENDBR @@ -1562,7 +1565,7 @@ SYM_FUNC_START(clear_bhb_loop) sub $1, %ecx jnz 1b .Lret2: RET -5: lfence +5: pop %rbp RET SYM_FUNC_END(clear_bhb_loop) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 4f4b5e8a1574..70b377fcbc1c 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -331,11 +331,11 @@ =20 #ifdef CONFIG_X86_64 .macro CLEAR_BRANCH_HISTORY - ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP + ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_LOOP .endm =20 .macro CLEAR_BRANCH_HISTORY_VMEXIT - ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_VMEXIT + ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_VMEX= IT .endm #else #define CLEAR_BRANCH_HISTORY diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index e9b78040d703..63d6c9fa5e80 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1624,6 +1624,8 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *i= p, =20 if (emit_call(&prog, func, ip)) return -EINVAL; + /* Don't speculate past this until BHB is cleared */ + EMIT_LFENCE(); EMIT1(0x59); /* pop rcx */ EMIT1(0x58); /* pop rax */ } --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 074B337B400; Tue, 24 Mar 2026 18:16:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376216; cv=none; b=PPUPLRtJH/k+wyhnNtvr19R38vwqQ0BPAjLhyJTbB2/7dJRRAcXJk9ROq+vPPv4WC7vNID+CFR4g0eaEUIcJQxw62ExRUMdFzNudOOSx91G+8VFhkPiDOwYygk0R21b1wr6VB3383ayYPHxXztJoPblUZzdIaSlKWeNsOAfPbgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376216; c=relaxed/simple; bh=44kks2Hupy2PXIuwsM7N+ABSrDUKzV+bhx8Hz1JtAcg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=vFHueTxtZxiGgYp7oXY0bKaF5R6m5EW1ai84Js+JYpATTwNgNStGvznI8wan+eCzd9JHuMbPUU99p2yCqq4/qaNtmNKEuMlHlMRZ245A8cBh6OhZnRz62nQubVAQUkr6CVVPklD/e9OSAms+IjH21UlTdu7Jdmips8sq7ml5eFE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HGEuthKq; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HGEuthKq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376215; x=1805912215; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=44kks2Hupy2PXIuwsM7N+ABSrDUKzV+bhx8Hz1JtAcg=; b=HGEuthKqfi+gjw7yTlfHDr+ANsQesn+Nn76NzolLIzDQuMwRCREroWYl 7EBHqNFpBTpwTljvGwM49CTtTAD6B7RaoC7HxOmgDLJIT2r3fMK/ExXV/ sHpGsJUPOa3gcrNNqv7of2/xPbKAwg+reME708kWnS0yeqzV3ViWSR3Jl biyM5/45bYeckK5f60RB/0NePSq234vQ23ODopD1tT2cbwSyjgii0fodc nAOVZ2yt1vQoAsYYxumypwd0K+FhQlCt6AsbbCFnPwhJNjRkGsCHBYciT mID2IZ//dqhwvSmoePUZMwWElQ8TzeRUOtrTyuB96+sOnGwhV6N7N7Sod Q==; X-CSE-ConnectionGUID: X/6oGqDaQMmS2m7HFYZkPw== X-CSE-MsgGUID: Vfxugr7zTomFaVoLILCAJQ== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="79261575" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="79261575" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:16:54 -0700 X-CSE-ConnectionGUID: HFi0EA1VRl2RlV6R1Q2qYw== X-CSE-MsgGUID: xT/ewu6PToS/Hi9AYvILiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="248012771" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:16:52 -0700 Date: Tue, 24 Mar 2026 11:16:51 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 02/10] x86/bhi: Make clear_bhb_loop() effective on newer CPUs Message-ID: <20260324-vmscape-bhb-v8-2-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As a mitigation for BHI, clear_bhb_loop() executes branches that overwrites the Branch History Buffer (BHB). On Alder Lake and newer parts this sequence is not sufficient because it doesn't clear enough entries. This was not an issue because these CPUs have a hardware control (BHI_DIS_S) that mitigates BHI in kernel. BHI variant of VMSCAPE requires isolating branch history between guests and userspace. Note that there is no equivalent hardware control for userspace. To effectively isolate branch history on newer CPUs, clear_bhb_loop() should execute sufficient number of branches to clear a larger BHB. Dynamically set the loop count of clear_bhb_loop() such that it is effective on newer CPUs too. Use the hardware control enumeration X86_FEATURE_BHI_CTRL to select the appropriate loop count. Suggested-by: Dave Hansen Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- arch/x86/entry/entry_64.S | 21 ++++++++++++++++----- arch/x86/net/bpf_jit_comp.c | 7 ------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 3a180a36ca0e..8128e00ca73f 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1535,8 +1535,17 @@ SYM_CODE_END(rewind_stack_and_make_dead) SYM_FUNC_START(clear_bhb_loop) ANNOTATE_NOENDBR push %rbp + /* BPF caller may require %rax to be preserved */ + push %rax mov %rsp, %rbp - movl $5, %ecx + + /* + * Between the long and short version of BHB clear sequence, just the + * loop count differs based on BHI_CTRL, see Intel's BHI guidance. + */ + ALTERNATIVE "movb $5, %al", \ + "movb $12, %al", X86_FEATURE_BHI_CTRL + ANNOTATE_INTRA_FUNCTION_CALL call 1f jmp 5f @@ -1556,16 +1565,18 @@ SYM_FUNC_START(clear_bhb_loop) * This should be ideally be: .skip 32 - (.Lret2 - 2f), 0xcc * but some Clang versions (e.g. 18) don't like this. */ - .skip 32 - 18, 0xcc -2: movl $5, %eax + .skip 32 - 14, 0xcc +2: ALTERNATIVE "movb $5, %ah", \ + "movb $7, %ah", X86_FEATURE_BHI_CTRL 3: jmp 4f nop -4: sub $1, %eax +4: sub $1, %ah jnz 3b - sub $1, %ecx + sub $1, %al jnz 1b .Lret2: RET 5: + pop %rax pop %rbp RET SYM_FUNC_END(clear_bhb_loop) diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index 63d6c9fa5e80..e2cceabb23e8 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1614,11 +1614,6 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *= ip, u8 *func; =20 if (cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP)) { - /* The clearing sequence clobbers eax and ecx. */ - EMIT1(0x50); /* push rax */ - EMIT1(0x51); /* push rcx */ - ip +=3D 2; - func =3D (u8 *)clear_bhb_loop; ip +=3D x86_call_depth_emit_accounting(&prog, func, ip); =20 @@ -1626,8 +1621,6 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *i= p, return -EINVAL; /* Don't speculate past this until BHB is cleared */ EMIT_LFENCE(); - EMIT1(0x59); /* pop rcx */ - EMIT1(0x58); /* pop rax */ } /* Insert IBHF instruction */ if ((cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP) && --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 851BB239085; Tue, 24 Mar 2026 18:17:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; 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a="79261618" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="79261618" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:17:11 -0700 X-CSE-ConnectionGUID: W6YWY8GASRuxikTg4ITE4A== X-CSE-MsgGUID: RtHPMjR4QvyVbXVE5cxNHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="248012822" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:17:09 -0700 Date: Tue, 24 Mar 2026 11:17:09 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 03/10] x86/bhi: Rename clear_bhb_loop() to clear_bhb_loop_nofence() Message-ID: <20260324-vmscape-bhb-v8-3-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To reflect the recent change that moved LFENCE to the caller side. Suggested-by: Borislav Petkov Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- arch/x86/entry/entry_64.S | 8 ++++---- arch/x86/include/asm/nospec-branch.h | 6 +++--- arch/x86/net/bpf_jit_comp.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 8128e00ca73f..e9b81b95fcc8 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1532,7 +1532,7 @@ SYM_CODE_END(rewind_stack_and_make_dead) * Note, callers should use a speculation barrier like LFENCE immediately = after * a call to this function to ensure BHB is cleared before indirect branch= es. */ -SYM_FUNC_START(clear_bhb_loop) +SYM_FUNC_START(clear_bhb_loop_nofence) ANNOTATE_NOENDBR push %rbp /* BPF caller may require %rax to be preserved */ @@ -1579,6 +1579,6 @@ SYM_FUNC_START(clear_bhb_loop) pop %rax pop %rbp RET -SYM_FUNC_END(clear_bhb_loop) -EXPORT_SYMBOL_FOR_KVM(clear_bhb_loop) -STACK_FRAME_NON_STANDARD(clear_bhb_loop) +SYM_FUNC_END(clear_bhb_loop_nofence) +EXPORT_SYMBOL_FOR_KVM(clear_bhb_loop_nofence) +STACK_FRAME_NON_STANDARD(clear_bhb_loop_nofence) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 70b377fcbc1c..0f5e6ed6c9c2 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -331,11 +331,11 @@ =20 #ifdef CONFIG_X86_64 .macro CLEAR_BRANCH_HISTORY - ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_LOOP + ALTERNATIVE "", "call clear_bhb_loop_nofence; lfence", X86_FEATURE_CLEAR_= BHB_LOOP .endm =20 .macro CLEAR_BRANCH_HISTORY_VMEXIT - ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_VMEX= IT + ALTERNATIVE "", "call clear_bhb_loop_nofence; lfence", X86_FEATURE_CLEAR_= BHB_VMEXIT .endm #else #define CLEAR_BRANCH_HISTORY @@ -389,7 +389,7 @@ extern void entry_untrain_ret(void); extern void write_ibpb(void); =20 #ifdef CONFIG_X86_64 -extern void clear_bhb_loop(void); +extern void clear_bhb_loop_nofence(void); #endif =20 extern void (*x86_return_thunk)(void); diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index e2cceabb23e8..b57e9ab51c5d 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1614,7 +1614,7 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *i= p, u8 *func; =20 if (cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP)) { - func =3D (u8 *)clear_bhb_loop; + func =3D (u8 *)clear_bhb_loop_nofence; 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24 Mar 2026 11:17:26 -0700 Date: Tue, 24 Mar 2026 11:17:25 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 04/10] x86/vmscape: Rename x86_ibpb_exit_to_user to x86_predictor_flush_exit_to_user Message-ID: <20260324-vmscape-bhb-v8-4-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the upcoming changes x86_ibpb_exit_to_user will also be used when BHB clearing sequence is used. Rename it cover both the cases. No functional change. Suggested-by: Sean Christopherson Signed-off-by: Pawan Gupta Acked-by: Sean Christopherson Tested-By: Jon Kohler --- arch/x86/include/asm/entry-common.h | 6 +++--- arch/x86/include/asm/nospec-branch.h | 2 +- arch/x86/kernel/cpu/bugs.c | 4 ++-- arch/x86/kvm/x86.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index ce3eb6d5fdf9..c45858db16c9 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -94,11 +94,11 @@ static inline void arch_exit_to_user_mode_prepare(struc= t pt_regs *regs, */ choose_random_kstack_offset(rdtsc()); =20 - /* Avoid unnecessary reads of 'x86_ibpb_exit_to_user' */ + /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && - this_cpu_read(x86_ibpb_exit_to_user)) { + this_cpu_read(x86_predictor_flush_exit_to_user)) { indirect_branch_prediction_barrier(); - this_cpu_write(x86_ibpb_exit_to_user, false); + this_cpu_write(x86_predictor_flush_exit_to_user, false); } } #define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 0f5e6ed6c9c2..0a55b1c64741 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -533,7 +533,7 @@ void alternative_msr_write(unsigned int msr, u64 val, u= nsigned int feature) : "memory"); } =20 -DECLARE_PER_CPU(bool, x86_ibpb_exit_to_user); +DECLARE_PER_CPU(bool, x86_predictor_flush_exit_to_user); =20 static inline void indirect_branch_prediction_barrier(void) { diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 83f51cab0b1e..47c020b80371 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -65,8 +65,8 @@ EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); * be needed to before running userspace. That IBPB will flush the branch * predictor content. */ -DEFINE_PER_CPU(bool, x86_ibpb_exit_to_user); -EXPORT_PER_CPU_SYMBOL_GPL(x86_ibpb_exit_to_user); +DEFINE_PER_CPU(bool, x86_predictor_flush_exit_to_user); +EXPORT_PER_CPU_SYMBOL_GPL(x86_predictor_flush_exit_to_user); =20 u64 x86_pred_cmd __ro_after_init =3D PRED_CMD_IBPB; =20 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index fd1c4a36b593..45d7cfedc507 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11464,7 +11464,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) * may migrate to. */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER)) - this_cpu_write(x86_ibpb_exit_to_user, true); + this_cpu_write(x86_predictor_flush_exit_to_user, true); =20 /* * Consume any pending interrupts, including the possible source of --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C11037CD4F; Tue, 24 Mar 2026 18:17:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376265; cv=none; b=gh0Mdq/Kbr3cLZ8frmVUogJwcF41HJdhaZfw0LWu0OrGMcNHDNuHEOhyNOhoefbFvzMgYuLA2TwAS5kRPzsuiRtIpb43CHolRuCYnoDUfFU6LScsdVFKClQ3SBMziSVPW700qlAVc5FBsB1+8f2anC6jGH6K5myt88eIn2S+vZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376265; c=relaxed/simple; bh=iKbYaTDuUMcCWsnSDj/iaOVKUwO2Qpaue4niM52YYmE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Lfua7nYaUG957vF20lsUN9mJfZlGRJFq15nzX5K5cHMOId6IJ7aqO1acO8fSn5n6YbRWqM4Vrvu0WmzRTAzxD0jV9Yblyeyp23av1kJsDpw98fwWudjhfCa4ASRzbf1xnWB15ZNikLLVFtkOGC/tSiIopG4A0KuP9NcSGYrJJyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TMy+eA9K; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TMy+eA9K" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376263; x=1805912263; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=iKbYaTDuUMcCWsnSDj/iaOVKUwO2Qpaue4niM52YYmE=; b=TMy+eA9KxcPR4IYemwOD3FadN6ClYWie+S8/uh2u0+aYEmkW4c/Bi3Gt VTcnCqJ7Quwi9mNdqlisOLia4aQSNsWGjxqp+kpyMwFleNVhZIZqTm/bD /RrCWgzt2MtqXmyW1jMq5JsVm9ml4BzZ+Vd65MuuQ3wGSPlue4XDWFnMZ vI0MTTBY00tCSYXbQ8lCTuOCS1iEgNPojbDODbZe0O2Vz2ThF+dSOY1Qu DRjG8ww+9ezqbUIFVW8IBvfzPJCzSTbcGDD5nGsucHghK806AmG/YMtzD ysa8LRSLElhh5WBlsry5+5djIKagoS73YV+PjvCQNgUYAg3inlYOFdq1x A==; X-CSE-ConnectionGUID: 31iMJ4IIQsysbWFra6uHcA== X-CSE-MsgGUID: VroQMhoKTGSCCWgZuVLkUg== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="86479970" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="86479970" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:17:42 -0700 X-CSE-ConnectionGUID: zgdaje3hSoeNZiG9eprngQ== X-CSE-MsgGUID: Gy+6QpTmQrSaRUz73o2pqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="217858388" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:17:42 -0700 Date: Tue, 24 Mar 2026 11:17:41 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 05/10] x86/vmscape: Move mitigation selection to a switch() Message-ID: <20260324-vmscape-bhb-v8-5-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This ensures that all mitigation modes are explicitly handled, while keeping the mitigation selection for each mode together. This also prepares for adding BHB-clearing mitigation mode for VMSCAPE. Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- arch/x86/kernel/cpu/bugs.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 47c020b80371..68e2df3e3bf5 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3084,17 +3084,33 @@ early_param("vmscape", vmscape_parse_cmdline); =20 static void __init vmscape_select_mitigation(void) { - if (!boot_cpu_has_bug(X86_BUG_VMSCAPE) || - !boot_cpu_has(X86_FEATURE_IBPB)) { + if (!boot_cpu_has_bug(X86_BUG_VMSCAPE)) { vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; return; } =20 - if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_AUTO) { - if (should_mitigate_vuln(X86_BUG_VMSCAPE)) + if ((vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_AUTO) && + !should_mitigate_vuln(X86_BUG_VMSCAPE)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + + switch (vmscape_mitigation) { + case VMSCAPE_MITIGATION_NONE: + break; + + case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: + if (!boot_cpu_has(X86_FEATURE_IBPB)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + break; + + case VMSCAPE_MITIGATION_AUTO: + if (boot_cpu_has(X86_FEATURE_IBPB)) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; else vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + break; + + default: + break; } } =20 --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3133DCA52; Tue, 24 Mar 2026 18:17:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376280; cv=none; b=fgsrk0cIwU2yq+15kHqBhmo8biN3/7kUUeUlCdibJXRuYtzyWuxB3Fka28STTNgcTnWb/KHFpj8GKYOPQ8IX5vI29YUy+pBj6SY9DJl+7Tzc9tkEsN8yxz4wyudD++iYLUq38wXtTyCvwGEtAGlUgLsui3YY5X37yNibOvwiJlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376280; c=relaxed/simple; bh=7cJ6sjEbP/Ga7TlX9Dfhyujzs7TDJzczjuzBKjjVTK0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=SRyyy4nJptEqtU/GfjjPgfyzvLyxMJitscUvd5FqCQMAed+fo7OY9jiSch2kgM+P2/Q/MgDNiO84VaS05WdzFuFLNUVSJPhDIYRUTtaNQa6JPnx1bCgadmjpcsHVC+8LzdDs9GMS93Gr56Oeodm7tYu1Q1JYWJjlMZATfEVxWmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ge1nEx1Z; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ge1nEx1Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376278; x=1805912278; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=7cJ6sjEbP/Ga7TlX9Dfhyujzs7TDJzczjuzBKjjVTK0=; b=ge1nEx1ZFNCVLKLjTc35iESeTGJmHtdk0A4ZAT3ewBRcOh4V9hy1qp1r 2a+5XXhOuuFRUSDjGPpON7To2KzVg33l5KPhBwODN7z6E7NB+8lquU35j 0DlAgph+1nLcpvd7UY2SmE3m9oQTLLakhbJDFhly/a8d3Qv2a3imP5Mz6 4zVKvZgzq3agMtCu4A/eJwYQGGhqfiuVhY2QonuWT2YuVtHtdQwyuL+0r 1s0Y3QNjy06YuN/gKR/LbddLAmqWDNtvfGcdb9BQVTPHoPAhAG7Lt8uFs 2WNwZ7i5oVxD95jkSkCQN90XmVmV6UTlkwk7JkMdhaGkGcs3AHFkqQwmb g==; X-CSE-ConnectionGUID: B0K68buAQP2Vq6/cHR2bQA== X-CSE-MsgGUID: tfL3yuS8TrS7oQtvCAIrMw== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="79000951" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="79000951" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:17:57 -0700 X-CSE-ConnectionGUID: OjpqPBbaQei+bNjUoRhz1g== X-CSE-MsgGUID: uwRdaqKcTP+zWrxosEGgtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="224443620" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:17:59 -0700 Date: Tue, 24 Mar 2026 11:17:58 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 06/10] x86/vmscape: Use write_ibpb() instead of indirect_branch_prediction_barrier() Message-ID: <20260324-vmscape-bhb-v8-6-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" indirect_branch_prediction_barrier() is a wrapper to write_ibpb(), which also checks if the CPU supports IBPB. For VMSCAPE, call to indirect_branch_prediction_barrier() is only possible when CPU supports IBPB. Simply call write_ibpb() directly to avoid unnecessary alternative patching. Suggested-by: Dave Hansen Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- arch/x86/include/asm/entry-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index c45858db16c9..78b143673ca7 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -97,7 +97,7 @@ static inline void arch_exit_to_user_mode_prepare(struct = pt_regs *regs, /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && this_cpu_read(x86_predictor_flush_exit_to_user)) { - indirect_branch_prediction_barrier(); + write_ibpb(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } } --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FD3E37DEA0; Tue, 24 Mar 2026 18:18:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376295; cv=none; b=obEDgGpBh32U4jxTyVNrjvqPlRu3yUn6cmTirMJ8MDm6Q4l9sBBFosk7v4sx8TJanBEC/TJAcZmWWy8iGsPJM9dWp8XPx37qnkPJZ8ANtTx1VoIJnykEGGEfrIUNoQKxnM+CkaQGVI9XQr2Q049F9woFroFTVDBviRu1X/XcaLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376295; c=relaxed/simple; bh=BfGqaoPByCgcbN0j0dFpAGziltvkHNZ8Ap33MPYcA44=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=igKH/IkjK9xoRVVteqfj83RgGMovmoRABYlVyMMe12kuUSjvo6mgs1xRjph4hhzCHWbYSHTv2WneLHH1hCZ5+BTvLMWuoLy78zz1cjY0zLVWQzCfMidIMwCe8VbGo3KpowADBYbrpsmVoxaJGuPZbTngHgaAhQaZV/rryMYHeb0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=W99TnVbE; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="W99TnVbE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376293; x=1805912293; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=BfGqaoPByCgcbN0j0dFpAGziltvkHNZ8Ap33MPYcA44=; b=W99TnVbE3ZZNke+Cvc3UfiQSatHCIzbbutIZ26vOrqqxwb3x8VcsAHOJ M86NToXkRotQ3cPLTHS2wkuuNmIRL9BCNYZF+M+0k0E5Z6DKla89SQYue 0iRalyH4VnOE969rA9ooO8MVRvu9A44A1NTKsNLtt7+lnIC8o+BZMOsWn /n2d3zr0EtyW+v9AMQzah9/IdW6KoRF8tDS7YdTeHX4BzJhK+RBBThWn2 yjzW8ibCw+s2ZxNsnL3RHU61Lgr1/8KUeXA/7X+pBncSs7gLkxhF8De3n ScswlCAhzRpQlKnmnMaA/67N+4FI3Zrg74719GxtZezxUKkxTUhPAK9lt g==; X-CSE-ConnectionGUID: epvPKMyaSNCaeNTzgr9jUQ== X-CSE-MsgGUID: EkZ4O4wuQeGu7efRooZmxw== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="79001013" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="79001013" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:18:13 -0700 X-CSE-ConnectionGUID: PC0+nKMlSfu2jSbHqz99Dw== X-CSE-MsgGUID: bNPjS4C8Qb2R9CTIIOOLTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="224443670" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:18:14 -0700 Date: Tue, 24 Mar 2026 11:18:13 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 07/10] x86/vmscape: Use static_call() for predictor flush Message-ID: <20260324-vmscape-bhb-v8-7-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adding more mitigation options at exit-to-userspace for VMSCAPE would usually require a series of checks to decide which mitigation to use. In this case, the mitigation is done by calling a function, which is decided at boot. So, adding more feature flags and multiple checks can be avoided by using static_call() to the mitigating function. Replace the flag-based mitigation selector with a static_call(). This also frees the existing X86_FEATURE_IBPB_EXIT_TO_USER. Suggested-by: Dave Hansen Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- arch/x86/Kconfig | 1 + arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/entry-common.h | 7 +++---- arch/x86/include/asm/nospec-branch.h | 3 +++ arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/bugs.c | 14 +++++++++++++- arch/x86/kvm/x86.c | 2 +- 7 files changed, 23 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e2df1b147184..5b8def9ddb98 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2720,6 +2720,7 @@ config MITIGATION_TSA config MITIGATION_VMSCAPE bool "Mitigate VMSCAPE" depends on KVM + depends on HAVE_STATIC_CALL default y help Enable mitigation for VMSCAPE attacks. VMSCAPE is a hardware security diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dbe104df339b..b4d529dd6d30 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -503,7 +503,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ -#define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-us= erspace, see VMSCAPE bug */ +/* Free */ #define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Co= unters */ #define X86_FEATURE_MSR_IMM (21*32+16) /* MSR immediate form instructions= */ #define X86_FEATURE_SGX_EUPDATESVN (21*32+17) /* Support for ENCLS[EUPDATE= SVN] instruction */ diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index 78b143673ca7..783e7cb50cae 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #include #include @@ -94,10 +95,8 @@ static inline void arch_exit_to_user_mode_prepare(struct= pt_regs *regs, */ choose_random_kstack_offset(rdtsc()); =20 - /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ - if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && - this_cpu_read(x86_predictor_flush_exit_to_user)) { - write_ibpb(); + if (unlikely(this_cpu_read(x86_predictor_flush_exit_to_user))) { + static_call_cond(vmscape_predictor_flush)(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } } diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 0a55b1c64741..e45e49f1e0c9 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -542,6 +542,9 @@ static inline void indirect_branch_prediction_barrier(v= oid) :: "rax", "rcx", "rdx", "memory"); } =20 +#include +DECLARE_STATIC_CALL(vmscape_predictor_flush, write_ibpb); + /* The Intel SPEC CTRL MSR base value cache */ extern u64 x86_spec_ctrl_base; DECLARE_PER_CPU(u64, x86_spec_ctrl_current); diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index a24c7805acdb..20ab4dd588c6 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -753,6 +753,7 @@ enum mds_mitigations { }; =20 extern bool gds_ucode_mitigated(void); +extern bool vmscape_mitigation_enabled(void); =20 /* * Make previous memory operations globally visible before diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 68e2df3e3bf5..a7dee7ec6ea3 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -144,6 +144,12 @@ EXPORT_SYMBOL_GPL(cpu_buf_idle_clear); */ DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); =20 +/* + * Controls how vmscape is mitigated e.g. via IBPB or BHB-clear + * sequence. This defaults to no mitigation. + */ +DEFINE_STATIC_CALL_NULL(vmscape_predictor_flush, write_ibpb); + #undef pr_fmt #define pr_fmt(fmt) "mitigations: " fmt =20 @@ -3129,8 +3135,14 @@ static void __init vmscape_update_mitigation(void) static void __init vmscape_apply_mitigation(void) { if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER) - setup_force_cpu_cap(X86_FEATURE_IBPB_EXIT_TO_USER); + static_call_update(vmscape_predictor_flush, write_ibpb); +} + +bool vmscape_mitigation_enabled(void) +{ + return !!static_call_query(vmscape_predictor_flush); } +EXPORT_SYMBOL_FOR_KVM(vmscape_mitigation_enabled); =20 #undef pr_fmt #define pr_fmt(fmt) fmt diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 45d7cfedc507..e204482e64f3 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11463,7 +11463,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) * set for the CPU that actually ran the guest, and not the CPU that it * may migrate to. */ - if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER)) + if (vmscape_mitigation_enabled()) this_cpu_write(x86_predictor_flush_exit_to_user, true); =20 /* --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D63C537F733; Tue, 24 Mar 2026 18:18:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376312; cv=none; b=QwfmZ+p+nuqpM0OGTVtGh8CM06jnH8OFziAuv3xWv+QuOkIrf0Z8PEDanAEqci+Gyx428B7ukksP3t+hkNISBu4C7j8yERCZBJGffHc2lgot2m4Apkr9FaZ89dCZpy4KGsNtu/JSB0CdKiWyhA8KWR66J0xbFWJWvgBbf7gOjPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376312; c=relaxed/simple; bh=5O7npA2R+PTs11/qeBAXfNz7xHj3j/vBMPYhM+J1ZLM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=VpRvhypd+POzTJMxlVFlT3UoQyCsmNrUc5WMl1rp3HaQ/llBiGYsay85ovGEld4BAj6K/8lQ4ngoQHxMSZdFfmQKd3d2zK2J/MGLYjZMQs+5SDF96WYo6WK5tEDKqbg5glaqS9vpqGBexEIW3N1BkoD+hOnu47PxbrlOfBRbhZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KGurPd8j; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KGurPd8j" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376311; x=1805912311; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=5O7npA2R+PTs11/qeBAXfNz7xHj3j/vBMPYhM+J1ZLM=; b=KGurPd8j8IQcu+XlyaVIp7X4Y/s991JrvtGBcNAWZ6n/n8ubnqyH5cfl 4WXgoFsNrlUhVaAmvyP5v1olugu4oNljMx4E0GzXphRc2x6onT7W+Rlp8 LzyrZynSP5akpDPk3TJMtC1natClvSxeiW1cB5SKLMWwfXAhRIXcaffdE Tv6rcv64aFV+4TmEHdYP6fyzORL7Y09a1Eqenfmz+t6QV+3ELRNIdQfTS +Vb4SB7gEFnpPd6z6UDNTRfHxJoIBmI80Wtv67korPef6Xih6L0ZGpKbU s8txN5QvkOcKoghwmxAnrH/eB8Du0f8P1nL85Wa//legDM1ai0Fjg+sqi g==; X-CSE-ConnectionGUID: bDhvreBgSZSk4dJAnZW3SQ== X-CSE-MsgGUID: HKYfVIPLTLumRqMsRSnPGQ== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="74429569" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="74429569" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:18:30 -0700 X-CSE-ConnectionGUID: acNsU9AwSh6JnrYGgX7m4g== X-CSE-MsgGUID: DdX15JbnSfGtiWGiWJ25zA== X-ExtLoop1: 1 Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:18:29 -0700 Date: Tue, 24 Mar 2026 11:18:28 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 08/10] x86/vmscape: Deploy BHB clearing mitigation Message-ID: <20260324-vmscape-bhb-v8-8-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" IBPB mitigation for VMSCAPE is an overkill on CPUs that are only affected by the BHI variant of VMSCAPE. On such CPUs, eIBRS already provides indirect branch isolation between guest and host userspace. However, branch history from guest may also influence the indirect branches in host userspace. To mitigate the BHI aspect, use the BHB clearing sequence. Since now, IBPB is not the only mitigation for VMSCAPE, update the documentation to reflect that =3Dauto could select either IBPB or BHB clear mitigation based on the CPU. Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- Documentation/admin-guide/hw-vuln/vmscape.rst | 11 ++++++++- Documentation/admin-guide/kernel-parameters.txt | 4 +++- arch/x86/include/asm/nospec-branch.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 30 +++++++++++++++++++--= ---- 4 files changed, 38 insertions(+), 9 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/vmscape.rst b/Documentation/= admin-guide/hw-vuln/vmscape.rst index d9b9a2b6c114..7c40cf70ad7a 100644 --- a/Documentation/admin-guide/hw-vuln/vmscape.rst +++ b/Documentation/admin-guide/hw-vuln/vmscape.rst @@ -86,6 +86,10 @@ The possible values in this file are: run a potentially malicious guest and issues an IBPB before the first exit to userspace after VM-exit. =20 + * 'Mitigation: Clear BHB before exit to userspace': + + As above, conditional BHB clearing mitigation is enabled. + * 'Mitigation: IBPB on VMEXIT': =20 IBPB is issued on every VM-exit. This occurs when other mitigations like @@ -102,9 +106,14 @@ The mitigation can be controlled via the ``vmscape=3D`= ` command line parameter: =20 * ``vmscape=3Dibpb``: =20 - Enable conditional IBPB mitigation (default when CONFIG_MITIGATION_VMSC= APE=3Dy). + Enable conditional IBPB mitigation. =20 * ``vmscape=3Dforce``: =20 Force vulnerability detection and mitigation even on processors that are not known to be affected. + + * ``vmscape=3Dauto``: + + Choose the mitigation based on the VMSCAPE variant the CPU is affected = by. + (default when CONFIG_MITIGATION_VMSCAPE=3Dy) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 03a550630644..3853c7109419 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -8378,9 +8378,11 @@ Kernel parameters =20 off - disable the mitigation ibpb - use Indirect Branch Prediction Barrier - (IBPB) mitigation (default) + (IBPB) mitigation force - force vulnerability detection even on unaffected processors + auto - (default) use IBPB or BHB clear + mitigation based on CPU =20 vsyscall=3D [X86-64,EARLY] Controls the behavior of vsyscalls (i.e. calls to diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index e45e49f1e0c9..7be812a73326 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -390,6 +390,8 @@ extern void write_ibpb(void); =20 #ifdef CONFIG_X86_64 extern void clear_bhb_loop_nofence(void); +#else +static inline void clear_bhb_loop_nofence(void) {} #endif =20 extern void (*x86_return_thunk)(void); diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index a7dee7ec6ea3..8cacd9474fdf 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -61,9 +61,8 @@ DEFINE_PER_CPU(u64, x86_spec_ctrl_current); EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); =20 /* - * Set when the CPU has run a potentially malicious guest. An IBPB will - * be needed to before running userspace. That IBPB will flush the branch - * predictor content. + * Set when the CPU has run a potentially malicious guest. Indicates that a + * branch predictor flush is needed before running userspace. */ DEFINE_PER_CPU(bool, x86_predictor_flush_exit_to_user); EXPORT_PER_CPU_SYMBOL_GPL(x86_predictor_flush_exit_to_user); @@ -3056,13 +3055,15 @@ enum vmscape_mitigations { VMSCAPE_MITIGATION_AUTO, VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER, VMSCAPE_MITIGATION_IBPB_ON_VMEXIT, + VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER, }; =20 static const char * const vmscape_strings[] =3D { - [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", + [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", /* [VMSCAPE_MITIGATION_AUTO] */ - [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit = to userspace", - [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", + [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit= to userspace", + [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", + [VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER] =3D "Mitigation: Clear BHB be= fore exit to userspace", }; =20 static enum vmscape_mitigations vmscape_mitigation __ro_after_init =3D @@ -3080,6 +3081,8 @@ static int __init vmscape_parse_cmdline(char *str) } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; + } else if (!strcmp(str, "auto")) { + vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { pr_err("Ignoring unknown vmscape=3D%s option.\n", str); } @@ -3109,7 +3112,17 @@ static void __init vmscape_select_mitigation(void) break; =20 case VMSCAPE_MITIGATION_AUTO: - if (boot_cpu_has(X86_FEATURE_IBPB)) + /* + * CPUs with BHI_CTRL(ADL and newer) can avoid the IBPB and use + * BHB clear sequence. These CPUs are only vulnerable to the BHI + * variant of the VMSCAPE attack, and thus they do not require a + * full predictor flush. + * + * Note, in 32-bit mode BHB clear sequence is not supported. + */ + if (boot_cpu_has(X86_FEATURE_BHI_CTRL) && IS_ENABLED(CONFIG_X86_64)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER; + else if (boot_cpu_has(X86_FEATURE_IBPB)) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; else vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; @@ -3136,6 +3149,8 @@ static void __init vmscape_apply_mitigation(void) { if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER) static_call_update(vmscape_predictor_flush, write_ibpb); + else if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_U= SER) + static_call_update(vmscape_predictor_flush, clear_bhb_loop_nofence); } =20 bool vmscape_mitigation_enabled(void) @@ -3233,6 +3248,7 @@ void cpu_bugs_smt_update(void) break; case VMSCAPE_MITIGATION_IBPB_ON_VMEXIT: case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: + case VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER: /* * Hypervisors can be attacked across-threads, warn for SMT when * STIBP is not already enabled system-wide. --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22757387356; Tue, 24 Mar 2026 18:18:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376328; cv=none; b=WjhTIWM2mf9zwFeOZ+cxkUDCFpXYKQHz2zQhdGUhmhDFOGrYeIOl0DkKuNwpeNDfVtNO6POcdLBZYOs4jhcBt19xhsKL4V7ilBm8xIchTV+zsmeNK40hhQNVAECSRqz8qYAOtOo8LHJdJdWtVYMqFUvnphK7OILBd5CjnSkTlGA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376328; c=relaxed/simple; bh=/LpaN8rl4GCEDdEvnTvtBW4O1Y6doVjK38xWXFBBDrQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=tHKzLQizHK0TKiCCDGyi5Ri/5tmI89NvCrw63oau30NREQ0f8fqIsP3qY6f02UwDK0YyHZUL7AuCgXd6VV5FIiz0rZnPZWnXs2MYA6YUy745/xt0JKQ2QMIC4nCZSYvyWy/r2x3ve0l8K/MUJ+/Mzz91gJGSq6+iLOr+9Uj4ITY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DgdNAnII; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DgdNAnII" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376327; x=1805912327; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=/LpaN8rl4GCEDdEvnTvtBW4O1Y6doVjK38xWXFBBDrQ=; b=DgdNAnIIwBuNrnlWGSJ8nsX5eXzLdXeTGZG9D7nQBqK6cornIGDjb7aB x6a/zJhxuXZPvpGP5CTIyDrudKXCgYAFMCgMoSRtdYNRkKfAym7rcBBLN NkObbRcBIfM+ltTOaTg3YbmBOm9cnMywYYUMBL8Z8KWW2EeNWlCfQLXvN cLv/jafVp/SOaDePEWIBkgEevEYEczPZznitT8JPu5qPP3ZUNLPlStzoz HZxCNV6VBoiB/zQ8GvWQwJY4NlvNg6tkMLizg5yZFdmWqL4JxzHXKzEhe k0LXcy6hnCRAxt2YNZeL9k0kYvA9UJxfjiA9fbBds4pNYNsniqEgUUE9J Q==; X-CSE-ConnectionGUID: ympmxbquTIKYdD/VVwUluw== X-CSE-MsgGUID: BB81UbcfS3ey6wzWO9HF/Q== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="74429599" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="74429599" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:18:47 -0700 X-CSE-ConnectionGUID: 0E2tp4xnR86/WS0a5+ZwGw== X-CSE-MsgGUID: dnjGq3PESKyOF94JbD0moQ== X-ExtLoop1: 1 Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:18:45 -0700 Date: Tue, 24 Mar 2026 11:18:44 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 09/10] x86/vmscape: Resolve conflict between attack-vectors and vmscape=force Message-ID: <20260324-vmscape-bhb-v8-9-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" vmscape=3Dforce option currently defaults to AUTO mitigation. This lets attack-vector controls to override the vmscape mitigation. Preventing the user from being able to force VMSCAPE mitigation. When vmscape mitigation is forced, allow it be deployed irrespective of attack vectors. Introduce VMSCAPE_MITIGATION_ON that wins over attack-vector controls. Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- arch/x86/kernel/cpu/bugs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 8cacd9474fdf..ba714f600249 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3053,6 +3053,7 @@ static void __init srso_apply_mitigation(void) enum vmscape_mitigations { VMSCAPE_MITIGATION_NONE, VMSCAPE_MITIGATION_AUTO, + VMSCAPE_MITIGATION_ON, VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER, VMSCAPE_MITIGATION_IBPB_ON_VMEXIT, VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER, @@ -3061,6 +3062,7 @@ enum vmscape_mitigations { static const char * const vmscape_strings[] =3D { [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", /* [VMSCAPE_MITIGATION_AUTO] */ + /* [VMSCAPE_MITIGATION_ON] */ [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit= to userspace", [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", [VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER] =3D "Mitigation: Clear BHB be= fore exit to userspace", @@ -3080,7 +3082,7 @@ static int __init vmscape_parse_cmdline(char *str) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); - vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; + vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; } else if (!strcmp(str, "auto")) { vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { @@ -3112,6 +3114,7 @@ static void __init vmscape_select_mitigation(void) break; =20 case VMSCAPE_MITIGATION_AUTO: + case VMSCAPE_MITIGATION_ON: /* * CPUs with BHI_CTRL(ADL and newer) can avoid the IBPB and use * BHB clear sequence. These CPUs are only vulnerable to the BHI @@ -3245,6 +3248,7 @@ void cpu_bugs_smt_update(void) switch (vmscape_mitigation) { case VMSCAPE_MITIGATION_NONE: case VMSCAPE_MITIGATION_AUTO: + case VMSCAPE_MITIGATION_ON: break; case VMSCAPE_MITIGATION_IBPB_ON_VMEXIT: case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: --=20 2.34.1 From nobody Fri Apr 3 01:08:33 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 003E537DEA0; Tue, 24 Mar 2026 18:19:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376345; cv=none; b=BxoklGB/0pV9NKD1iCof3Bm1cdVesO+NOgsvImrqAT/bCQougYloeOEBwPhsRNhRXKB3VMC2b4lIjmI6c420rxRf2cr00oC1BwCEpIC0fsxhsGFk9VRtbXVTuJXRBC3tJY8LxVwibwFf2sHibR8TE7r8ul22b6y3z9mkvyC9dVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774376345; c=relaxed/simple; bh=tJKPFoTE04b29dqHeQZIy36ufkX7uRuyKW9NSMZZOE4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=sLGetAlkm+f63DHG1s57GqXXr4P2Nqe3se8YG5km7QF5r9aStbsU0VcffzJxJoTErLS3+A+bBmfXxsjt+D/Qu47K88wmbs68+1DFrkLHTmMDY4ft30ZdDdBiic1LS9lkLJ2FCXiQHNRfYvBqH0fItLTSHSZCjxx0IvJIim1GhdU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XMXvE67a; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XMXvE67a" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774376343; x=1805912343; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=tJKPFoTE04b29dqHeQZIy36ufkX7uRuyKW9NSMZZOE4=; b=XMXvE67alTmY0b8weYjGVyOiX0QFxGpYvaAvAvEh/yqBUUnPBvkIxCdI nPQeMv8atEneuQDPfCUsGs83XK5bGrsvIOEBJymwGHS+Urgxch5aI+8o1 j24yC4DLJCMQHjsp9+gnhVT2TfK2ICQuDboVh5ah+7ACR8+3hzF6uoqmT LCsjwpOh6pHVbl5A2yz620MRSQP467ypiCsyroV0uq0Kcmz1/kD7smAlm g41B0W+c2V3b9LvshMmWAHb31TvaJJPRCmD3HXLXSNj5VA3CVePDfPSQ4 FXs1N41J+jE5W94Mi7ffVW0tXQfxY5oovEb2dMrcLKEB0hLOoQdGfzzUk Q==; X-CSE-ConnectionGUID: fB6pw53HTue8cRQjJGqEwA== X-CSE-MsgGUID: 0eBc547jRxOPDmOPTBXAUQ== X-IronPort-AV: E=McAfee;i="6800,10657,11739"; a="79001149" X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="79001149" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:19:02 -0700 X-CSE-ConnectionGUID: whTIKQ1dTJenyzHLYJZAdg== X-CSE-MsgGUID: 7EdO1p2ZR36PRWrpLZAIIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,138,1770624000"; d="scan'208";a="226066052" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2026 11:19:01 -0700 Date: Tue, 24 Mar 2026 11:19:01 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v8 10/10] x86/vmscape: Add cmdline vmscape=on to override attack vector controls Message-ID: <20260324-vmscape-bhb-v8-10-68bb524b3ab9@linux.intel.com> X-Mailer: b4 0.15-dev References: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260324-vmscape-bhb-v8-0-68bb524b3ab9@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In general, individual mitigation knobs override the attack vector controls. For VMSCAPE, =3Dibpb exists but nothing to select BHB clearing mitigation. The =3Dforce option would select BHB clearing when supported, b= ut with a side-effect of also forcing the bug, hence deploying the mitigation on unaffected parts too. Add a new cmdline option vmscape=3Don to enable the mitigation based on the VMSCAPE variant the CPU is affected by. Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta Tested-By: Jon Kohler --- Documentation/admin-guide/hw-vuln/vmscape.rst | 4 ++++ Documentation/admin-guide/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/bugs.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/Documentation/admin-guide/hw-vuln/vmscape.rst b/Documentation/= admin-guide/hw-vuln/vmscape.rst index 7c40cf70ad7a..a15d1bc91cce 100644 --- a/Documentation/admin-guide/hw-vuln/vmscape.rst +++ b/Documentation/admin-guide/hw-vuln/vmscape.rst @@ -117,3 +117,7 @@ The mitigation can be controlled via the ``vmscape=3D``= command line parameter: =20 Choose the mitigation based on the VMSCAPE variant the CPU is affected = by. (default when CONFIG_MITIGATION_VMSCAPE=3Dy) + + * ``vmscape=3Don``: + + Same as `auto`, except that it overrides attack vector controls. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 3853c7109419..98204d464477 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -8383,6 +8383,8 @@ Kernel parameters unaffected processors auto - (default) use IBPB or BHB clear mitigation based on CPU + on - same as "auto", but override attack + vector control =20 vsyscall=3D [X86-64,EARLY] Controls the behavior of vsyscalls (i.e. calls to diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ba714f600249..84bf89ca278b 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3083,6 +3083,8 @@ static int __init vmscape_parse_cmdline(char *str) } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; + } else if (!strcmp(str, "on")) { + vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; } else if (!strcmp(str, "auto")) { vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { --=20 2.34.1