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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a285207454sm3162823e87.48.2026.03.24.06.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 06:54:41 -0700 (PDT) From: Marcus Folkesson Date: Tue, 24 Mar 2026 14:54:16 +0100 Subject: [PATCH v9 2/5] i2c: mux: add support for per channel bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260324-i2c-mux-v9-2-5292b0608243@gmail.com> References: <20260324-i2c-mux-v9-0-5292b0608243@gmail.com> In-Reply-To: <20260324-i2c-mux-v9-0-5292b0608243@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7627; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=zzwP/dH6nVUsUc4kUSRaQrWbWPe+IT1e5Ig8MAfNhhE=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpwpeS17UHmxhJ8CGOEdifxF/PD0KJwhBW/q8sM 6oYa9EFnq2JAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCacKXkgAKCRCIgE5vWV1S Mq4kD/wOYxLZGglFGcP1qoL6GdhHXQO/bjAa/srPJEh7UjC7KC/0tc0ayxEKJfdrGAgrSXGcP8C hA4gclNC7vYdcQu2W280HT+hQjL7KRrJ16cPdK6zqO1IEAksvJyiLaYh3VDux74cUyMRUcHTAIp X+nhE/eJLLtQU45xEx/FB4GaxBO1ociPSjkMPRJjsgflDRQNL4UgB+1xKQyS533qnsr18hrfnMz R08DRT1IyxAzQzZu6Z9prSkmYJhQSKLKw8+zGV3hGaSBfdpkwGWGwbIJnzTJ1I2eO2/cf/iGD7k QBVg/3/Fx9w7mVBnmOQe0MqTzL/wkxwrq5+3l1gKHrqfHuQ4llJHKFopPpQV6oRQB5F0ylxe2Sp OD0KISytWmYJhMHCTSldawhC9eeEYopuEplmQEXExGtnjcQcYt6GWkx3rPYBEb09xLoNW+Q4sIo iWPMZiprIlkJTijf/JQ85Z9Kq6oQv+H0vqdmbHTZEXO5f35rQN8qwORuziDKvvPsX5197F9qI1F Wr20d9i8SejoK0uT7ewowtxPGuTX+O+4a2StViFktLGrpAWLc0Sz1bLu54P32cztNLh4HQtVqv+ 5e0Y/fBmUpqzxFOt6PwfGFh8p+1+swNWcWxLomOcdTE8BELjSjEHkTgefMFwp3vSF4JVUymba2l +dkAzDbOX/npvjQ== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 There may be several reasons why you may need to use a certain speed on an I2C bus. E.g. - When several devices are attached to the bus, the speed must be selected according to the slowest device. - Electrical conditions may limit the usable speed on the bus for different reasons. With an I2C multiplexer, it is possible to group the attached devices after their preferred speed by e.g. putting all "slow" devices on a separate channel on the multiplexer. Consider the following topology: .----------. 100kHz .--------. .--------. 400kHz | |--------| dev D1 | | root |--+-----| I2C MUX | '--------' '--------' | | |--. 400kHz .--------. | '----------' '-------| dev D2 | | .--------. '--------' '--| dev D3 | '--------' One requirement with this design is that a multiplexer may only use the same or lower bus speed as its parent. Otherwise, if the multiplexer would have to increase the bus frequency, then all siblings (D3 in this case) would run into a clock speed it may not support. The bus frequency for each channel is set in the devicetree. As the i2c-mux bindings import the i2c-controller schema, the clock-frequency property is already allowed. If no clock-frequency property is set, the channel inherits their parent bus speed. The following example uses dt bindings to illustrate the topology above: i2c { clock-frequency =3D <400000>; i2c-mux { i2c@0 { clock-frequency =3D <100000>; D1 { ... }; }; i2c@1 { D2 { ... }; }; }; D3 { ... } }; Signed-off-by: Marcus Folkesson --- drivers/i2c/i2c-mux.c | 107 ++++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 95 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index d59644e50f14..6b5c9ae1efde 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -36,21 +36,75 @@ struct i2c_mux_priv { u32 chan_id; }; =20 +static int i2c_mux_select_chan(struct i2c_adapter *adap, u32 chan_id, u32 = *oldclock) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + int ret; + + if (priv->adap.clock_hz && priv->adap.clock_hz < parent->clock_hz) { + *oldclock =3D parent->clock_hz; + + if (muxc->mux_locked) + ret =3D i2c_adapter_set_clk_freq(parent, priv->adap.clock_hz); + else + ret =3D __i2c_adapter_set_clk_freq(parent, priv->adap.clock_hz); + + dev_dbg(&adap->dev, "Set clock frequency %uHz on %s\n", + priv->adap.clock_hz, parent->name); + + if (ret) + dev_err(&adap->dev, + "Failed to set clock frequency %uHz on adapter %s: %d\n", + *oldclock, parent->name, ret); + } + + return muxc->select(muxc, priv->chan_id); +} + +static void i2c_mux_deselect_chan(struct i2c_adapter *adap, u32 chan_id, u= 32 oldclock) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + int ret; + + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); + + if (oldclock && oldclock !=3D priv->adap.clock_hz) { + if (muxc->mux_locked) + ret =3D i2c_adapter_set_clk_freq(parent, oldclock); + else + ret =3D __i2c_adapter_set_clk_freq(parent, oldclock); + + dev_dbg(&adap->dev, "Restored clock frequency %uHz on %s\n", + oldclock, parent->name); + + if (ret) + dev_err(&adap->dev, + "Failed to set clock frequency %uHz on adapter %s: %d\n", + oldclock, parent->name, ret); + } +} + static int __i2c_mux_master_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D __i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -61,15 +115,16 @@ static int i2c_mux_master_xfer(struct i2c_adapter *ada= p, struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -82,16 +137,17 @@ static int __i2c_mux_smbus_xfer(struct i2c_adapter *ad= ap, struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D __i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -104,16 +160,17 @@ static int i2c_mux_smbus_xfer(struct i2c_adapter *ada= p, struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -362,6 +419,32 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc, } } =20 + of_property_read_u32(child, "clock-frequency", &priv->adap.clock_hz); + + /* If the mux adapter has no clock-frequency property, inherit from pare= nt */ + if (!priv->adap.clock_hz) + priv->adap.clock_hz =3D parent->clock_hz; + + /* + * Warn if the mux adapter is not parent-locked as + * this may cause issues for some hardware topologies. + */ + if ((priv->adap.clock_hz < parent->clock_hz) && muxc->mux_locked) + dev_warn(muxc->dev, + "channel %u is slower than parent on a non parent-locked mux\n", + chan_id); + + /* We don't support mux adapters faster than their parent */ + if (priv->adap.clock_hz > parent->clock_hz) { + dev_err(muxc->dev, + "channel (%u) is faster (%u) than parent (%u)\n", + chan_id, priv->adap.clock_hz, parent->clock_hz); + + of_node_put(mux_node); + ret =3D -EINVAL; + goto err_free_priv; + } + priv->adap.dev.of_node =3D child; of_node_put(mux_node); } --=20 2.53.0